Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128329
T. Zhao, Chun Zhao, I. Mitrovic, E. G. Lim, Li Yang, Chenghu Qiu, Cezhou Zhao
In this work, solution processed zinc tin oxide semiconductor films were investigated. Different from the widely reported high-temperature and toxic organic solvent-based fabrication process, a low temperature and eco-friendly aqueous solvent-based route was studied. The optimization of electrical performances on field effect mobility and reliability was proved. Moreover, a resistor-loaded inverter was constructed.
{"title":"Facile Route for Low-temperature Eco-friendly Solution Processed ZnSnO Thin-film Transistors","authors":"T. Zhao, Chun Zhao, I. Mitrovic, E. G. Lim, Li Yang, Chenghu Qiu, Cezhou Zhao","doi":"10.1109/IRPS45951.2020.9128329","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128329","url":null,"abstract":"In this work, solution processed zinc tin oxide semiconductor films were investigated. Different from the widely reported high-temperature and toxic organic solvent-based fabrication process, a low temperature and eco-friendly aqueous solvent-based route was studied. The optimization of electrical performances on field effect mobility and reliability was proved. Moreover, a resistor-loaded inverter was constructed.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130736838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129198
T. Grasser, B. Kaczer, B. O’Sullivan, G. Rzepa, B. Stampfer, M. Waltl
While the bias temperature instability has provided many puzzles for more than half a century, the observation that bipolar (+Vg/-Vg) AC stress can lead to larger degradation than DC or unipolar (Vg/0) AC NBTI/PBTI combined, is particularly mysterious. Interestingly, similar observations have been made for oxide breakdown and hot carrier injection. Both have been linked to accelerated hydrogen release from the oxide under alternating positive and negative bias which then causes the creation of near-interface states. Based on these observations, we investigate the phenomenon from the perspective of the recently proposed gate-sided hydrogen release model for BTI. We suggest a mechanism which can explain the accelerated degradation observed during bipolar AC stress and investigate and validate possibilities for mitigating the effect by reducing the oxide volume from which H is released.
{"title":"The Mysterious Bipolar Bias Temperature Stress from the Perspective of Gate-Sided Hydrogen Release","authors":"T. Grasser, B. Kaczer, B. O’Sullivan, G. Rzepa, B. Stampfer, M. Waltl","doi":"10.1109/IRPS45951.2020.9129198","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129198","url":null,"abstract":"While the bias temperature instability has provided many puzzles for more than half a century, the observation that bipolar (+Vg/-Vg) AC stress can lead to larger degradation than DC or unipolar (Vg/0) AC NBTI/PBTI combined, is particularly mysterious. Interestingly, similar observations have been made for oxide breakdown and hot carrier injection. Both have been linked to accelerated hydrogen release from the oxide under alternating positive and negative bias which then causes the creation of near-interface states. Based on these observations, we investigate the phenomenon from the perspective of the recently proposed gate-sided hydrogen release model for BTI. We suggest a mechanism which can explain the accelerated degradation observed during bipolar AC stress and investigate and validate possibilities for mitigating the effect by reducing the oxide volume from which H is released.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115694843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129352
P. Colestock, P. Srinivasan, F. Guarín
5G communication standards brings new promise and also new challenges. While the sub 6 GHz 5G market can leverage existing III-V front end PA solutions, the broad commercialization of CMOS based power generation at millimeter wave frequencies for 5G will chart new territory for reliable power generation. This paper hopes to lay the groundwork for charting the path to success for CMOS millimeter wave PA reliability from the lab to the fab to the field.
{"title":"Silicon Based RF Reliability Challenges for 5G Communications","authors":"P. Colestock, P. Srinivasan, F. Guarín","doi":"10.1109/IRPS45951.2020.9129352","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129352","url":null,"abstract":"5G communication standards brings new promise and also new challenges. While the sub 6 GHz 5G market can leverage existing III-V front end PA solutions, the broad commercialization of CMOS based power generation at millimeter wave frequencies for 5G will chart new territory for reliable power generation. This paper hopes to lay the groundwork for charting the path to success for CMOS millimeter wave PA reliability from the lab to the fab to the field.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114657183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128342
Victor M. van Santen, Simon Thomann, Chaitanya Pasupuleti, P. Genssler, Narendra Gangwar, Uma Sharma, J. Henkel, S. Mahapatra, H. Amrouch
For the first time, we present a study of BTI and HCD degradation in a 32 × 64 cell SRAM array including Sense Amplifiers (SA), Write Drivers (WD) and pre-charging circuitry (one each for 64 columns) stimulated by the workload-induced activity of a commercial processor. In under 2 hours, our fully automated framework employs the extracted activities to create voltage waveforms used in SPICE simulations (SRAM Array, SA, WD) and degrades transistors using their individual exhibited voltages as stimuli in BTI and HCD models. We support different temperatures, supply voltages (including DVFS), SRAM, SA and WD designs.
{"title":"BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array – including Sense Amplifiers and Write Drivers – under Processor Activity","authors":"Victor M. van Santen, Simon Thomann, Chaitanya Pasupuleti, P. Genssler, Narendra Gangwar, Uma Sharma, J. Henkel, S. Mahapatra, H. Amrouch","doi":"10.1109/IRPS45951.2020.9128342","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128342","url":null,"abstract":"For the first time, we present a study of BTI and HCD degradation in a 32 × 64 cell SRAM array including Sense Amplifiers (SA), Write Drivers (WD) and pre-charging circuitry (one each for 64 columns) stimulated by the workload-induced activity of a commercial processor. In under 2 hours, our fully automated framework employs the extracted activities to create voltage waveforms used in SPICE simulations (SRAM Array, SA, WD) and degrades transistors using their individual exhibited voltages as stimuli in BTI and HCD models. We support different temperatures, supply voltages (including DVFS), SRAM, SA and WD designs.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117273569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128224
H. Seki, Y. Nakasaki, Y. Mitani
Modulation of electron trap levels in fluorine (F) incorporated silicon nitride (SiNx) films was investigated by temperature-dependent discharging current transient spectroscopy (DCTS). The shallower trap level is observed in F incorporated SiNx films. F incorporation has more influence on the energy level of traps in the most Si rich SiNx film (x = 1.05) than the other SiNx films (x = 1.11 and 1.23). Considering with physical analyses by secondary ion mass spectrometry (SIMS), X-ray-reflectometry (XRR) and X-ray photoelectron spectroscopy (XPS), we found that depth profiles of F are different among these SiNx films because F atoms can diffuse easily as increasing of Si content. It is plausible that the F incorporation around the charge centroid causes trap level shallowing. It is inferred that F atom terminates Si dangling bond and F-terminated puckered nitrogen vacancy originates the extracted very shallow trap level, which is suggested from first-principles calculations.
{"title":"Further Investigation on Mechanism of Trap Level Modulation in Silicon Nitride Films by Fluorine Incorporation","authors":"H. Seki, Y. Nakasaki, Y. Mitani","doi":"10.1109/IRPS45951.2020.9128224","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128224","url":null,"abstract":"Modulation of electron trap levels in fluorine (F) incorporated silicon nitride (SiNx) films was investigated by temperature-dependent discharging current transient spectroscopy (DCTS). The shallower trap level is observed in F incorporated SiNx films. F incorporation has more influence on the energy level of traps in the most Si rich SiNx film (x = 1.05) than the other SiNx films (x = 1.11 and 1.23). Considering with physical analyses by secondary ion mass spectrometry (SIMS), X-ray-reflectometry (XRR) and X-ray photoelectron spectroscopy (XPS), we found that depth profiles of F are different among these SiNx films because F atoms can diffuse easily as increasing of Si content. It is plausible that the F incorporation around the charge centroid causes trap level shallowing. It is inferred that F atom terminates Si dangling bond and F-terminated puckered nitrogen vacancy originates the extracted very shallow trap level, which is suggested from first-principles calculations.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123452342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129331
T. Uemura, Byungjin Chung, J. Jo, Hai Jiang, Yongsung Ji, T. Jeong, R. Ranjan, Seungbae Lee, H. Rhee, S. Pae, Euncheol Lee, Jaehee Choi, Shotaro Ohnishi, Ken Machida
This paper proposes an alternative method of alpha-irradiation test in flip-chip packages, backside irradiation test in EUV 7nm FinFET SRAM. The backside-test is conducted in backside-ground flip-chips. The sample thickness is measured, and the correlation factor is calculated by Monte-Carlo simulations. The results of backside- and front-side-tests show the dependability of the proposed method.
{"title":"Backside Alpha-Irradiation Test in Flip-Chip Package in EUV 7 nm FinFET SRAM","authors":"T. Uemura, Byungjin Chung, J. Jo, Hai Jiang, Yongsung Ji, T. Jeong, R. Ranjan, Seungbae Lee, H. Rhee, S. Pae, Euncheol Lee, Jaehee Choi, Shotaro Ohnishi, Ken Machida","doi":"10.1109/IRPS45951.2020.9129331","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129331","url":null,"abstract":"This paper proposes an alternative method of alpha-irradiation test in flip-chip packages, backside irradiation test in EUV 7nm FinFET SRAM. The backside-test is conducted in backside-ground flip-chips. The sample thickness is measured, and the correlation factor is calculated by Monte-Carlo simulations. The results of backside- and front-side-tests show the dependability of the proposed method.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123593448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128359
Yao‐Feng Chang, J. O'Donnell, T. Acosta, R. Kotlyar, Albert B. Chen, Pedro A. Quintero, N. Strutt, O. Golonzka, C. Connor, J. Hicks
For the first time, a comprehensive study of embedded nonvolatile memory (eNVM) resistive random access memory (RRAM) reliability performance and modeling in 22FFL FinFET technology is presented. RRAM retention relaxation is characterized and modeled, and product-level reliability performance is assessed for 105°C-10yrs-1k life time capability within error-correcting code (ECC) budget. Endurance with automotive grade II (-40°C-105°C) and 5x JEDEC reflow is demonstrated for potential automotive SoC applications. The resistance-based retention follows oxygen vacancy diffusion relaxation (time) and Arrhenius procedure (temperature), providing insight into empirical models and improving long-term reliability prediction accuracy.
{"title":"eNVM RRAM reliability performance and modeling in 22FFL FinFET technology","authors":"Yao‐Feng Chang, J. O'Donnell, T. Acosta, R. Kotlyar, Albert B. Chen, Pedro A. Quintero, N. Strutt, O. Golonzka, C. Connor, J. Hicks","doi":"10.1109/IRPS45951.2020.9128359","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128359","url":null,"abstract":"For the first time, a comprehensive study of embedded nonvolatile memory (eNVM) resistive random access memory (RRAM) reliability performance and modeling in 22FFL FinFET technology is presented. RRAM retention relaxation is characterized and modeled, and product-level reliability performance is assessed for 105°C-10yrs-1k life time capability within error-correcting code (ECC) budget. Endurance with automotive grade II (-40°C-105°C) and 5x JEDEC reflow is demonstrated for potential automotive SoC applications. The resistance-based retention follows oxygen vacancy diffusion relaxation (time) and Arrhenius procedure (temperature), providing insight into empirical models and improving long-term reliability prediction accuracy.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122028940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128327
S. Tyaginov, A. Grill, M. Vandemaele, T. Grasser, G. Hellings, A. Makarov, M. Jech, D. Linten, B. Kaczer
We develop and validate a fully analytical model for hot-carrier degradation based on a thorough description of the physical picture behind this reliability phenomenon. This approach captures and links carrier transport, modeling of the Si-H bond-breakage mechanisms, and simulations of the degraded devices. All quantities evaluated within the model are described by analytical expressions and time consuming TCAD simulations are therefore avoided. We show that the model can capture measured dependencies of the normalized linear drain current change on stress time with good accuracy.
{"title":"A Compact Physics Analytical Model for Hot-Carrier Degradation","authors":"S. Tyaginov, A. Grill, M. Vandemaele, T. Grasser, G. Hellings, A. Makarov, M. Jech, D. Linten, B. Kaczer","doi":"10.1109/IRPS45951.2020.9128327","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128327","url":null,"abstract":"We develop and validate a fully analytical model for hot-carrier degradation based on a thorough description of the physical picture behind this reliability phenomenon. This approach captures and links carrier transport, modeling of the Si-H bond-breakage mechanisms, and simulations of the degraded devices. All quantities evaluated within the model are described by analytical expressions and time consuming TCAD simulations are therefore avoided. We show that the model can capture measured dependencies of the normalized linear drain current change on stress time with good accuracy.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"9 22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124682019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129246
A. Lesniewska, P. Roussel, D. Tierno, V. Vega-Gonzalez, M. V. Veen, P. Verdonck, N. Jourdan, Christopher J. Wilson, Z. Tökei, K. Croes
We evaluate the dielectric reliability performance of 21 nm pitch interconnects integrated in a dense low-k and using a barrierless Ru fill scheme. We show our line-to-line and tip-to-tip TDDB pass 10 years of lifetime at 0.75 V for technology relevant line lengths and number of tips, respectively. Intrinsic dielectric breakdown without metal drift is demonstrated using BTS-TVS measurements. We also investigate the impact of dielectric scaling towards lower dimensions using planar capacitor structures. We observe an increasing field acceleration factor with decreasing thickness possibly suggesting different, slower, degradation mechanisms being present in the thinner dielectrics leading towards more reliability margin for scaled interconnects.
{"title":"Dielectric Reliability Study of 21 nm Pitch Interconnects with Barrierless Ru Fill","authors":"A. Lesniewska, P. Roussel, D. Tierno, V. Vega-Gonzalez, M. V. Veen, P. Verdonck, N. Jourdan, Christopher J. Wilson, Z. Tökei, K. Croes","doi":"10.1109/IRPS45951.2020.9129246","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129246","url":null,"abstract":"We evaluate the dielectric reliability performance of 21 nm pitch interconnects integrated in a dense low-k and using a barrierless Ru fill scheme. We show our line-to-line and tip-to-tip TDDB pass 10 years of lifetime at 0.75 V for technology relevant line lengths and number of tips, respectively. Intrinsic dielectric breakdown without metal drift is demonstrated using BTS-TVS measurements. We also investigate the impact of dielectric scaling towards lower dimensions using planar capacitor structures. We observe an increasing field acceleration factor with decreasing thickness possibly suggesting different, slower, degradation mechanisms being present in the thinner dielectrics leading towards more reliability margin for scaled interconnects.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128313349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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