Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128328
Chen Wu, A. Chasin, S. Demuynck, N. Horiguchi, K. Croes
To achieve robust middle of line interconnects in advanced CMOS technology, electrical reliability of the dielectric stacks consisting of low-k spacer and nitride spacer dielectrics between gate metal and local interconnect metal is critical. To mimic this dielectric system, this work focuses on the stacks having SiN on top of SiO2 with the total thickness below 15nm. The electrical conduction is proven to be determined by the electron injection interface. Additional defects are found in the SiN layer close to the SiO2 interface as the result of SiN deposition on SiO2. These defects assist electron transport when the electrons are injected from the SiN side. In the time dependent dielectric breakdown assessment, the Weibull slope, β, behaves differently under positively and negatively biased stresses where +β depends on both SiO2 and SiN thicknesses, but -β is mainly dependent on the SiO2 thickness and is only weakly dependent on the SiN thickness. The field acceleration factor, +m and -m, show similar relations versus the equivalent SiN thickness. Due to the much higher electric field distributed in the low-k layer in dielectric stacks, the performance of low-k spacer layer is proven to be crucial for the stack reliability.
{"title":"Conduction and Breakdown Mechanisms in Low-k Spacer and Nitride Spacer Dielectric Stacks in Middle of Line Interconnects","authors":"Chen Wu, A. Chasin, S. Demuynck, N. Horiguchi, K. Croes","doi":"10.1109/IRPS45951.2020.9128328","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128328","url":null,"abstract":"To achieve robust middle of line interconnects in advanced CMOS technology, electrical reliability of the dielectric stacks consisting of low-k spacer and nitride spacer dielectrics between gate metal and local interconnect metal is critical. To mimic this dielectric system, this work focuses on the stacks having SiN on top of SiO2 with the total thickness below 15nm. The electrical conduction is proven to be determined by the electron injection interface. Additional defects are found in the SiN layer close to the SiO2 interface as the result of SiN deposition on SiO2. These defects assist electron transport when the electrons are injected from the SiN side. In the time dependent dielectric breakdown assessment, the Weibull slope, β, behaves differently under positively and negatively biased stresses where +β depends on both SiO2 and SiN thicknesses, but -β is mainly dependent on the SiO2 thickness and is only weakly dependent on the SiN thickness. The field acceleration factor, +m and -m, show similar relations versus the equivalent SiN thickness. Due to the much higher electric field distributed in the low-k layer in dielectric stacks, the performance of low-k spacer layer is proven to be crucial for the stack reliability.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122472637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129515
K. Hwang, S. Karalkar, Vishal Ganesan, Sevashanmugam Marimuthu, A. Zaka, T. Herrmann, Bhoopendra Singh, R. Gauthier
An effective design for self-protection medium voltage nMOS with modification of drain junction in 28nm high voltage CMOS technology is presented. Pull down nMOS of the output driver is the main electrostatic discharge path. Design of Source/Drain junction of baseline device can be optimized for only current driving ability and DC reliability. Sometimes this design is not sufficient as ESD protection device including Self-protection output driver device which can be possible long-term reliability issue after ESD stress. Modification of N+ drain junction with LDD spacer mask shows improved ESD performance by reducing the electric field at poly/drain overlap region and, spreading the ESD current path between drain and source. TLP, HBM, DC-IV and, HCI characterization techniques were used to verify the structure and, TCAD simulations were used to examine failure analysis.
{"title":"Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology","authors":"K. Hwang, S. Karalkar, Vishal Ganesan, Sevashanmugam Marimuthu, A. Zaka, T. Herrmann, Bhoopendra Singh, R. Gauthier","doi":"10.1109/IRPS45951.2020.9129515","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129515","url":null,"abstract":"An effective design for self-protection medium voltage nMOS with modification of drain junction in 28nm high voltage CMOS technology is presented. Pull down nMOS of the output driver is the main electrostatic discharge path. Design of Source/Drain junction of baseline device can be optimized for only current driving ability and DC reliability. Sometimes this design is not sufficient as ESD protection device including Self-protection output driver device which can be possible long-term reliability issue after ESD stress. Modification of N+ drain junction with LDD spacer mask shows improved ESD performance by reducing the electric field at poly/drain overlap region and, spreading the ESD current path between drain and source. TLP, HBM, DC-IV and, HCI characterization techniques were used to verify the structure and, TCAD simulations were used to examine failure analysis.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127690638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129618
W. Hubbard, Z. Lingley, J. Theiss, M. Brodie, B. Foran
Electron beam-induced current (EBIC) data, acquired in a scanning transmission electron microscope (STEM), are presented in the context of microelectronic device reliability. The mechanisms causing, and applications of, three distinct EBIC modes are discussed along with the requirements and challenges of preparing STEM EBIC-compatible samples with a focused ion beam (FIB). STEM EBIC images are acquired from samples extracted, by FIB lift-out, from off-the-shelf multilayer ceramic capacitors (MLCCs). These STEM EBIC images show two different EBIC modes simultaneously, which map both resistance and local electric fields. Observed variability in the distribution of BaTiO3 grain boundary resistivities is compared to predicted wear-out and reliability models. These techniques may be extended to other electronic components to map electronic signals that are otherwise inaccessible at high-resolution.
{"title":"STEM EBIC for High-Resolution Electronic Characterization","authors":"W. Hubbard, Z. Lingley, J. Theiss, M. Brodie, B. Foran","doi":"10.1109/IRPS45951.2020.9129618","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129618","url":null,"abstract":"Electron beam-induced current (EBIC) data, acquired in a scanning transmission electron microscope (STEM), are presented in the context of microelectronic device reliability. The mechanisms causing, and applications of, three distinct EBIC modes are discussed along with the requirements and challenges of preparing STEM EBIC-compatible samples with a focused ion beam (FIB). STEM EBIC images are acquired from samples extracted, by FIB lift-out, from off-the-shelf multilayer ceramic capacitors (MLCCs). These STEM EBIC images show two different EBIC modes simultaneously, which map both resistance and local electric fields. Observed variability in the distribution of BaTiO3 grain boundary resistivities is compared to predicted wear-out and reliability models. These techniques may be extended to other electronic components to map electronic signals that are otherwise inaccessible at high-resolution.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132760474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129479
W. Arfaoui, G. Bossu, A. Muehlhoff, D. Lipp, R. Manuwald, T. Chen, T. Nigam, M. Siddabathula
Although technology scaling to deep submicron enable higher degrees of semiconductor integration, highly integrated circuit have become increasingly sensitive to the slightest parameter drift. One of the main causes of parameter degradation in recent technologies is the Hot Carrier Injection (HCI), a progressive wear out phenomenon whose understanding and modeling has become mandatory in new CMOS nodes. Therefore, we present in this paper a new HCI reliability model for Fully Depleted Silicon On Insulator (FDSOI) MOSFETs which covers the RF/mmWave (Radiofrequency /millimeter wave) applications taking into account back bias operation.
{"title":"A Novel HCI Reliability Model for RF/mmWave Applications in FDSOI Technology","authors":"W. Arfaoui, G. Bossu, A. Muehlhoff, D. Lipp, R. Manuwald, T. Chen, T. Nigam, M. Siddabathula","doi":"10.1109/IRPS45951.2020.9129479","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129479","url":null,"abstract":"Although technology scaling to deep submicron enable higher degrees of semiconductor integration, highly integrated circuit have become increasingly sensitive to the slightest parameter drift. One of the main causes of parameter degradation in recent technologies is the Hot Carrier Injection (HCI), a progressive wear out phenomenon whose understanding and modeling has become mandatory in new CMOS nodes. Therefore, we present in this paper a new HCI reliability model for Fully Depleted Silicon On Insulator (FDSOI) MOSFETs which covers the RF/mmWave (Radiofrequency /millimeter wave) applications taking into account back bias operation.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133589599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128352
T. Bonifield, Honglin Guo, Jeff West, H. Shichijo, Talha Tahir
Reinforced isolation provides protection of equipment and operators that interact with high voltage domains. Standards that define it have evolved over time from those that require only partial discharge to confirm reliability at the high voltage operating conditions, to those that also require a time dependent dielectric breakdown model (TDDB) for verifying reliable working voltage. In this paper we assess the impact of AC frequency, waveform, and rise and fall times on lifetime, which are important parameters that are not included in the current standards.
{"title":"High Frequency TDDB of Reinforced Isolation Dielectric Systems","authors":"T. Bonifield, Honglin Guo, Jeff West, H. Shichijo, Talha Tahir","doi":"10.1109/IRPS45951.2020.9128352","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128352","url":null,"abstract":"Reinforced isolation provides protection of equipment and operators that interact with high voltage domains. Standards that define it have evolved over time from those that require only partial discharge to confirm reliability at the high voltage operating conditions, to those that also require a time dependent dielectric breakdown model (TDDB) for verifying reliable working voltage. In this paper we assess the impact of AC frequency, waveform, and rise and fall times on lifetime, which are important parameters that are not included in the current standards.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131933874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128309
Wen Yang, Jiann-Shiun Yuan, Balakrishnan Krishnan, A. Tzou, W. Yeh
his paper investigates the substrate bias effects on a monolithically integrated half-bridge fabricated using lateral GaN-on-Si technology. The dynamic characteristics, including dynamic Ron degradation and gate charge (Qg) shift, are presented for both high- and low-side GaN power devices. Compared to the grounded substrate, significant dynamic Ron degradations and decreased Qg are observed in high-side GaN power devices under negative DC substrate biases. Pulse-mode substrate biasing has also been studied with suppressed degradation by eliminating the cross-talk effect. The trade-off between dynamic Ron degradation and Qg shift has been explored under different switching frequencies for a monolithically integrated GaN half-bridge.
{"title":"Substrate Bias Effect on Dynamic Characteristics of a Monolithically Integrated GaN Half-Bridge","authors":"Wen Yang, Jiann-Shiun Yuan, Balakrishnan Krishnan, A. Tzou, W. Yeh","doi":"10.1109/IRPS45951.2020.9128309","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128309","url":null,"abstract":"his paper investigates the substrate bias effects on a monolithically integrated half-bridge fabricated using lateral GaN-on-Si technology. The dynamic characteristics, including dynamic Ron degradation and gate charge (Qg) shift, are presented for both high- and low-side GaN power devices. Compared to the grounded substrate, significant dynamic Ron degradations and decreased Qg are observed in high-side GaN power devices under negative DC substrate biases. Pulse-mode substrate biasing has also been studied with suppressed degradation by eliminating the cross-talk effect. The trade-off between dynamic Ron degradation and Qg shift has been explored under different switching frequencies for a monolithically integrated GaN half-bridge.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115090675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128324
Dongyoung Kim, Adam J. Morgan, Nick Yun, Woongje Sung, A. Agarwal, R. Kaplar
Non-Isothermal simulations to understand Short-Circuit (SC) behavior of SiC MOSFETs were performed. Using the established model, structures to enhance the SC ruggedness were proposed. Thin gate oxide and a narrow JFET region are shown to reduce saturation current enhancing SC ruggedness without increasing Ron,sp. Results indicate thin gate oxide offers moderate improvement in SC capability, at the cost of increased Cgs. In contrast, narrow JFET region provides much improved (2×) SC ruggedness, as well as lower Ron,sp, with no negative impact on Cgs.
{"title":"Non-Isothermal Simulations to Optimize SiC MOSFETs for Enhanced Short-Circuit Ruggedness","authors":"Dongyoung Kim, Adam J. Morgan, Nick Yun, Woongje Sung, A. Agarwal, R. Kaplar","doi":"10.1109/IRPS45951.2020.9128324","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128324","url":null,"abstract":"Non-Isothermal simulations to understand Short-Circuit (SC) behavior of SiC MOSFETs were performed. Using the established model, structures to enhance the SC ruggedness were proposed. Thin gate oxide and a narrow JFET region are shown to reduce saturation current enhancing SC ruggedness without increasing Ron,sp. Results indicate thin gate oxide offers moderate improvement in SC capability, at the cost of increased Cgs. In contrast, narrow JFET region provides much improved (2×) SC ruggedness, as well as lower Ron,sp, with no negative impact on Cgs.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115626141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128349
J. Michl, A. Grill, D. Claes, G. Rzepa, B. Kaczer, D. Linten, I. Radu, T. Grasser, M. Waltl
Electronics operating at cryogenic temperatures is crucial for scaling up single qubits to complex quantum computing systems. There are various studies concentrating on the characterization of advanced CMOS technologies operating at low temperatures, but so far little attention has been paid to reliability issues. Even though classical models predict BTI to freeze out, our measurements clearly reveal a significant threshold voltage degradation down to 4 K. This effect can be consistently explained by considering a quantum mechanical extension for the description of charge transitions in the transistor, which leads to an effective barrier lowering towards cryogenic temperatures. We implement this model in our reliability simulator Comphy and are finally able to fully explain BTI behaviour at temperatures down to 4 K.
{"title":"Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures","authors":"J. Michl, A. Grill, D. Claes, G. Rzepa, B. Kaczer, D. Linten, I. Radu, T. Grasser, M. Waltl","doi":"10.1109/IRPS45951.2020.9128349","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128349","url":null,"abstract":"Electronics operating at cryogenic temperatures is crucial for scaling up single qubits to complex quantum computing systems. There are various studies concentrating on the characterization of advanced CMOS technologies operating at low temperatures, but so far little attention has been paid to reliability issues. Even though classical models predict BTI to freeze out, our measurements clearly reveal a significant threshold voltage degradation down to 4 K. This effect can be consistently explained by considering a quantum mechanical extension for the description of charge transitions in the transistor, which leads to an effective barrier lowering towards cryogenic temperatures. We implement this model in our reliability simulator Comphy and are finally able to fully explain BTI behaviour at temperatures down to 4 K.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"6 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113969702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128220
M. Sampath, D. Morisette, J. A. Cooper
SiC unipolar power devices have ~350× lower drift region resistance than silicon devices at a given blocking voltage, but their higher power density reduces their short-circuit withstand time (SCWT). We propose to increase the SCWT of SiC MOSFETs and IGBTs by reducing their oxide thickness and gate drive voltage, keeping the gate charge and oxide field constant. This increases their SCWT with no impact on on-state or blocking performance, and requires no changes to existing designs or mask sets.
{"title":"Constant-Gate-Charge Scaling for Increased Short-Circuit Withstand Time in SiC Power Devices","authors":"M. Sampath, D. Morisette, J. A. Cooper","doi":"10.1109/IRPS45951.2020.9128220","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128220","url":null,"abstract":"SiC unipolar power devices have ~350× lower drift region resistance than silicon devices at a given blocking voltage, but their higher power density reduces their short-circuit withstand time (SCWT). We propose to increase the SCWT of SiC MOSFETs and IGBTs by reducing their oxide thickness and gate drive voltage, keeping the gate charge and oxide field constant. This increases their SCWT with no impact on on-state or blocking performance, and requires no changes to existing designs or mask sets.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122876723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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