Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128328
Chen Wu, A. Chasin, S. Demuynck, N. Horiguchi, K. Croes
To achieve robust middle of line interconnects in advanced CMOS technology, electrical reliability of the dielectric stacks consisting of low-k spacer and nitride spacer dielectrics between gate metal and local interconnect metal is critical. To mimic this dielectric system, this work focuses on the stacks having SiN on top of SiO2 with the total thickness below 15nm. The electrical conduction is proven to be determined by the electron injection interface. Additional defects are found in the SiN layer close to the SiO2 interface as the result of SiN deposition on SiO2. These defects assist electron transport when the electrons are injected from the SiN side. In the time dependent dielectric breakdown assessment, the Weibull slope, β, behaves differently under positively and negatively biased stresses where +β depends on both SiO2 and SiN thicknesses, but -β is mainly dependent on the SiO2 thickness and is only weakly dependent on the SiN thickness. The field acceleration factor, +m and -m, show similar relations versus the equivalent SiN thickness. Due to the much higher electric field distributed in the low-k layer in dielectric stacks, the performance of low-k spacer layer is proven to be crucial for the stack reliability.
{"title":"Conduction and Breakdown Mechanisms in Low-k Spacer and Nitride Spacer Dielectric Stacks in Middle of Line Interconnects","authors":"Chen Wu, A. Chasin, S. Demuynck, N. Horiguchi, K. Croes","doi":"10.1109/IRPS45951.2020.9128328","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128328","url":null,"abstract":"To achieve robust middle of line interconnects in advanced CMOS technology, electrical reliability of the dielectric stacks consisting of low-k spacer and nitride spacer dielectrics between gate metal and local interconnect metal is critical. To mimic this dielectric system, this work focuses on the stacks having SiN on top of SiO2 with the total thickness below 15nm. The electrical conduction is proven to be determined by the electron injection interface. Additional defects are found in the SiN layer close to the SiO2 interface as the result of SiN deposition on SiO2. These defects assist electron transport when the electrons are injected from the SiN side. In the time dependent dielectric breakdown assessment, the Weibull slope, β, behaves differently under positively and negatively biased stresses where +β depends on both SiO2 and SiN thicknesses, but -β is mainly dependent on the SiO2 thickness and is only weakly dependent on the SiN thickness. The field acceleration factor, +m and -m, show similar relations versus the equivalent SiN thickness. Due to the much higher electric field distributed in the low-k layer in dielectric stacks, the performance of low-k spacer layer is proven to be crucial for the stack reliability.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122472637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129515
K. Hwang, S. Karalkar, Vishal Ganesan, Sevashanmugam Marimuthu, A. Zaka, T. Herrmann, Bhoopendra Singh, R. Gauthier
An effective design for self-protection medium voltage nMOS with modification of drain junction in 28nm high voltage CMOS technology is presented. Pull down nMOS of the output driver is the main electrostatic discharge path. Design of Source/Drain junction of baseline device can be optimized for only current driving ability and DC reliability. Sometimes this design is not sufficient as ESD protection device including Self-protection output driver device which can be possible long-term reliability issue after ESD stress. Modification of N+ drain junction with LDD spacer mask shows improved ESD performance by reducing the electric field at poly/drain overlap region and, spreading the ESD current path between drain and source. TLP, HBM, DC-IV and, HCI characterization techniques were used to verify the structure and, TCAD simulations were used to examine failure analysis.
{"title":"Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology","authors":"K. Hwang, S. Karalkar, Vishal Ganesan, Sevashanmugam Marimuthu, A. Zaka, T. Herrmann, Bhoopendra Singh, R. Gauthier","doi":"10.1109/IRPS45951.2020.9129515","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129515","url":null,"abstract":"An effective design for self-protection medium voltage nMOS with modification of drain junction in 28nm high voltage CMOS technology is presented. Pull down nMOS of the output driver is the main electrostatic discharge path. Design of Source/Drain junction of baseline device can be optimized for only current driving ability and DC reliability. Sometimes this design is not sufficient as ESD protection device including Self-protection output driver device which can be possible long-term reliability issue after ESD stress. Modification of N+ drain junction with LDD spacer mask shows improved ESD performance by reducing the electric field at poly/drain overlap region and, spreading the ESD current path between drain and source. TLP, HBM, DC-IV and, HCI characterization techniques were used to verify the structure and, TCAD simulations were used to examine failure analysis.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127690638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129618
W. Hubbard, Z. Lingley, J. Theiss, M. Brodie, B. Foran
Electron beam-induced current (EBIC) data, acquired in a scanning transmission electron microscope (STEM), are presented in the context of microelectronic device reliability. The mechanisms causing, and applications of, three distinct EBIC modes are discussed along with the requirements and challenges of preparing STEM EBIC-compatible samples with a focused ion beam (FIB). STEM EBIC images are acquired from samples extracted, by FIB lift-out, from off-the-shelf multilayer ceramic capacitors (MLCCs). These STEM EBIC images show two different EBIC modes simultaneously, which map both resistance and local electric fields. Observed variability in the distribution of BaTiO3 grain boundary resistivities is compared to predicted wear-out and reliability models. These techniques may be extended to other electronic components to map electronic signals that are otherwise inaccessible at high-resolution.
{"title":"STEM EBIC for High-Resolution Electronic Characterization","authors":"W. Hubbard, Z. Lingley, J. Theiss, M. Brodie, B. Foran","doi":"10.1109/IRPS45951.2020.9129618","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129618","url":null,"abstract":"Electron beam-induced current (EBIC) data, acquired in a scanning transmission electron microscope (STEM), are presented in the context of microelectronic device reliability. The mechanisms causing, and applications of, three distinct EBIC modes are discussed along with the requirements and challenges of preparing STEM EBIC-compatible samples with a focused ion beam (FIB). STEM EBIC images are acquired from samples extracted, by FIB lift-out, from off-the-shelf multilayer ceramic capacitors (MLCCs). These STEM EBIC images show two different EBIC modes simultaneously, which map both resistance and local electric fields. Observed variability in the distribution of BaTiO3 grain boundary resistivities is compared to predicted wear-out and reliability models. These techniques may be extended to other electronic components to map electronic signals that are otherwise inaccessible at high-resolution.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132760474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129479
W. Arfaoui, G. Bossu, A. Muehlhoff, D. Lipp, R. Manuwald, T. Chen, T. Nigam, M. Siddabathula
Although technology scaling to deep submicron enable higher degrees of semiconductor integration, highly integrated circuit have become increasingly sensitive to the slightest parameter drift. One of the main causes of parameter degradation in recent technologies is the Hot Carrier Injection (HCI), a progressive wear out phenomenon whose understanding and modeling has become mandatory in new CMOS nodes. Therefore, we present in this paper a new HCI reliability model for Fully Depleted Silicon On Insulator (FDSOI) MOSFETs which covers the RF/mmWave (Radiofrequency /millimeter wave) applications taking into account back bias operation.
{"title":"A Novel HCI Reliability Model for RF/mmWave Applications in FDSOI Technology","authors":"W. Arfaoui, G. Bossu, A. Muehlhoff, D. Lipp, R. Manuwald, T. Chen, T. Nigam, M. Siddabathula","doi":"10.1109/IRPS45951.2020.9129479","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129479","url":null,"abstract":"Although technology scaling to deep submicron enable higher degrees of semiconductor integration, highly integrated circuit have become increasingly sensitive to the slightest parameter drift. One of the main causes of parameter degradation in recent technologies is the Hot Carrier Injection (HCI), a progressive wear out phenomenon whose understanding and modeling has become mandatory in new CMOS nodes. Therefore, we present in this paper a new HCI reliability model for Fully Depleted Silicon On Insulator (FDSOI) MOSFETs which covers the RF/mmWave (Radiofrequency /millimeter wave) applications taking into account back bias operation.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133589599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128352
T. Bonifield, Honglin Guo, Jeff West, H. Shichijo, Talha Tahir
Reinforced isolation provides protection of equipment and operators that interact with high voltage domains. Standards that define it have evolved over time from those that require only partial discharge to confirm reliability at the high voltage operating conditions, to those that also require a time dependent dielectric breakdown model (TDDB) for verifying reliable working voltage. In this paper we assess the impact of AC frequency, waveform, and rise and fall times on lifetime, which are important parameters that are not included in the current standards.
{"title":"High Frequency TDDB of Reinforced Isolation Dielectric Systems","authors":"T. Bonifield, Honglin Guo, Jeff West, H. Shichijo, Talha Tahir","doi":"10.1109/IRPS45951.2020.9128352","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128352","url":null,"abstract":"Reinforced isolation provides protection of equipment and operators that interact with high voltage domains. Standards that define it have evolved over time from those that require only partial discharge to confirm reliability at the high voltage operating conditions, to those that also require a time dependent dielectric breakdown model (TDDB) for verifying reliable working voltage. In this paper we assess the impact of AC frequency, waveform, and rise and fall times on lifetime, which are important parameters that are not included in the current standards.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131933874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128358
E. Zanoni, M. Meneghini, G. Meneghesso, F. Rampazzo, D. Marcon, V. G. Zhan, F. Chiocchetta, A. Graff, F. Altmann, M. Simon-Najasek, D. Poppitz
This paper reviews failure modes and mechanisms of 0.5 μm, 0.25 μm and 0.15 μm AlGaN/GaN HEMTs for microwave and millimeter-wave applications. Early devices adopting Ni/Pt/Au metallization were found to be affected by sidewall interdiffusion of Au and O, followed by electrochemical oxidation of AlGaN, a problem which was solved by adopting a new metallization and passivation scheme providing 0.25 μm devices capable of withstanding 24h at VDS = 60V, on-state, Tch = 375°C with no failure. 4000 h long-term thermal storage tests with no bias identified a non-monotonic behaviour of gate Schottky barrier height, causing a temporary increase of gate leakage current which presented no risk for device reliability. Beside contact-related degradation mechanisms, hot electron effects become increasingly more relevant during DC life tests (inducing a 10% increase of on-resistance), rf tests (creating or re-activating deep levels, which increase current-collapse and reduce rf output power and gain). RF tests are the harshest ones for hot-electron degradation, which represents the limiting factor for GaN HEMTs having LG ≤ 0.15 μm.
{"title":"Reliability Physics of GaN HEMT Microwave Devices: The Age of Scaling","authors":"E. Zanoni, M. Meneghini, G. Meneghesso, F. Rampazzo, D. Marcon, V. G. Zhan, F. Chiocchetta, A. Graff, F. Altmann, M. Simon-Najasek, D. Poppitz","doi":"10.1109/IRPS45951.2020.9128358","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128358","url":null,"abstract":"This paper reviews failure modes and mechanisms of 0.5 μm, 0.25 μm and 0.15 μm AlGaN/GaN HEMTs for microwave and millimeter-wave applications. Early devices adopting Ni/Pt/Au metallization were found to be affected by sidewall interdiffusion of Au and O, followed by electrochemical oxidation of AlGaN, a problem which was solved by adopting a new metallization and passivation scheme providing 0.25 μm devices capable of withstanding 24h at VDS = 60V, on-state, Tch = 375°C with no failure. 4000 h long-term thermal storage tests with no bias identified a non-monotonic behaviour of gate Schottky barrier height, causing a temporary increase of gate leakage current which presented no risk for device reliability. Beside contact-related degradation mechanisms, hot electron effects become increasingly more relevant during DC life tests (inducing a 10% increase of on-resistance), rf tests (creating or re-activating deep levels, which increase current-collapse and reduce rf output power and gain). RF tests are the harshest ones for hot-electron degradation, which represents the limiting factor for GaN HEMTs having LG ≤ 0.15 μm.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125599647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129517
L. Soriano, H. Valencia, K. Sun, R. Nelson
Radiation-hard semiconductor devices are becoming more important for a growing number of nuclear and space applications. Gallium Nitride (GaN) semiconductor devices can be highly beneficial in this regard. In this paper, we report the electrical performance of multiple AlGaN/GaN deep UV LEDs irradiated by high fluence fast neutrons. The irradiation experiment was conducted in a newly enhanced beamline at the Los Alamos Neutron Science Center (LANSCE) from 2014-2016 with a maximum fluence of 2.41x1013 neutrons/cm2 over a 3-year span, in an temperature varying, semi-open outdoor housing. We continuously monitored the I-V characteristics of all GaN devices, and showed that they maintained proper I-V behaviors as the neutron fluence increased. Extensive data analysis further shows that effects of neutron irradiation fluence increment in a given day are actually smaller than that induced by daily temperature variation. Our experimental results facilitate the design of diagnostics systems such as multi-pixel imagers for high energy density physics experiments, and complex space electronics that must survive through both high fluence radiation and large orbital temperature variations.
{"title":"Fast Neutron Irradiation Effects on Multiple Gallium Nitride (GaN) Device Reliability in Presence of Ambient Variations","authors":"L. Soriano, H. Valencia, K. Sun, R. Nelson","doi":"10.1109/IRPS45951.2020.9129517","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129517","url":null,"abstract":"Radiation-hard semiconductor devices are becoming more important for a growing number of nuclear and space applications. Gallium Nitride (GaN) semiconductor devices can be highly beneficial in this regard. In this paper, we report the electrical performance of multiple AlGaN/GaN deep UV LEDs irradiated by high fluence fast neutrons. The irradiation experiment was conducted in a newly enhanced beamline at the Los Alamos Neutron Science Center (LANSCE) from 2014-2016 with a maximum fluence of 2.41x1013 neutrons/cm2 over a 3-year span, in an temperature varying, semi-open outdoor housing. We continuously monitored the I-V characteristics of all GaN devices, and showed that they maintained proper I-V behaviors as the neutron fluence increased. Extensive data analysis further shows that effects of neutron irradiation fluence increment in a given day are actually smaller than that induced by daily temperature variation. Our experimental results facilitate the design of diagnostics systems such as multi-pixel imagers for high energy density physics experiments, and complex space electronics that must survive through both high fluence radiation and large orbital temperature variations.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134620122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128816
N. Zagni, A. Chini, F. Puglisi, P. Pavan, M. Meneghini, G. Meneghesso, E. Zanoni, G. Verzellesi
In this paper, we present simulation results that reproduce stress and recovery experiments in Carbon-doped power GaN MOS-HEMTs and explain the associated RON increase and decrease as the result of the emission, redistribution and re-trapping of holes within the Carbon-doped buffer. The proposed model can straightforwardly clarify the beneficial impact of the recently proposed p-type drain contact on RON degradation as being a consequence of enhanced hole trapping and reduced negative trapped charge within the buffer during stress.
在本文中，我们给出了模拟结果，再现了碳掺杂功率GaN mos - hemt的应力和恢复实验，并解释了碳掺杂缓冲中空穴的发射、再分配和重新捕获导致的相关RON的增加和减少。所提出的模型可以直接阐明最近提出的p型漏接触对RON降解的有益影响，因为在应力作用下，缓冲层内的空穴捕获增强，负电荷捕获减少。
{"title":"Trap Dynamics Model Explaining the RON Stress/Recovery Behavior in Carbon-Doped Power AlGaN/GaN MOS-HEMTs","authors":"N. Zagni, A. Chini, F. Puglisi, P. Pavan, M. Meneghini, G. Meneghesso, E. Zanoni, G. Verzellesi","doi":"10.1109/IRPS45951.2020.9128816","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128816","url":null,"abstract":"In this paper, we present simulation results that reproduce stress and recovery experiments in Carbon-doped power GaN MOS-HEMTs and explain the associated RON increase and decrease as the result of the emission, redistribution and re-trapping of holes within the Carbon-doped buffer. The proposed model can straightforwardly clarify the beneficial impact of the recently proposed p-type drain contact on RON degradation as being a consequence of enhanced hole trapping and reduced negative trapped charge within the buffer during stress.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133461329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129093
Yang Wang, Chen Wang, Tao Chen, Hao Liu, Chinte Kuo, Ke Zhou, Bin. F. Yin, Lin Chen, Qingqing Sun
In this work, we investigated Bias Temperature Instability under front-plane and back-plane stress based on 22 nm gate-last FDSOI MOSFETs. The front-plane stress, which was twice the operation voltage, was applied to gate under 25 oC and 125 oC, while the back-plane stress, which was under similar electric field of front-plane stress, was applied to back-gate. The DC I-V measurement was carried out after the removal of the stress. For both nMOSFETs and pMOSFETs, the degradation of Id,lin and Id,sat, and the Vth shift were calculated to measure the deterioration of the devices. The results demonstrated that under similar electric field, the degradation caused by back-plane stress was more severe than that of front-plane stress.
{"title":"Front-plane and Back-plane Bias Temperature Instability of 22 nm Gate-last FDSOI MOSFETs","authors":"Yang Wang, Chen Wang, Tao Chen, Hao Liu, Chinte Kuo, Ke Zhou, Bin. F. Yin, Lin Chen, Qingqing Sun","doi":"10.1109/IRPS45951.2020.9129093","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129093","url":null,"abstract":"In this work, we investigated Bias Temperature Instability under front-plane and back-plane stress based on 22 nm gate-last FDSOI MOSFETs. The front-plane stress, which was twice the operation voltage, was applied to gate under 25 oC and 125 oC, while the back-plane stress, which was under similar electric field of front-plane stress, was applied to back-gate. The DC I-V measurement was carried out after the removal of the stress. For both nMOSFETs and pMOSFETs, the degradation of Id,lin and Id,sat, and the Vth shift were calculated to measure the deterioration of the devices. The results demonstrated that under similar electric field, the degradation caused by back-plane stress was more severe than that of front-plane stress.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114939819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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