Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128220
M. Sampath, D. Morisette, J. A. Cooper
SiC unipolar power devices have ~350× lower drift region resistance than silicon devices at a given blocking voltage, but their higher power density reduces their short-circuit withstand time (SCWT). We propose to increase the SCWT of SiC MOSFETs and IGBTs by reducing their oxide thickness and gate drive voltage, keeping the gate charge and oxide field constant. This increases their SCWT with no impact on on-state or blocking performance, and requires no changes to existing designs or mask sets.
{"title":"Constant-Gate-Charge Scaling for Increased Short-Circuit Withstand Time in SiC Power Devices","authors":"M. Sampath, D. Morisette, J. A. Cooper","doi":"10.1109/IRPS45951.2020.9128220","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128220","url":null,"abstract":"SiC unipolar power devices have ~350× lower drift region resistance than silicon devices at a given blocking voltage, but their higher power density reduces their short-circuit withstand time (SCWT). We propose to increase the SCWT of SiC MOSFETs and IGBTs by reducing their oxide thickness and gate drive voltage, keeping the gate charge and oxide field constant. This increases their SCWT with no impact on on-state or blocking performance, and requires no changes to existing designs or mask sets.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122876723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128227
D. Habersat, A. Lelis, R. Green
The threshold voltage hysteresis seen in SiC MOSFETs complicates the direct use of qualification standards such as AECQ101 for high-temperature gate-bias effects. We review approaches that are appropriate for use in a production environment and can accommodate this effect, comparing their efficacy. Our findings show that in situ hysteresis measurements can be nearly as effective as those made ex situ, and that threshold instability in modern SiC MOSFETs is more performance matter than reliability problem.
{"title":"Towards a Robust Approach to Threshold Voltage Characterization and High Temperature Gate Bias Qualification","authors":"D. Habersat, A. Lelis, R. Green","doi":"10.1109/IRPS45951.2020.9128227","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128227","url":null,"abstract":"The threshold voltage hysteresis seen in SiC MOSFETs complicates the direct use of qualification standards such as AECQ101 for high-temperature gate-bias effects. We review approaches that are appropriate for use in a production environment and can accommodate this effect, comparing their efficacy. Our findings show that in situ hysteresis measurements can be nearly as effective as those made ex situ, and that threshold instability in modern SiC MOSFETs is more performance matter than reliability problem.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130216601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129530
Rui Zhang, Zhaocheng Liu, Kexin Yang, Taizhi Liu, W. Cai, L. Milor
A convenient method based on deep neural networks and an evolutionary algorithm is proposed for the inverse design of FinFET SRAM cells. Inverse design helps designers who have less device physics knowledge obtain cell configurations that provide the desired performance metrics under selected wearout conditions, such as a set specific stress time and use scenario that creates a specific activity level (duty cycle and transition rate). The cell configurations being considered consists of various process parameters, such as gate length and fin height, in the presence of variations due to process and wearout. The front-end mechanisms related to wearout include negative bias temperature instability (NBTI), hot carrier injection (HCI), and random telegraph noise (RTN). The process of inverse design is achieved quickly and at good accuracy.
{"title":"Inverse Design of FinFET SRAM Cells","authors":"Rui Zhang, Zhaocheng Liu, Kexin Yang, Taizhi Liu, W. Cai, L. Milor","doi":"10.1109/IRPS45951.2020.9129530","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129530","url":null,"abstract":"A convenient method based on deep neural networks and an evolutionary algorithm is proposed for the inverse design of FinFET SRAM cells. Inverse design helps designers who have less device physics knowledge obtain cell configurations that provide the desired performance metrics under selected wearout conditions, such as a set specific stress time and use scenario that creates a specific activity level (duty cycle and transition rate). The cell configurations being considered consists of various process parameters, such as gate length and fin height, in the presence of variations due to process and wearout. The front-end mechanisms related to wearout include negative bias temperature instability (NBTI), hot carrier injection (HCI), and random telegraph noise (RTN). The process of inverse design is achieved quickly and at good accuracy.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130116619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128315
C. Mackin, P. Narayanan, S. Ambrogio, H. Tsai, K. Spoon, A. Fasoli, An Chen, A. Friz, R. Shelby, G. Burr
Neuromorphic computing with analog memory can accelerate deep neural networks (DNNs) by enabling multiply-accumulate (MAC) operations to occur within memory. Analog memory, however, presents a number of device-level challenges having macro-implications on the achievable accuracy and reliability of these artificial neural networks. This paper focuses on the adverse effects of conductance drift in phase-change memory (PCM) on network reliability. It is shown that conductance drift can be effectively compensated in a variety of networks by applying a ‘slope correction’ technique to the squashing functions to maintain accuracy/reliability for a period of ~1 year. In addition to conductance drift, PCM poses considerable variability challenges, which impact the accuracy of the initial t0 weights. This paper summarizes recent advances in optimizing t0 weight programming, and provides evidence suggesting that the combination of ‘slope correction’ and programming optimization techniques may allow DNN acceleration using analog memory while maintaining software-equivalent accuracy with reasonable reliability.
{"title":"Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges","authors":"C. Mackin, P. Narayanan, S. Ambrogio, H. Tsai, K. Spoon, A. Fasoli, An Chen, A. Friz, R. Shelby, G. Burr","doi":"10.1109/IRPS45951.2020.9128315","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128315","url":null,"abstract":"Neuromorphic computing with analog memory can accelerate deep neural networks (DNNs) by enabling multiply-accumulate (MAC) operations to occur within memory. Analog memory, however, presents a number of device-level challenges having macro-implications on the achievable accuracy and reliability of these artificial neural networks. This paper focuses on the adverse effects of conductance drift in phase-change memory (PCM) on network reliability. It is shown that conductance drift can be effectively compensated in a variety of networks by applying a ‘slope correction’ technique to the squashing functions to maintain accuracy/reliability for a period of ~1 year. In addition to conductance drift, PCM poses considerable variability challenges, which impact the accuracy of the initial t0 weights. This paper summarizes recent advances in optimizing t0 weight programming, and provides evidence suggesting that the combination of ‘slope correction’ and programming optimization techniques may allow DNN acceleration using analog memory while maintaining software-equivalent accuracy with reasonable reliability.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127660171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128839
Andrew M. Keller, Jared Anderson, M. Wirthlin, Shi-Jie Wen, R. Fung, Conner Chambers
Duplication with compare, a circuit-level fault-detection technique, is used in this study in a partial manner to detect radiation-induced failures in a commercial FPGA-based networking system. A novel approach is taken to overcome challenges presented by multiple clock domains, the use of third-party IP, and the collection of error detection signals dispersed throughout the design. Novel fault injection techniques are also used to evaluate critical regions of the target design. Accelerated neutron radiation testing was performed to evaluate the effectiveness of the applied technique. One design version was able to detect 45% of all failures with the proposed technique applied to 29% of the circuit components within the design. Another design version was able to detect 31% of all failures with the proposed technique applied to only 8% of circuit components.
{"title":"Using Partial Duplication With Compare to Detect Radiation-Induced Failure in a Commercial FPGA-Based Networking System","authors":"Andrew M. Keller, Jared Anderson, M. Wirthlin, Shi-Jie Wen, R. Fung, Conner Chambers","doi":"10.1109/IRPS45951.2020.9128839","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128839","url":null,"abstract":"Duplication with compare, a circuit-level fault-detection technique, is used in this study in a partial manner to detect radiation-induced failures in a commercial FPGA-based networking system. A novel approach is taken to overcome challenges presented by multiple clock domains, the use of third-party IP, and the collection of error detection signals dispersed throughout the design. Novel fault injection techniques are also used to evaluate critical regions of the target design. Accelerated neutron radiation testing was performed to evaluate the effectiveness of the applied technique. One design version was able to detect 45% of all failures with the proposed technique applied to 29% of the circuit components within the design. Another design version was able to detect 31% of all failures with the proposed technique applied to only 8% of circuit components.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"24 26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128466910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128806
A. Helou, M. Tadjer, K. Hobart, P. Raad
GaN high power devices experience substantial self-heating that drives operation temperatures beyond a safe and reliable limit, which has led to the consideration of high conductivity substrates. This study presents a coupled experimental and numerical investigation of the effectiveness of CVD-Diamond as a substrate for GaN HEMTs. The study uses a novel that optimizes a thermal model using an experimentally observed thermal response. The model is then used to assess the effect of the GaN-Di interface on the thermal response of GaN-Di HEMTs, which would serve as a guideline for future developments in GaN and Di growth.
{"title":"Effects of Thermal Boundary Resistance on the Thermal Performance of GaN HEMT on Diamond","authors":"A. Helou, M. Tadjer, K. Hobart, P. Raad","doi":"10.1109/IRPS45951.2020.9128806","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128806","url":null,"abstract":"GaN high power devices experience substantial self-heating that drives operation temperatures beyond a safe and reliable limit, which has led to the consideration of high conductivity substrates. This study presents a coupled experimental and numerical investigation of the effectiveness of CVD-Diamond as a substrate for GaN HEMTs. The study uses a novel that optimizes a thermal model using an experimentally observed thermal response. The model is then used to assess the effect of the GaN-Di interface on the thermal response of GaN-Di HEMTs, which would serve as a guideline for future developments in GaN and Di growth.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128777105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129337
Y. Kim, Allison T. Osmanson, H. Madanipour, C. Kim, P. Thompson, Qiao Chen
This paper investigates the effects of the under bump metallization (UBM) on Electromigration (EM) reliability of SAC solder joints and presents evidence suggestive of hidden mechanisms controlling the EM failure. This conclusion is based on the observation that the EM resistance does not show a monotonic increase with UBM thickness, but rather decreases above a certain critical limit. Since a thicker UBM would provide a greater supply of Cu, our observation contradicts the conventional view on the role of UBM on prolonging EM failure. We initially ascribed it to the increased of EM-prone microstructures or weak- links at the SAC/UBM interface active in thicker UBM layers. This is considered to be due to a more even distribution of EM flux across the joint by reducing current crowding at the corners of the joint. However, switching the test configuration, reducing current crowding, yielded results that disagreed with our proposition. It is found that the impact of the current configuration, and thereby the level of current crowding, on EM resistance does not vary much with the UBM thickness. This defies initial prediction that there would be a smaller impact in samples with thicker UBMs when the current configuration is switched. These results suggest that the EM failure mechanism is affected by UBM in a more complicated manner. Considering hidden factors such as the change in thermal stress with UBM thickness that act against the growth of EM void is necessary in order to better understand the mechanism.
{"title":"Effects of UBM Thickness and Current Flow Configuration on Electromigration Failure Mechanisms in Solder Interconnects","authors":"Y. Kim, Allison T. Osmanson, H. Madanipour, C. Kim, P. Thompson, Qiao Chen","doi":"10.1109/IRPS45951.2020.9129337","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129337","url":null,"abstract":"This paper investigates the effects of the under bump metallization (UBM) on Electromigration (EM) reliability of SAC solder joints and presents evidence suggestive of hidden mechanisms controlling the EM failure. This conclusion is based on the observation that the EM resistance does not show a monotonic increase with UBM thickness, but rather decreases above a certain critical limit. Since a thicker UBM would provide a greater supply of Cu, our observation contradicts the conventional view on the role of UBM on prolonging EM failure. We initially ascribed it to the increased of EM-prone microstructures or weak- links at the SAC/UBM interface active in thicker UBM layers. This is considered to be due to a more even distribution of EM flux across the joint by reducing current crowding at the corners of the joint. However, switching the test configuration, reducing current crowding, yielded results that disagreed with our proposition. It is found that the impact of the current configuration, and thereby the level of current crowding, on EM resistance does not vary much with the UBM thickness. This defies initial prediction that there would be a smaller impact in samples with thicker UBMs when the current configuration is switched. These results suggest that the EM failure mechanism is affected by UBM in a more complicated manner. Considering hidden factors such as the change in thermal stress with UBM thickness that act against the growth of EM void is necessary in order to better understand the mechanism.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129240027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128318
Amartya Ghosh, J. Hao, M. Cook, C. Kendrick, S. Suliman, G. Hall, T. Kopley, O. Awadelkarim
Bias Temperature Instability (BTI) measurements were performed on SiC n-channel DMOSFETs. The effects of the BTI stress on the electrical characteristics of the device were studied using slow and fast measurements. The slow Measurements show that the change in threshold voltage (Vth) can be attributed to charge carrier trapping/de-trapping at border traps, while interface trapped charge density is found to be unaffected. The fast measurements, however, shows significant Vth recovery taking place in-situ during measurement. Moreover, Vth shift is observed to decrease with increasing temperature for the same stress level suggesting that Vth recovery is temperature activated.
{"title":"Studies of Bias Temperature Instabilities in 4H-SiC DMOSFETs","authors":"Amartya Ghosh, J. Hao, M. Cook, C. Kendrick, S. Suliman, G. Hall, T. Kopley, O. Awadelkarim","doi":"10.1109/IRPS45951.2020.9128318","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128318","url":null,"abstract":"Bias Temperature Instability (BTI) measurements were performed on SiC n-channel DMOSFETs. The effects of the BTI stress on the electrical characteristics of the device were studied using slow and fast measurements. The slow Measurements show that the change in threshold voltage (Vth) can be attributed to charge carrier trapping/de-trapping at border traps, while interface trapped charge density is found to be unaffected. The fast measurements, however, shows significant Vth recovery taking place in-situ during measurement. Moreover, Vth shift is observed to decrease with increasing temperature for the same stress level suggesting that Vth recovery is temperature activated.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115968602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129148
Min-su Kim, Jeehwan Song, C. Kim
A logic-compatible embedded NAND (eNAND) flash memory based synapse with 3 bit per cell weight storage and 1μA current steps was demonstrated in a standard 65nm CMOS process. The eNAND flash based neuromorphic core consists of 16stack eNAND strings. Each flash cell is composed of 3 transistors (2 PMOS and 1 NMOS) and each string is connected to the main bitline via 2 additional NMOS access transistors. In this work, we realized 3 bit weight based on 1μA current steps using the proposed back-pattern tolerant program-verify scheme. To evaluate the reliability of eNAND Flash based synapses, we measured the temperature dependence, read disturbance, and retention characteristics from a 65nm test chip with 3 bit per cell weight storage and 1μA current steps.
{"title":"Reliability Characterization of Logic-Compatible NAND Flash Memory based Synapses with 3-bit per Cell Weights and 1μA Current Steps","authors":"Min-su Kim, Jeehwan Song, C. Kim","doi":"10.1109/IRPS45951.2020.9129148","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129148","url":null,"abstract":"A logic-compatible embedded NAND (eNAND) flash memory based synapse with 3 bit per cell weight storage and 1μA current steps was demonstrated in a standard 65nm CMOS process. The eNAND flash based neuromorphic core consists of 16stack eNAND strings. Each flash cell is composed of 3 transistors (2 PMOS and 1 NMOS) and each string is connected to the main bitline via 2 additional NMOS access transistors. In this work, we realized 3 bit weight based on 1μA current steps using the proposed back-pattern tolerant program-verify scheme. To evaluate the reliability of eNAND Flash based synapses, we measured the temperature dependence, read disturbance, and retention characteristics from a 65nm test chip with 3 bit per cell weight storage and 1μA current steps.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115431576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128829
C. Dunn, John MacPeak, Sean Bo, B. Kirkpatrick, Brian Horning, T. Grider, C. O'Brien, S. Heinrich-Barna, Armando Vigil, Jon Nafziger, Lyndon Preiss, Kelly DeShields, V. Markov, JinHo Kim, N. Do, A. Kotov
In advanced embedded split-gate SuperFlash® 3rd generation technology (ESF3) the select gate is compiled with continually scaled core logic transistors. In doing so, enhanced performance and lower power are achieved. However, it was observed during ESF3 process development and integration with 1 V core logic that the program disturb performance was degraded over previous generations of this cell. Data are presented to show that the disturb phenomenon was driven by trap-assisted tunneling in the 19 Å core oxide. Corrective actions taken to eliminate this failure mechanism are discussed. Process improvement solutions were successfully applied to the smaller ESF3 technology nodes compatible with 1 V core logic and thinner gate dielectric. Pathway for continual scaling of the ESF3 cell technology in line with core transistors is presented.
{"title":"Program Disturb Mechanism in Embedded SuperFlash® Technology","authors":"C. Dunn, John MacPeak, Sean Bo, B. Kirkpatrick, Brian Horning, T. Grider, C. O'Brien, S. Heinrich-Barna, Armando Vigil, Jon Nafziger, Lyndon Preiss, Kelly DeShields, V. Markov, JinHo Kim, N. Do, A. Kotov","doi":"10.1109/IRPS45951.2020.9128829","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128829","url":null,"abstract":"In advanced embedded split-gate SuperFlash® 3rd generation technology (ESF3) the select gate is compiled with continually scaled core logic transistors. In doing so, enhanced performance and lower power are achieved. However, it was observed during ESF3 process development and integration with 1 V core logic that the program disturb performance was degraded over previous generations of this cell. Data are presented to show that the disturb phenomenon was driven by trap-assisted tunneling in the 19 Å core oxide. Corrective actions taken to eliminate this failure mechanism are discussed. Process improvement solutions were successfully applied to the smaller ESF3 technology nodes compatible with 1 V core logic and thinner gate dielectric. Pathway for continual scaling of the ESF3 cell technology in line with core transistors is presented.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115722951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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