Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563537
M. Si Moussa, C. Pavageau, D. Lederer, L. Picheta, F. Danneville, J. Russat, N. Fel, J. Raskin, D. Vanhoenacker-Janvier
Losses of microstrip line and coplanar waveguide made on HR and STD SOI wafers were analyzed with respect to temperature. MSL allows the use of STD substrate because the back ground plane shields the Si substrate. MSL can then be an interesting topology if the losses can be lowered to the same level than CPW made on HR SOI or SOS. For the CPW, the losses are of two kinds: conductor losses, due to the metal resistivity, and substrate losses, due to the coupling between the line and the substrate. These results demonstrate the feasibility and practical applicability of different passive structures in circuits design for both room and high temperature applications. Due to the rapid increase in the number of metallic interconnects, the top level metals are situated further away from the SOI substrate as the technology scales, thus reducing the substrate losses for CPW and widen the metallic strip for MSL. In a near future, 12 metal levels are available and enable using 5 times wider strips for MSL and thus reduce the losses by a factor of 3 making MSL as a very promising structure for RF design for the next technological node.
{"title":"An investigation of temperature effects on CPW and MSL on SOI substrate for RF applications","authors":"M. Si Moussa, C. Pavageau, D. Lederer, L. Picheta, F. Danneville, J. Russat, N. Fel, J. Raskin, D. Vanhoenacker-Janvier","doi":"10.1109/SOI.2005.1563537","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563537","url":null,"abstract":"Losses of microstrip line and coplanar waveguide made on HR and STD SOI wafers were analyzed with respect to temperature. MSL allows the use of STD substrate because the back ground plane shields the Si substrate. MSL can then be an interesting topology if the losses can be lowered to the same level than CPW made on HR SOI or SOS. For the CPW, the losses are of two kinds: conductor losses, due to the metal resistivity, and substrate losses, due to the coupling between the line and the substrate. These results demonstrate the feasibility and practical applicability of different passive structures in circuits design for both room and high temperature applications. Due to the rapid increase in the number of metallic interconnects, the top level metals are situated further away from the SOI substrate as the technology scales, thus reducing the substrate losses for CPW and widen the metallic strip for MSL. In a near future, 12 metal levels are available and enable using 5 times wider strips for MSL and thus reduce the losses by a factor of 3 making MSL as a very promising structure for RF design for the next technological node.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115362638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563551
T. Ohtou, K. Yokoyama, T. Nagumo, T. Hiramoto
A new bias scheme of variable-/spl gamma/ FD SOI MOSFET is proposed. Using the scheme, almost no degradation of t/sub pd/ in the active-state is achieved even in the t/sub BOX/ of a sub-10 nm while I/sub off/ is sufficiently suppressed in the standby-state. Reducing the inter-die V/sub th/ fluctuation on a wide V/sub sub/ range in the active-state is realized. This device scheme is also well applicable to 3D channel MOSFETs including a FinFET.
{"title":"V/sub th/ control of t/sub pd/-degradation-free FD SOI MOSFET with extremely thin BOX using variable body-factor scheme","authors":"T. Ohtou, K. Yokoyama, T. Nagumo, T. Hiramoto","doi":"10.1109/SOI.2005.1563551","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563551","url":null,"abstract":"A new bias scheme of variable-/spl gamma/ FD SOI MOSFET is proposed. Using the scheme, almost no degradation of t/sub pd/ in the active-state is achieved even in the t/sub BOX/ of a sub-10 nm while I/sub off/ is sufficiently suppressed in the standby-state. Reducing the inter-die V/sub th/ fluctuation on a wide V/sub sub/ range in the active-state is realized. This device scheme is also well applicable to 3D channel MOSFETs including a FinFET.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114965429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563581
M. Fujiwara, T. Morooka, N. Yasutake, K. Ohuchi, N. Aoki, H. Tanimoto, M. Kondo, K. Miyano, S. Inaba, K. Ishimaru, H. Ishiuchi
This paper presents the first demonstration of ultra-thin BOX FD SOI devices with nominal gate length of 30 nm. The characteristics of FD SOI MOSFETs are investigated in detail as T/sub BOX/ is varied from 5 nm to 145 nm. In addition, optimum design regions of T/sub BOX/ for achieving performance requirements are demonstrated.
本文首次展示了标称栅极长度为30nm的超薄BOX FD SOI器件。详细研究了T/sub BOX/在5nm ~ 145nm范围内变化时FD SOI mosfet的特性。此外，还展示了T/sub BOX/的最佳设计区域，以达到性能要求。
{"title":"Impact of BOX scaling on 30 nm gate length FD SOI MOSFET","authors":"M. Fujiwara, T. Morooka, N. Yasutake, K. Ohuchi, N. Aoki, H. Tanimoto, M. Kondo, K. Miyano, S. Inaba, K. Ishimaru, H. Ishiuchi","doi":"10.1109/SOI.2005.1563581","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563581","url":null,"abstract":"This paper presents the first demonstration of ultra-thin BOX FD SOI devices with nominal gate length of 30 nm. The characteristics of FD SOI MOSFETs are investigated in detail as T/sub BOX/ is varied from 5 nm to 145 nm. In addition, optimum design regions of T/sub BOX/ for achieving performance requirements are demonstrated.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"10 8-9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132467300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563525
J. Lolivier, X. Jehl, Q. Rafhay, T. Poiroux, M. Vinet, B. Previtali, M. Sanquer, F. Balestra, S. Deleonibus
This work deals with the electrical characterization down to 4K of fully depleted SOI MOSFET with a physical gate length down to 10nm. Temperature measurements are used to highlight source to drain tunneling: which is evidenced at room temperature for the first time. Finally resonant tunneling effect is observed.
{"title":"Experimental characterization of source-to-drain tunneling in 10nm SOI devices","authors":"J. Lolivier, X. Jehl, Q. Rafhay, T. Poiroux, M. Vinet, B. Previtali, M. Sanquer, F. Balestra, S. Deleonibus","doi":"10.1109/SOI.2005.1563525","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563525","url":null,"abstract":"This work deals with the electrical characterization down to 4K of fully depleted SOI MOSFET with a physical gate length down to 10nm. Temperature measurements are used to highlight source to drain tunneling: which is evidenced at room temperature for the first time. Finally resonant tunneling effect is observed.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133804493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563541
L. Geynet, E. de Foucauld, D. Cartalade, G. Jacquemod
The feasibility of a switched LC tank for multi-standards applications has been proved. With our balun structure, the MOSFET (and its noise) is isolated at secondary, therefore Q-factor is less decreased and flicker noise doesn't contribute to phase noise. This new structure has lower phase noise than classical bulk tank particularly when switched on. Moreover this new switched tank occupies only one inductor area (290/spl mu/m /spl times/ 190/spl mu/m).
{"title":"An integrated balun for dual-band LC tank VCO in 130nm CMOS/SOI","authors":"L. Geynet, E. de Foucauld, D. Cartalade, G. Jacquemod","doi":"10.1109/SOI.2005.1563541","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563541","url":null,"abstract":"The feasibility of a switched LC tank for multi-standards applications has been proved. With our balun structure, the MOSFET (and its noise) is isolated at secondary, therefore Q-factor is less decreased and flicker noise doesn't contribute to phase noise. This new structure has lower phase noise than classical bulk tank particularly when switched on. Moreover this new switched tank occupies only one inductor area (290/spl mu/m /spl times/ 190/spl mu/m).","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130116968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563523
J. Widiez, M. Vinet, T. Poiroux, P. Holliger, B. Previtali, P. Grosgeorges, M. Mouis, S. Deleonibus
In this paper, we report the influence of the TiN metal gate thickness on fully depleted (FD) silicon-on-insulator (SOI) MOS transistors with SiO/sub 2/ and HfO/sub 2/ gate dielectrics. The threshold voltage as well as the electrical oxide thickness (EOT), the gate leakage current and the channel mobility are impacted. Smaller the TiN layer is, better are the transistors characteristics. This is due to a lower charge effect when the TiN thickness decreases.
{"title":"TiN metal gate thickness influence on fully depleted SOI MOSFETs physical and electrical properties","authors":"J. Widiez, M. Vinet, T. Poiroux, P. Holliger, B. Previtali, P. Grosgeorges, M. Mouis, S. Deleonibus","doi":"10.1109/SOI.2005.1563523","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563523","url":null,"abstract":"In this paper, we report the influence of the TiN metal gate thickness on fully depleted (FD) silicon-on-insulator (SOI) MOS transistors with SiO/sub 2/ and HfO/sub 2/ gate dielectrics. The threshold voltage as well as the electrical oxide thickness (EOT), the gate leakage current and the channel mobility are impacted. Smaller the TiN layer is, better are the transistors characteristics. This is due to a lower charge effect when the TiN thickness decreases.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133600101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563532
F. Allibert, N. Bresson, K. Bellatreche, C. Maunand-Tussot, S. Cristoloveanu
As the MOSFETs dimensions are scaled down, following the ITRS roadmap, the need for SOI wafers with ultra-thin Si films (UTF) becomes acute. Characterization of these wafers with simple, process-independent, and fast turnaround methods is very important. In this paper, we present for the first time 3 key aspects: (i) properties of UTF down to 10 nm thickness; (ii) comparison of thinning techniques (sacrificial oxidation vs. SCI); and (iii) comparison of pseudo-MOSFET and Hg-FET methods for UTF.
{"title":"Electrical characterization of ultra-thin SOI films: comparison of the pseudo-MOSFET and Hg-FET techniques","authors":"F. Allibert, N. Bresson, K. Bellatreche, C. Maunand-Tussot, S. Cristoloveanu","doi":"10.1109/SOI.2005.1563532","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563532","url":null,"abstract":"As the MOSFETs dimensions are scaled down, following the ITRS roadmap, the need for SOI wafers with ultra-thin Si films (UTF) becomes acute. Characterization of these wafers with simple, process-independent, and fast turnaround methods is very important. In this paper, we present for the first time 3 key aspects: (i) properties of UTF down to 10 nm thickness; (ii) comparison of thinning techniques (sacrificial oxidation vs. SCI); and (iii) comparison of pseudo-MOSFET and Hg-FET methods for UTF.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129784751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563526
G. Knoblinger, F. Kuttner, A. Marshall, C. Russ, P. Haibach, P. Patruno, T. Schulz, W. Xiong, M. Gostkowski, K. Schruefer, C. Cleavelin
Multi-gate MOSFET (MuGFET) are the most promising candidates for beyond 45nm technology CMOS nodes. For future SoC solutions in these technologies the ability to realize also analog building blocks is of utmost importance. Up to now only a few publications are available concerning the perspective of FinFETs for analog applications and no reports and measurement results can be found about the realization of analog circuits with these advanced devices. In this work the design and realization of basic analog circuits (low voltage bandgap, Miller op amp and current reference) with FinFET devices were demonstrated for the first time, including measurement results.
{"title":"Design and evaluation of basic analog circuits in an emerging MuGFET technology","authors":"G. Knoblinger, F. Kuttner, A. Marshall, C. Russ, P. Haibach, P. Patruno, T. Schulz, W. Xiong, M. Gostkowski, K. Schruefer, C. Cleavelin","doi":"10.1109/SOI.2005.1563526","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563526","url":null,"abstract":"Multi-gate MOSFET (MuGFET) are the most promising candidates for beyond 45nm technology CMOS nodes. For future SoC solutions in these technologies the ability to realize also analog building blocks is of utmost importance. Up to now only a few publications are available concerning the perspective of FinFETs for analog applications and no reports and measurement results can be found about the realization of analog circuits with these advanced devices. In this work the design and realization of basic analog circuits (low voltage bandgap, Miller op amp and current reference) with FinFET devices were demonstrated for the first time, including measurement results.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130516659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563593
M. Ershov, F. Nemati, R. Gupta, V. Gopalakrishnan, R. Gooty, M. Tarabbia, K. Yang, S. Banna, D. Hayes, H. Cho, S. Robins
This paper presents various considerations for substrate doping optimization in SOI T-RAM technology. Back gate (substrate voltage) control is used in an SOI T-RAM technology for optimizing cell characteristics. However, it is reported for the first time that typical low-doped substrates used in SOI logic technologies can create unusually slow transient effects in T-RAM cell. It is also demonstrated that the optimization of substrate doping resolves this slow transient problem and improves back gate control of SOI T-RAM memory arrays.
{"title":"Optimization of substrate doping for back-gate control in SOI T-RAM memory technology","authors":"M. Ershov, F. Nemati, R. Gupta, V. Gopalakrishnan, R. Gooty, M. Tarabbia, K. Yang, S. Banna, D. Hayes, H. Cho, S. Robins","doi":"10.1109/SOI.2005.1563593","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563593","url":null,"abstract":"This paper presents various considerations for substrate doping optimization in SOI T-RAM technology. Back gate (substrate voltage) control is used in an SOI T-RAM technology for optimizing cell characteristics. However, it is reported for the first time that typical low-doped substrates used in SOI logic technologies can create unusually slow transient effects in T-RAM cell. It is also demonstrated that the optimization of substrate doping resolves this slow transient problem and improves back gate control of SOI T-RAM memory arrays.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129489542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563517
C. Mazure, I. Cayrefourcq
Strained silicon engineering has become a key innovation to enhance device on-current. It has allowed the IC industry to keep on the scaling path and assure a performance gain from one technology node to the next. Uniaxial strained silicon has already made its way into 90nm IC manufacturing. Biaxial wafer level strain may be the next step for boosting transistor performance. At the substrate level, strained silicon on insulator is a major innovation that offers higher carrier mobility, combining the advantages of SOI with those of strained silicon. This review focuses on the development of strained silicon, its impact on device properties and its scalability beyond 65nm design rules.
{"title":"Status of device mobility enhancement through strained silicon engineering","authors":"C. Mazure, I. Cayrefourcq","doi":"10.1109/SOI.2005.1563517","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563517","url":null,"abstract":"Strained silicon engineering has become a key innovation to enhance device on-current. It has allowed the IC industry to keep on the scaling path and assure a performance gain from one technology node to the next. Uniaxial strained silicon has already made its way into 90nm IC manufacturing. Biaxial wafer level strain may be the next step for boosting transistor performance. At the substrate level, strained silicon on insulator is a major innovation that offers higher carrier mobility, combining the advantages of SOI with those of strained silicon. This review focuses on the development of strained silicon, its impact on device properties and its scalability beyond 65nm design rules.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129515098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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