Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563541
L. Geynet, E. de Foucauld, D. Cartalade, G. Jacquemod
The feasibility of a switched LC tank for multi-standards applications has been proved. With our balun structure, the MOSFET (and its noise) is isolated at secondary, therefore Q-factor is less decreased and flicker noise doesn't contribute to phase noise. This new structure has lower phase noise than classical bulk tank particularly when switched on. Moreover this new switched tank occupies only one inductor area (290/spl mu/m /spl times/ 190/spl mu/m).
{"title":"An integrated balun for dual-band LC tank VCO in 130nm CMOS/SOI","authors":"L. Geynet, E. de Foucauld, D. Cartalade, G. Jacquemod","doi":"10.1109/SOI.2005.1563541","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563541","url":null,"abstract":"The feasibility of a switched LC tank for multi-standards applications has been proved. With our balun structure, the MOSFET (and its noise) is isolated at secondary, therefore Q-factor is less decreased and flicker noise doesn't contribute to phase noise. This new structure has lower phase noise than classical bulk tank particularly when switched on. Moreover this new switched tank occupies only one inductor area (290/spl mu/m /spl times/ 190/spl mu/m).","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130116968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563544
M. Chiang, Keunwoo Kim, C. Chuang, C. Tretz
We have presented a high-density DG logic circuit technique exploiting the unique V/sub T/ modulation effect through the extended gate-to-gate coupling in high-V/sub T/ symmetrical DG devices. The scheme reduces the number of stacked transistors (hence area/capacitance and standby/dynamic power), and improves performance. The performance improvement and power reduction are evaluated/validated using mixed-mode two-dimensional numerical simulations.
{"title":"High-density logic techniques with reduced-stack double-gate MOSFETs","authors":"M. Chiang, Keunwoo Kim, C. Chuang, C. Tretz","doi":"10.1109/SOI.2005.1563544","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563544","url":null,"abstract":"We have presented a high-density DG logic circuit technique exploiting the unique V/sub T/ modulation effect through the extended gate-to-gate coupling in high-V/sub T/ symmetrical DG devices. The scheme reduces the number of stacked transistors (hence area/capacitance and standby/dynamic power), and improves performance. The performance improvement and power reduction are evaluated/validated using mixed-mode two-dimensional numerical simulations.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114356509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563546
K. Yamasaki, D. Kosemura, S. Tanaka, A. Ogura, I. Ichiba, R. Shimidzu
Three different type strained-Si substrates, EPI, SGOI and SSOI, were evaluated by newly developed high-resolution UV-Raman spectroscopy. The structure relaxation occurred by RTA at 1050/spl deg/C. The Raman peak shifted toward larger wavenumber after RTA for SSOI, indicating strain relaxation. The peak shifted toward lower wavenumber in the case of EPI due to the Ge diffusion rather than strain relaxation. The SGOI showed complex characteristics of SSOI and EPI.
{"title":"Relaxation of strained-SOI substrates by RTA process","authors":"K. Yamasaki, D. Kosemura, S. Tanaka, A. Ogura, I. Ichiba, R. Shimidzu","doi":"10.1109/SOI.2005.1563546","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563546","url":null,"abstract":"Three different type strained-Si substrates, EPI, SGOI and SSOI, were evaluated by newly developed high-resolution UV-Raman spectroscopy. The structure relaxation occurred by RTA at 1050/spl deg/C. The Raman peak shifted toward larger wavenumber after RTA for SSOI, indicating strain relaxation. The peak shifted toward lower wavenumber in the case of EPI due to the Ge diffusion rather than strain relaxation. The SGOI showed complex characteristics of SSOI and EPI.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116878816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563525
J. Lolivier, X. Jehl, Q. Rafhay, T. Poiroux, M. Vinet, B. Previtali, M. Sanquer, F. Balestra, S. Deleonibus
This work deals with the electrical characterization down to 4K of fully depleted SOI MOSFET with a physical gate length down to 10nm. Temperature measurements are used to highlight source to drain tunneling: which is evidenced at room temperature for the first time. Finally resonant tunneling effect is observed.
{"title":"Experimental characterization of source-to-drain tunneling in 10nm SOI devices","authors":"J. Lolivier, X. Jehl, Q. Rafhay, T. Poiroux, M. Vinet, B. Previtali, M. Sanquer, F. Balestra, S. Deleonibus","doi":"10.1109/SOI.2005.1563525","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563525","url":null,"abstract":"This work deals with the electrical characterization down to 4K of fully depleted SOI MOSFET with a physical gate length down to 10nm. Temperature measurements are used to highlight source to drain tunneling: which is evidenced at room temperature for the first time. Finally resonant tunneling effect is observed.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133804493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563581
M. Fujiwara, T. Morooka, N. Yasutake, K. Ohuchi, N. Aoki, H. Tanimoto, M. Kondo, K. Miyano, S. Inaba, K. Ishimaru, H. Ishiuchi
This paper presents the first demonstration of ultra-thin BOX FD SOI devices with nominal gate length of 30 nm. The characteristics of FD SOI MOSFETs are investigated in detail as T/sub BOX/ is varied from 5 nm to 145 nm. In addition, optimum design regions of T/sub BOX/ for achieving performance requirements are demonstrated.
本文首次展示了标称栅极长度为30nm的超薄BOX FD SOI器件。详细研究了T/sub BOX/在5nm ~ 145nm范围内变化时FD SOI mosfet的特性。此外，还展示了T/sub BOX/的最佳设计区域，以达到性能要求。
{"title":"Impact of BOX scaling on 30 nm gate length FD SOI MOSFET","authors":"M. Fujiwara, T. Morooka, N. Yasutake, K. Ohuchi, N. Aoki, H. Tanimoto, M. Kondo, K. Miyano, S. Inaba, K. Ishimaru, H. Ishiuchi","doi":"10.1109/SOI.2005.1563581","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563581","url":null,"abstract":"This paper presents the first demonstration of ultra-thin BOX FD SOI devices with nominal gate length of 30 nm. The characteristics of FD SOI MOSFETs are investigated in detail as T/sub BOX/ is varied from 5 nm to 145 nm. In addition, optimum design regions of T/sub BOX/ for achieving performance requirements are demonstrated.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"10 8-9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132467300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563523
J. Widiez, M. Vinet, T. Poiroux, P. Holliger, B. Previtali, P. Grosgeorges, M. Mouis, S. Deleonibus
In this paper, we report the influence of the TiN metal gate thickness on fully depleted (FD) silicon-on-insulator (SOI) MOS transistors with SiO/sub 2/ and HfO/sub 2/ gate dielectrics. The threshold voltage as well as the electrical oxide thickness (EOT), the gate leakage current and the channel mobility are impacted. Smaller the TiN layer is, better are the transistors characteristics. This is due to a lower charge effect when the TiN thickness decreases.
{"title":"TiN metal gate thickness influence on fully depleted SOI MOSFETs physical and electrical properties","authors":"J. Widiez, M. Vinet, T. Poiroux, P. Holliger, B. Previtali, P. Grosgeorges, M. Mouis, S. Deleonibus","doi":"10.1109/SOI.2005.1563523","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563523","url":null,"abstract":"In this paper, we report the influence of the TiN metal gate thickness on fully depleted (FD) silicon-on-insulator (SOI) MOS transistors with SiO/sub 2/ and HfO/sub 2/ gate dielectrics. The threshold voltage as well as the electrical oxide thickness (EOT), the gate leakage current and the channel mobility are impacted. Smaller the TiN layer is, better are the transistors characteristics. This is due to a lower charge effect when the TiN thickness decreases.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133600101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563566
L. Widodo, D. Pham, B. Sassman, L. Larson
Thermal agglomeration of ultra-thin SOI (<20nm) is an undesirable issue for device fabrication. In this article for the first time, a methodology to calculate the critical temperature and agglomeration rate on patterned SOI wafers with different thicknesses, ranging from 5.9nm to 12.1nm has been established. This study also presents the agglomeration effect on patterned SOI wafers for silicon structure shape, undoped, n-type doped, and p-type doped. The developed method has been tested and compared in context of previous papers published on non-patterned films presented in Y. Ishikawa et al. (2002). In addition, detailed analysis on various surface morphologies at different temperatures has been included.
{"title":"A novel technique to calculate the critical temperature of thermal agglomerations on patterned SOI wafers","authors":"L. Widodo, D. Pham, B. Sassman, L. Larson","doi":"10.1109/SOI.2005.1563566","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563566","url":null,"abstract":"Thermal agglomeration of ultra-thin SOI (<20nm) is an undesirable issue for device fabrication. In this article for the first time, a methodology to calculate the critical temperature and agglomeration rate on patterned SOI wafers with different thicknesses, ranging from 5.9nm to 12.1nm has been established. This study also presents the agglomeration effect on patterned SOI wafers for silicon structure shape, undoped, n-type doped, and p-type doped. The developed method has been tested and compared in context of previous papers published on non-patterned films presented in Y. Ishikawa et al. (2002). In addition, detailed analysis on various surface morphologies at different temperatures has been included.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115661952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563517
C. Mazure, I. Cayrefourcq
Strained silicon engineering has become a key innovation to enhance device on-current. It has allowed the IC industry to keep on the scaling path and assure a performance gain from one technology node to the next. Uniaxial strained silicon has already made its way into 90nm IC manufacturing. Biaxial wafer level strain may be the next step for boosting transistor performance. At the substrate level, strained silicon on insulator is a major innovation that offers higher carrier mobility, combining the advantages of SOI with those of strained silicon. This review focuses on the development of strained silicon, its impact on device properties and its scalability beyond 65nm design rules.
{"title":"Status of device mobility enhancement through strained silicon engineering","authors":"C. Mazure, I. Cayrefourcq","doi":"10.1109/SOI.2005.1563517","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563517","url":null,"abstract":"Strained silicon engineering has become a key innovation to enhance device on-current. It has allowed the IC industry to keep on the scaling path and assure a performance gain from one technology node to the next. Uniaxial strained silicon has already made its way into 90nm IC manufacturing. Biaxial wafer level strain may be the next step for boosting transistor performance. At the substrate level, strained silicon on insulator is a major innovation that offers higher carrier mobility, combining the advantages of SOI with those of strained silicon. This review focuses on the development of strained silicon, its impact on device properties and its scalability beyond 65nm design rules.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129515098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563593
M. Ershov, F. Nemati, R. Gupta, V. Gopalakrishnan, R. Gooty, M. Tarabbia, K. Yang, S. Banna, D. Hayes, H. Cho, S. Robins
This paper presents various considerations for substrate doping optimization in SOI T-RAM technology. Back gate (substrate voltage) control is used in an SOI T-RAM technology for optimizing cell characteristics. However, it is reported for the first time that typical low-doped substrates used in SOI logic technologies can create unusually slow transient effects in T-RAM cell. It is also demonstrated that the optimization of substrate doping resolves this slow transient problem and improves back gate control of SOI T-RAM memory arrays.
{"title":"Optimization of substrate doping for back-gate control in SOI T-RAM memory technology","authors":"M. Ershov, F. Nemati, R. Gupta, V. Gopalakrishnan, R. Gooty, M. Tarabbia, K. Yang, S. Banna, D. Hayes, H. Cho, S. Robins","doi":"10.1109/SOI.2005.1563593","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563593","url":null,"abstract":"This paper presents various considerations for substrate doping optimization in SOI T-RAM technology. Back gate (substrate voltage) control is used in an SOI T-RAM technology for optimizing cell characteristics. However, it is reported for the first time that typical low-doped substrates used in SOI logic technologies can create unusually slow transient effects in T-RAM cell. It is also demonstrated that the optimization of substrate doping resolves this slow transient problem and improves back gate control of SOI T-RAM memory arrays.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129489542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563554
S. Barraud, L. Clavelier
Electrical properties in germanium and performances of GeOI devices have been studied using MC simulations. We have shown an ion improvement increasing when the channel length is shrinked that is not the case in strained-Si based NFET. The results clearly demonstrate that the germanium may be a promising material for the future CMOS technology.
{"title":"Scaling of GeOI NFET in sub-50nm regime using a Monte-Carlo method","authors":"S. Barraud, L. Clavelier","doi":"10.1109/SOI.2005.1563554","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563554","url":null,"abstract":"Electrical properties in germanium and performances of GeOI devices have been studied using MC simulations. We have shown an ion improvement increasing when the channel length is shrinked that is not the case in strained-Si based NFET. The results clearly demonstrate that the germanium may be a promising material for the future CMOS technology.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126347752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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