Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563584
M. Alles, D. Ball, L. Massengill, peixiong zhao, K. Warren, R. Weller
Reductions in supply voltage and device dimensions, and increased transistor circuits in advanced circuits, make single event effects increasingly relevant. Non-planar multiple-gate FETs (MugFETs) are under consideration for /spl les/ 45 nm technology generations. In this work, we examine issues for SEE in advanced MugFETs using energy deposition and device simulations.
{"title":"Considerations for single event effects in non-planar multi-gate SOI FETs","authors":"M. Alles, D. Ball, L. Massengill, peixiong zhao, K. Warren, R. Weller","doi":"10.1109/SOI.2005.1563584","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563584","url":null,"abstract":"Reductions in supply voltage and device dimensions, and increased transistor circuits in advanced circuits, make single event effects increasingly relevant. Non-planar multiple-gate FETs (MugFETs) are under consideration for /spl les/ 45 nm technology generations. In this work, we examine issues for SEE in advanced MugFETs using energy deposition and device simulations.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122076782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563555
V. Kilchytska, D. Lederer, P. Simon, N. Collaert, J. Raskin, D. Flandre
In this paper we revise the split C-V technique widely used for mobility extraction. To extend its applicability we propose to use an integral of transconductance measured at high frequencies (HF) instead of the DC drain current. For the first time it is shown that such procedure allows not only to suppress parasitic gate-induced floating body effect (GIFBE), but also to improve the accuracy of mobility extraction in weak inversion (WI) regime. In this paper we apply our technique to partially-depleted (PD) SOI MOSFETs from a FinFET process and demonstrate its advantages in comparison to the standard method.
本文对目前广泛应用于流动性提取的分裂C-V技术进行了改进。为了扩大其适用性，我们建议使用高频(HF)测量的跨导积分来代替直流漏极电流。首次证明了这种方法不仅可以抑制寄生门诱导的浮体效应(GIFBE)，而且可以提高弱反转(WI)状态下迁移率提取的准确性。在本文中，我们将我们的技术应用于FinFET过程中的部分耗尽(PD) SOI mosfet，并展示了与标准方法相比的优势。
{"title":"Revised split C-V technique for mobility investigation in advanced devices","authors":"V. Kilchytska, D. Lederer, P. Simon, N. Collaert, J. Raskin, D. Flandre","doi":"10.1109/SOI.2005.1563555","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563555","url":null,"abstract":"In this paper we revise the split C-V technique widely used for mobility extraction. To extend its applicability we propose to use an integral of transconductance measured at high frequencies (HF) instead of the DC drain current. For the first time it is shown that such procedure allows not only to suppress parasitic gate-induced floating body effect (GIFBE), but also to improve the accuracy of mobility extraction in weak inversion (WI) regime. In this paper we apply our technique to partially-depleted (PD) SOI MOSFETs from a FinFET process and demonstrate its advantages in comparison to the standard method.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124200280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563583
D. Nelson, H. Liu, K. Golke, A. Kohli
A split word line design technique that improves the soft error rate (SER) of high performance 150nm SOI embedded SRAMs is presented along with SER results.
提出了一种可提高高性能150nm SOI嵌入式sram软错误率(SER)的分字线设计技术。
{"title":"150nm SOI embedded SRAMs with very low SER","authors":"D. Nelson, H. Liu, K. Golke, A. Kohli","doi":"10.1109/SOI.2005.1563583","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563583","url":null,"abstract":"A split word line design technique that improves the soft error rate (SER) of high performance 150nm SOI embedded SRAMs is presented along with SER results.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129632675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563561
I.-S.M. Sun, W. Ng, H. Mochizuki, K. Kanekiyo, T. Kobayashi, M. Toita, H. Imai, A. Ishikawa, S. Tamura, K. Takasuka
This work presents an ultra-low power RF LBJT on SOI. The Johnson's product (f/sub /spl tau// /spl times/BV/sub CEO/) of the fabricated LBJTs ranges between 190-300 GHz-V. The f/sub max/ of the optimal device reaches 46 GHz at collector current density of only 0.15mA//spl mu/m/sup 2/. This LBJT is compatible with SOI-CMOS for SOI-BiCMOS integration, an ideal technology for RF and mixed-signal SoC.
{"title":"Novel ultra-low power RF lateral BJT on SOI-CMOS compatible substrate for SoC applications","authors":"I.-S.M. Sun, W. Ng, H. Mochizuki, K. Kanekiyo, T. Kobayashi, M. Toita, H. Imai, A. Ishikawa, S. Tamura, K. Takasuka","doi":"10.1109/SOI.2005.1563561","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563561","url":null,"abstract":"This work presents an ultra-low power RF LBJT on SOI. The Johnson's product (f/sub /spl tau// /spl times/BV/sub CEO/) of the fabricated LBJTs ranges between 190-300 GHz-V. The f/sub max/ of the optimal device reaches 46 GHz at collector current density of only 0.15mA//spl mu/m/sup 2/. This LBJT is compatible with SOI-CMOS for SOI-BiCMOS integration, an ideal technology for RF and mixed-signal SoC.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131574077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563542
D. Hackler, D. DeGregorio, S. Parke
This paper demonstrates IDG FlexFET CMOS in static CMOS ring oscillators, while the advantages of applying IDG-CMOS to dynamic domino CMOS logic circuits have recently been shown as well (H. Mahmoodi, 2004). IDG-CMOS has also recently been applied to several exciting new analog/MS/RF circuit applications, such as a single transistor mixer (L. Mathew, 2004).
{"title":"Ultra-low-power, high-performance, dynamic-threshold digital circuits in the FlexFET independently-double-gated SOI CMOS technology","authors":"D. Hackler, D. DeGregorio, S. Parke","doi":"10.1109/SOI.2005.1563542","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563542","url":null,"abstract":"This paper demonstrates IDG FlexFET CMOS in static CMOS ring oscillators, while the advantages of applying IDG-CMOS to dynamic domino CMOS logic circuits have recently been shown as well (H. Mahmoodi, 2004). IDG-CMOS has also recently been applied to several exciting new analog/MS/RF circuit applications, such as a single transistor mixer (L. Mathew, 2004).","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128380671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563596
F. Andrieu, T. Ernst, O. Faynot, Y. Bogumilowicz, J. Hartmann, J. Eymery, D. Lafond, Y. Levaillant, C. Dupré, R. Powers, F. Fournel, C. Fenouillet-Béranger, A. Vandooren, B. Ghyselen, C. Mazure, N. Kernevez, G. Ghibaudo, S. Deleonibus
We report an original dual channel fully depleted CMOSFET architecture on insulator (DCOI) co-integrating strained-Si (nMOS) and strained-Si/sub 0.6/Ge/sub 0.4/ (pMOS) with HfO/sub 2//TiN gate stacks down to 15nm gate length. We demonstrate for the first time an I/sub ON/ improvement for short channel SOI of 10% at 35nm gate length (25% at 75nm, 100% on long channels) for both n- and p-MOSFETs and a more than 3 decades gate leakage reduction compared to a SiO/sub 2/ dielectric. Meanwhile, thanks to the dual channel engineering, a threshold voltage adjustment is performed with a mid gap single metal gate suitable for high performance (HP) CMOS.
{"title":"Co-integrated dual strained channels on fully depleted sSDOI CMOSFETs with HfO/sub 2//TiN gate stack down to 15nm gate length","authors":"F. Andrieu, T. Ernst, O. Faynot, Y. Bogumilowicz, J. Hartmann, J. Eymery, D. Lafond, Y. Levaillant, C. Dupré, R. Powers, F. Fournel, C. Fenouillet-Béranger, A. Vandooren, B. Ghyselen, C. Mazure, N. Kernevez, G. Ghibaudo, S. Deleonibus","doi":"10.1109/SOI.2005.1563596","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563596","url":null,"abstract":"We report an original dual channel fully depleted CMOSFET architecture on insulator (DCOI) co-integrating strained-Si (nMOS) and strained-Si/sub 0.6/Ge/sub 0.4/ (pMOS) with HfO/sub 2//TiN gate stacks down to 15nm gate length. We demonstrate for the first time an I/sub ON/ improvement for short channel SOI of 10% at 35nm gate length (25% at 75nm, 100% on long channels) for both n- and p-MOSFETs and a more than 3 decades gate leakage reduction compared to a SiO/sub 2/ dielectric. Meanwhile, thanks to the dual channel engineering, a threshold voltage adjustment is performed with a mid gap single metal gate suitable for high performance (HP) CMOS.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134357540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563575
P.S. Fechnerand, E. Vogt
Additional process complexity required for multiple gate oxide thicknesses has been demonstrated to cause significant impact on p-channel mobility through oxidation induced stress effects. This can occur even after the STI oxide planarization step. Therefore, process flow options to minimize all oxidations after island definition should be considered. The data presented here also underscores the need to understand and model the oxidation induced stress associated with the specific device of interest. Since these stresses have a major impact on device mobility and current drive, care must be taken to make sure variation in layout options such as stacking transistors in a single device island rather than individual islands do not lead to circuit design modeling errors sufficient to compromise circuit performance margins. SUPREM4 appears to be able to model this behavior but most circuit level transistor models are not capable of handling this level of detail or complexity.
{"title":"Oxidation induced stress effects on hole mobility as a function of transistor geometry in a 0.15 /spl mu/m dual gate oxide CMOS SOI process","authors":"P.S. Fechnerand, E. Vogt","doi":"10.1109/SOI.2005.1563575","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563575","url":null,"abstract":"Additional process complexity required for multiple gate oxide thicknesses has been demonstrated to cause significant impact on p-channel mobility through oxidation induced stress effects. This can occur even after the STI oxide planarization step. Therefore, process flow options to minimize all oxidations after island definition should be considered. The data presented here also underscores the need to understand and model the oxidation induced stress associated with the specific device of interest. Since these stresses have a major impact on device mobility and current drive, care must be taken to make sure variation in layout options such as stacking transistors in a single device island rather than individual islands do not lead to circuit design modeling errors sufficient to compromise circuit performance margins. SUPREM4 appears to be able to model this behavior but most circuit level transistor models are not capable of handling this level of detail or complexity.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123770513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563569
C. Moulin, D. Delprat, C. Maleville, W. Mcmillan, J. Payne, K. Bird well, R. Brun, R. Moirin
This paper shows how a new generation of inspection system enables us to monitor SOI as requested in the ITRS roadmaps; it shows also the large amount of key information we can collect, giving us important feedback on the SOI process.
{"title":"UV scanning for SOI defectivity monitoring","authors":"C. Moulin, D. Delprat, C. Maleville, W. Mcmillan, J. Payne, K. Bird well, R. Brun, R. Moirin","doi":"10.1109/SOI.2005.1563569","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563569","url":null,"abstract":"This paper shows how a new generation of inspection system enables us to monitor SOI as requested in the ITRS roadmaps; it shows also the large amount of key information we can collect, giving us important feedback on the SOI process.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116542029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563540
M. Ketchen, M. Bhushan, K. Jenkins
We have implemented a new approach for measuring the pulse I-V characteristics of a set of nominally identical MOSFETs. In this scheme, all high speed signals are contained entirely inside the test structure itself. Only DC inputs and outputs are required for direct measurement of both DC and AC I-V characteristics at frequencies up to the GHz range.
{"title":"Circuit to measure high speed pulse I-V characteristics with only DC I/O's","authors":"M. Ketchen, M. Bhushan, K. Jenkins","doi":"10.1109/SOI.2005.1563540","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563540","url":null,"abstract":"We have implemented a new approach for measuring the pulse I-V characteristics of a set of nominally identical MOSFETs. In this scheme, all high speed signals are contained entirely inside the test structure itself. Only DC inputs and outputs are required for direct measurement of both DC and AC I-V characteristics at frequencies up to the GHz range.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129959485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563556
H. Liu, K. Golke, S.T. Liu
A new SPICE based dose rate model is proposed for SOI MOSFETs, which accounts for collections of excess carriers by both source/body and drain/body junctions. It is also identified that the parasitic bipolar transistor does not play a significant role within the range of dose rate of interest. An implementation method for circuit level simulation is described. The validity of this model has been verified by test results.
{"title":"A new dose rate model for SOI MOSFETs and its implementation in SPICE","authors":"H. Liu, K. Golke, S.T. Liu","doi":"10.1109/SOI.2005.1563556","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563556","url":null,"abstract":"A new SPICE based dose rate model is proposed for SOI MOSFETs, which accounts for collections of excess carriers by both source/body and drain/body junctions. It is also identified that the parasitic bipolar transistor does not play a significant role within the range of dose rate of interest. An implementation method for circuit level simulation is described. The validity of this model has been verified by test results.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134237199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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