Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563576
M. Pelella, G. Burbach, A. Salman, A. Beebe, D. Chan, J. Buller
In this work, we describe novel self-aligned diode and resistor structures and their process integration into an advanced 90nm SOI technology. Their superior device characteristics over conventional device structures built within the SOI film is described.
{"title":"A novel self-aligned substrate-diode structure for SOI technologies","authors":"M. Pelella, G. Burbach, A. Salman, A. Beebe, D. Chan, J. Buller","doi":"10.1109/SOI.2005.1563576","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563576","url":null,"abstract":"In this work, we describe novel self-aligned diode and resistor structures and their process integration into an advanced 90nm SOI technology. Their superior device characteristics over conventional device structures built within the SOI film is described.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"14 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113974525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563591
Jae-Joon Kim, Keunwoo Kim, C. Chuang
We have presented a novel back-gate controlled UTSOI SRAM cell structure and associated design considerations. The proposed scheme offers improved stability compared with conventional 6T cell, and has less number of transistors than the conventional 10T cell. Due to over 3/spl times/ improvement in SNM even at low VDD and reduced area penalty compared with 10T cell, the proposed 8T cell could be aggressively scaled down. This scheme can also be applied to SRAM cells with asymmetrical DG devices.
{"title":"Back-gate controlled READ SRAM with improved stability","authors":"Jae-Joon Kim, Keunwoo Kim, C. Chuang","doi":"10.1109/SOI.2005.1563591","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563591","url":null,"abstract":"We have presented a novel back-gate controlled UTSOI SRAM cell structure and associated design considerations. The proposed scheme offers improved stability compared with conventional 6T cell, and has less number of transistors than the conventional 10T cell. Due to over 3/spl times/ improvement in SNM even at low VDD and reduced area penalty compared with 10T cell, the proposed 8T cell could be aggressively scaled down. This scheme can also be applied to SRAM cells with asymmetrical DG devices.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126357968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563564
A. Wittkower
This paper describes two different aspects of endeavor in the supply chain of the semiconductor industry. Semiconductor equipment manufacturers have great problems dealing with the cyclical nature of the business as periods of overactive sales activity are followed by substantial periods of inactivity. Some management solutions are suggested. By comparison, sales of advanced materials tend to follow more smoothly the ups and downs of the market. However, the never-ending quest for higher quality material, defined by tighter specifications, generates its own challenges including improved capabilities for next generation characterization equipment. An example is given.
{"title":"The joys of equipment manufacturing and the agony of making materials","authors":"A. Wittkower","doi":"10.1109/SOI.2005.1563564","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563564","url":null,"abstract":"This paper describes two different aspects of endeavor in the supply chain of the semiconductor industry. Semiconductor equipment manufacturers have great problems dealing with the cyclical nature of the business as periods of overactive sales activity are followed by substantial periods of inactivity. Some management solutions are suggested. By comparison, sales of advanced materials tend to follow more smoothly the ups and downs of the market. However, the never-ending quest for higher quality material, defined by tighter specifications, generates its own challenges including improved capabilities for next generation characterization equipment. An example is given.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126497251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563534
A. Ohata, S. Cristoioveanu, M. Cassé, A. Vandoorcn, F. Daugé
By investigating the coupling effect between the front and back channels of ultra-thin SOI-MOSFETs, the mobility enhancement by volume inversion, the channel separation between the front and back channels, and the impact of the SOI thickness are discussed. As a result, it is shown that a careful check is necessary for confirming which channel (front or back) is inverted in a short device because the channel separation is difficult in transconductance curves. Furthermore, it is shown that the SOI thickness depends on the device size and location, leading to a complex behavior.
{"title":"Characterization of ultra-thin SOI MOSFETs by coupling effect between front and back interfaces","authors":"A. Ohata, S. Cristoioveanu, M. Cassé, A. Vandoorcn, F. Daugé","doi":"10.1109/SOI.2005.1563534","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563534","url":null,"abstract":"By investigating the coupling effect between the front and back channels of ultra-thin SOI-MOSFETs, the mobility enhancement by volume inversion, the channel separation between the front and back channels, and the impact of the SOI thickness are discussed. As a result, it is shown that a careful check is necessary for confirming which channel (front or back) is inverted in a short device because the channel separation is difficult in transconductance curves. Furthermore, it is shown that the SOI thickness depends on the device size and location, leading to a complex behavior.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131378315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563550
Zhichao Lv, Hao Zhang, Jian Wang, L. Tian, Zhijian Li, Jiayin Sun, Jing Chen, Xi Wang
In this work, a method to fabricate SA-DSOI MOSFET with dielectric pocket has been presented. Dielectric pocket and BOX are realized by local SIMOX technology. This novel structure results in good SCE and SHE suppression and higher speed performance, which is very important in nanoscale device design. With this novel self-aligned process, DSOI MOSFET can be scaled down to nano-scale and becomes a promising device.
{"title":"Fabrication of self-aligned drain and source on insulator MOSFET with dielectric pocket by local SIMOX technology","authors":"Zhichao Lv, Hao Zhang, Jian Wang, L. Tian, Zhijian Li, Jiayin Sun, Jing Chen, Xi Wang","doi":"10.1109/SOI.2005.1563550","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563550","url":null,"abstract":"In this work, a method to fabricate SA-DSOI MOSFET with dielectric pocket has been presented. Dielectric pocket and BOX are realized by local SIMOX technology. This novel structure results in good SCE and SHE suppression and higher speed performance, which is very important in nanoscale device design. With this novel self-aligned process, DSOI MOSFET can be scaled down to nano-scale and becomes a promising device.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129835128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563531
F. Gianesello, D. Gloria, C. Raynaud, S. Montusclat, S. Boret, C. Clement, C. Tinella, P. Benech, J. Fournier, G. Dambrine
In this paper, a comparison between transmission line (TL) integrated in high resistivity (HR) silicon on insulator technology (SOI), standard CMOS and InP technologies is made. State of the art performances are reported on HR SOI with loss propagation of about 0.4 dB/mm@40 GHz and < 1 dB/mm@100 GHz. These results demonstrate that using HR SOI wafer suppressed substrate losses (like for III-V technology). In addition, model has been developed for the described TL. To illustrate these results two microwave passive circuits, a 80 GHz coupler and a 80-100 GHz band-pass filter with both 2.5dB insertion losses (for the HR SOI version) have been realized in standard bulk CMOS and HR SOI technologies for comparison and modelization purpose.
{"title":"State of the art integrated millimeter wave passive components and circuits in advanced thin SOI CMOS technology on high resistivity substrate","authors":"F. Gianesello, D. Gloria, C. Raynaud, S. Montusclat, S. Boret, C. Clement, C. Tinella, P. Benech, J. Fournier, G. Dambrine","doi":"10.1109/SOI.2005.1563531","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563531","url":null,"abstract":"In this paper, a comparison between transmission line (TL) integrated in high resistivity (HR) silicon on insulator technology (SOI), standard CMOS and InP technologies is made. State of the art performances are reported on HR SOI with loss propagation of about 0.4 dB/mm@40 GHz and < 1 dB/mm@100 GHz. These results demonstrate that using HR SOI wafer suppressed substrate losses (like for III-V technology). In addition, model has been developed for the described TL. To illustrate these results two microwave passive circuits, a 80 GHz coupler and a 80-100 GHz band-pass filter with both 2.5dB insertion losses (for the HR SOI version) have been realized in standard bulk CMOS and HR SOI technologies for comparison and modelization purpose.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123842751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563568
S. Bedell, A. Reznicek, B. Yang, H. Hovel, J. Ott, K. Fogel, A. Domenicucci, D. Sadana
Stacking fault (SF) defects have been shown to form in Si layers under tensile strain based in P. M. J. Maree et al. (1987) and S. W. Bedell et al. (2004). In this work, we investigate the development of SF defects in strained silicon layers grown on low-defect SiGe graded buffer layers. Si layers were grown to various thicknesses at different temperatures and the resulting SF densities are measured using a specialized etching technique as presented in S. W. Bedell et al. (2004).
P. M. J. Maree等人(1987)和S. W. Bedell等人(2004)的研究表明，在拉伸应变下，硅层中会形成层错(SF)缺陷。在这项工作中，我们研究了在低缺陷SiGe梯度缓冲层上生长的应变硅层中SF缺陷的发展。硅层在不同的温度下生长到不同的厚度，并使用S. W. Bedell等人(2004)提出的专门蚀刻技术测量所得的SF密度。
{"title":"Development of stacking faults in strained silicon layers","authors":"S. Bedell, A. Reznicek, B. Yang, H. Hovel, J. Ott, K. Fogel, A. Domenicucci, D. Sadana","doi":"10.1109/SOI.2005.1563568","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563568","url":null,"abstract":"Stacking fault (SF) defects have been shown to form in Si layers under tensile strain based in P. M. J. Maree et al. (1987) and S. W. Bedell et al. (2004). In this work, we investigate the development of SF defects in strained silicon layers grown on low-defect SiGe graded buffer layers. Si layers were grown to various thicknesses at different temperatures and the resulting SF densities are measured using a specialized etching technique as presented in S. W. Bedell et al. (2004).","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"2 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113976919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563559
M. Golden, J. Tran, B. McGee, B. Kuo
Microprocessors require cutting edge technology to deliver competitive performance. AMD manufactures microprocessors in a 90nm, triple-Vt, SOI process. In this process, static transistor mismatch, caused by process variation, and dynamic transistor mismatch, caused by SOI effects, combine to increase the input referred offset of sense amplifier circuits used in SRAMs. A silicon experiment comparing different sense amp topologies reveals that body-tied transistors provide significant improvement in input referred offset without performance degradation.
{"title":"Sense amp design in SOI","authors":"M. Golden, J. Tran, B. McGee, B. Kuo","doi":"10.1109/SOI.2005.1563559","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563559","url":null,"abstract":"Microprocessors require cutting edge technology to deliver competitive performance. AMD manufactures microprocessors in a 90nm, triple-Vt, SOI process. In this process, static transistor mismatch, caused by process variation, and dynamic transistor mismatch, caused by SOI effects, combine to increase the input referred offset of sense amplifier circuits used in SRAMs. A silicon experiment comparing different sense amp topologies reveals that body-tied transistors provide significant improvement in input referred offset without performance degradation.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122814378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563565
T. Akatsu, C. Deguet, L. Sanchez, C. Richtarch, F. Allibert, F. Letertre, C. Mazure, N. Kernevez, L. Clavelier, C. Le Royer, J. Hartmann, V. Loup, M. Meuris, B. de Jaeger, G. Raskin
We present our recent achievements on 200mm GeOI formation from bulk Ge wafers and the resulting device characteristics. Pseudo-MOS measurements were done at Soitec, and Ge MOSFET fabrication was done at LETI and IMEC from epitaxial and bulk Ge starting materials, respectively.
{"title":"200mm germanium-on-insulator (GeOI) by Smart Cut/spl trade/ technology and recent GeOI pMOSFETs achievements","authors":"T. Akatsu, C. Deguet, L. Sanchez, C. Richtarch, F. Allibert, F. Letertre, C. Mazure, N. Kernevez, L. Clavelier, C. Le Royer, J. Hartmann, V. Loup, M. Meuris, B. de Jaeger, G. Raskin","doi":"10.1109/SOI.2005.1563565","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563565","url":null,"abstract":"We present our recent achievements on 200mm GeOI formation from bulk Ge wafers and the resulting device characteristics. Pseudo-MOS measurements were done at Soitec, and Ge MOSFET fabrication was done at LETI and IMEC from epitaxial and bulk Ge starting materials, respectively.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133678199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563574
K. Akarvardar, B. Dufrene, S. Cristoloveanu, J. Chroboczek, P. Gentil, B. Blalock, M. Mojarradi
Low-frequency noise characteristics of four-gate transistors (G/sup 4/-FETs) are presented distinguishing the surface conduction (MOSFET mode) and volume conduction (JFET mode). As the conducting channel moves from the surface to the bulk we observe that: (i) the noise level dramatically decreases; and (ii) the nature of the noise changes. The validity of the existing noise models for different conduction modes is discussed.
{"title":"Surface vs. bulk noise in SOI four-gate transistors","authors":"K. Akarvardar, B. Dufrene, S. Cristoloveanu, J. Chroboczek, P. Gentil, B. Blalock, M. Mojarradi","doi":"10.1109/SOI.2005.1563574","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563574","url":null,"abstract":"Low-frequency noise characteristics of four-gate transistors (G/sup 4/-FETs) are presented distinguishing the surface conduction (MOSFET mode) and volume conduction (JFET mode). As the conducting channel moves from the surface to the bulk we observe that: (i) the noise level dramatically decreases; and (ii) the nature of the noise changes. The validity of the existing noise models for different conduction modes is discussed.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114462812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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