Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563538
M. Pavanello, J. Martino, E. Simoen, C. Claeys
This work demonstrated that the saturation threshold voltage of short-channel SOI nMOSFETs degrades as the temperature is reduced. The V/sub T/ degradation at low temperatures is caused by a combination between the floating-body and impact ionization effects, increasing the gain of the parasitic bipolar structure. The halo or pocket implantation contributes for the enhanced V/sub T/ degradation at lower temperatures. The absence of halo efficiently reduces both the V/sub T/ variation and the V/sub T/ degradation in cryogenic operation. A negative biasing of the back gate tends to enhance the V/sub T/ degradation with temperature.
{"title":"Saturation threshold voltage degradation in deep-submicrometer fully depleted SOI nMOSFETs operating in cryogenic environments","authors":"M. Pavanello, J. Martino, E. Simoen, C. Claeys","doi":"10.1109/SOI.2005.1563538","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563538","url":null,"abstract":"This work demonstrated that the saturation threshold voltage of short-channel SOI nMOSFETs degrades as the temperature is reduced. The V/sub T/ degradation at low temperatures is caused by a combination between the floating-body and impact ionization effects, increasing the gain of the parasitic bipolar structure. The halo or pocket implantation contributes for the enhanced V/sub T/ degradation at lower temperatures. The absence of halo efficiently reduces both the V/sub T/ variation and the V/sub T/ degradation in cryogenic operation. A negative biasing of the back gate tends to enhance the V/sub T/ degradation with temperature.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116092617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563533
K. Samsudin, B. Cheng, A. R. Brown, S. Roy, A. Asenov
The CMOS scaling increases the impact of intrinsic parameter fluctuation on the yield and functionality of SRAM. A statistical circuit simulation framework which can fully capture intrinsic parameter fluctuation information into the compact model has been developed. The impact of discrete random dopants in the source and drain regions on 6T SRAM cells has been investigated for well scaled ultra thin body (UTB) SOI MOSFETs with physical channel length in the range of 10nm to 5nm.
CMOS的缩放增加了内在参数波动对SRAM成品率和功能的影响。提出了一种统计电路仿真框架，该框架能将固有参数波动信息充分捕捉到紧凑模型中。在物理通道长度为10nm ~ 5nm的超薄体(UTB) SOI mosfet中，研究了源极区和漏极区离散随机掺杂剂对6T SRAM电池的影响。
{"title":"Impact of random dopant induced fluctuations on sub-15nm UTB SOI 6T SRAM cells","authors":"K. Samsudin, B. Cheng, A. R. Brown, S. Roy, A. Asenov","doi":"10.1109/SOI.2005.1563533","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563533","url":null,"abstract":"The CMOS scaling increases the impact of intrinsic parameter fluctuation on the yield and functionality of SRAM. A statistical circuit simulation framework which can fully capture intrinsic parameter fluctuation information into the compact model has been developed. The impact of discrete random dopants in the source and drain regions on 6T SRAM cells has been investigated for well scaled ultra thin body (UTB) SOI MOSFETs with physical channel length in the range of 10nm to 5nm.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127818641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563557
M. Uenuma, Y. Ikoma, Y. Kato, T. Motooka
In this paper, we propose temperature independent AWG using silicon-on-insulator (SOI). Since the length of each waveguide is equal and the second star coupler consists of the hollow slab, the temperature dependence can be eliminated. Wavelength-multiplexed light is divided by the first diffraction order in the output slab region. We fabricated the AWG composed of equal-length waveguides on SOI substrates and the demultiplexing characteristic was measured.
{"title":"Design and fabrication of temperature-independent arrayed-waveguide grating demultiplexers on SOI substrates","authors":"M. Uenuma, Y. Ikoma, Y. Kato, T. Motooka","doi":"10.1109/SOI.2005.1563557","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563557","url":null,"abstract":"In this paper, we propose temperature independent AWG using silicon-on-insulator (SOI). Since the length of each waveguide is equal and the second star coupler consists of the hollow slab, the temperature dependence can be eliminated. Wavelength-multiplexed light is divided by the first diffraction order in the output slab region. We fabricated the AWG composed of equal-length waveguides on SOI substrates and the demultiplexing characteristic was measured.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121031551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563580
D. V. Singh, J. Hergenrother, J. Sleight, Z. Ren, H. Nayfeh, O. Dokumaci, L. Black, D. Chidambarrao, R. Venigalla, J. Pan, B. Tessier, A. Nomura, J. Ott, M. Khare, K. Guarini, M. Ieong, W. Haensch
We have investigated for the first time the effect of stressed contact liners on the performance of fully depleted ultra-thin channel CMOS devices with a raised source/drain. Significant enhancement in mobility and drive current is observed in both nFETs and pFETs. The observed enhancement shows a strong dependence on the Si channel thickness and the height of the raised source/drain, consistent with stress simulations.
{"title":"Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths","authors":"D. V. Singh, J. Hergenrother, J. Sleight, Z. Ren, H. Nayfeh, O. Dokumaci, L. Black, D. Chidambarrao, R. Venigalla, J. Pan, B. Tessier, A. Nomura, J. Ott, M. Khare, K. Guarini, M. Ieong, W. Haensch","doi":"10.1109/SOI.2005.1563580","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563580","url":null,"abstract":"We have investigated for the first time the effect of stressed contact liners on the performance of fully depleted ultra-thin channel CMOS devices with a raised source/drain. Significant enhancement in mobility and drive current is observed in both nFETs and pFETs. The observed enhancement shows a strong dependence on the Si channel thickness and the height of the raised source/drain, consistent with stress simulations.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115835762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563522
J. Nasrullah, J. Burr, G. Leonard Tyler, Y. Nishi
This work focuses on the processing technology that achieves device V/sub T/ adjustability in second and higher layers of short-channel stacked devices. The device mobility and adjusted subthreshold behavior reported here are, however, comparable to those in other TFT work.
{"title":"Edge-defined 90nm TFTs with adjustable V/sub T/ in a 3-D compatible process","authors":"J. Nasrullah, J. Burr, G. Leonard Tyler, Y. Nishi","doi":"10.1109/SOI.2005.1563522","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563522","url":null,"abstract":"This work focuses on the processing technology that achieves device V/sub T/ adjustability in second and higher layers of short-channel stacked devices. The device mobility and adjusted subthreshold behavior reported here are, however, comparable to those in other TFT work.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125186640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563560
J. Sullivan, H. Kirk, Sien Kang, P. Ong, F. Henley
Successful integration of hybrid-orientation substrates into high-volume production requires a layer-transfer process to prepare the substrates. Modifications of SiGen's NanoCleave/spl trade/ layer-transfer process were tested for compatibility to cleave and smooth [110] films, produce multi-stack composites and prepare direct bonded film structures. The technology has the promise to be a viable manufacturing process for strained and unstrained hybrid-orientation substrates used for deep submicron mobility enhancement.
{"title":"Layer-transfer process modifications for fabricating hybrid crystal orientation engineered substrates","authors":"J. Sullivan, H. Kirk, Sien Kang, P. Ong, F. Henley","doi":"10.1109/SOI.2005.1563560","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563560","url":null,"abstract":"Successful integration of hybrid-orientation substrates into high-volume production requires a layer-transfer process to prepare the substrates. Modifications of SiGen's NanoCleave/spl trade/ layer-transfer process were tested for compatibility to cleave and smooth [110] films, produce multi-stack composites and prepare direct bonded film structures. The technology has the promise to be a viable manufacturing process for strained and unstrained hybrid-orientation substrates used for deep submicron mobility enhancement.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128222337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563548
S. Eminente, K. Na, S. Cristoloveanu, L. Mathew, A. Vandooren
We have performed measurements on double-gate Fin-FETs with independent gate contacts in order to study the coupling effects. In these devices, it is possible to separate the coupling between the two lateral channels and the coupling between one lateral channel and the back gate. The lateral coupling effect between the two gates is strong and can be used to tune the threshold voltage of the device whereas the vertical coupling is weaker and depends on the MIGFET size.
{"title":"Lateral and vertical coupling effects in MIGFETs","authors":"S. Eminente, K. Na, S. Cristoloveanu, L. Mathew, A. Vandooren","doi":"10.1109/SOI.2005.1563548","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563548","url":null,"abstract":"We have performed measurements on double-gate Fin-FETs with independent gate contacts in order to study the coupling effects. In these devices, it is possible to separate the coupling between the two lateral channels and the coupling between one lateral channel and the back gate. The lateral coupling effect between the two gates is strong and can be used to tune the threshold voltage of the device whereas the vertical coupling is weaker and depends on the MIGFET size.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1974 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131330598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563519
J. Pelloie
SOI offers an efficient static and dynamic power reduction through V/sub dd/ reduction without sacrificing speed performance. This V/sub dd/ reduction may be combined or not with other circuit techniques: MTCMOS where high-V/sub t/ transistors are connected in series between the core logic and ground/V/sub dd/, gated clock cells where the clock is automatically diabled and not propagated. A low-power SOI circuit may be designed by gathering several blocks using different V/sub dd/ values depending on the speed requirement for each block. In such a case level-shifters are used to adapt the V/sub dd/ difference between the blocks (V/sub dd1/ output to V/sub dd2/ input and V/sub dd2/ output to V/sub dd/1 input). This requires the implementation of several power supply sources at system level. Implementing these techniques adds more design complexity and EDA tools must be able to support them. Making a comparison between bulk and SOI is not an easy task and it cannot be done only at transistor or cell level. The best way is to compare the results(speed, P/sub stat/, P/sub dyn/, area) obtained when a circuit is synthesized, placed and routed using bulk or SOI libraries, including the memories.
{"title":"Using SOI to achieve low-power consumption in digital","authors":"J. Pelloie","doi":"10.1109/SOI.2005.1563519","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563519","url":null,"abstract":"SOI offers an efficient static and dynamic power reduction through V/sub dd/ reduction without sacrificing speed performance. This V/sub dd/ reduction may be combined or not with other circuit techniques: MTCMOS where high-V/sub t/ transistors are connected in series between the core logic and ground/V/sub dd/, gated clock cells where the clock is automatically diabled and not propagated. A low-power SOI circuit may be designed by gathering several blocks using different V/sub dd/ values depending on the speed requirement for each block. In such a case level-shifters are used to adapt the V/sub dd/ difference between the blocks (V/sub dd1/ output to V/sub dd2/ input and V/sub dd2/ output to V/sub dd/1 input). This requires the implementation of several power supply sources at system level. Implementing these techniques adds more design complexity and EDA tools must be able to support them. Making a comparison between bulk and SOI is not an easy task and it cannot be done only at transistor or cell level. The best way is to compare the results(speed, P/sub stat/, P/sub dyn/, area) obtained when a circuit is synthesized, placed and routed using bulk or SOI libraries, including the memories.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134479263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563590
H. Lin, S. Tiwari
A novel, simple and bipolar-injection based nonvolatile field-effect memory cell is demonstrated in silicon-on-insulator CMOS technology. Programming time down to 8 ns are achieved together with erase times of a milli-second. The characteristics, compactness and compatibility with CMOS processes suggest suitability of the structure for embedded programmable and reprogrammable applications, and extensible to 3D applications. This extended abstract summarizes the technology and experimental characteristics of the device.
{"title":"A novel nonvolatile memory cell for programmable logic","authors":"H. Lin, S. Tiwari","doi":"10.1109/SOI.2005.1563590","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563590","url":null,"abstract":"A novel, simple and bipolar-injection based nonvolatile field-effect memory cell is demonstrated in silicon-on-insulator CMOS technology. Programming time down to 8 ns are achieved together with erase times of a milli-second. The characteristics, compactness and compatibility with CMOS processes suggest suitability of the structure for embedded programmable and reprogrammable applications, and extensible to 3D applications. This extended abstract summarizes the technology and experimental characteristics of the device.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116056124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563577
O. Bon, L. Boissonnet, O. Gonnard, S. Chouteau, B. Reynard, A. Perrotin, C. Raynaud
We have added to a 0.13/spl mu/m thin SOI CMOS core process a high competitive SOI NLDEMOS which presents excellent power switch and analog characteristics. Measurements have demonstrated that both drift and BC design rules allow to obtain HV devices (BV > 15V) with a low S.Ron and a low leakage.
{"title":"High voltage devices added to a 0.13/spl mu/m high resistivity thin SOI CMOS process for mixed analog-RF circuits","authors":"O. Bon, L. Boissonnet, O. Gonnard, S. Chouteau, B. Reynard, A. Perrotin, C. Raynaud","doi":"10.1109/SOI.2005.1563577","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563577","url":null,"abstract":"We have added to a 0.13/spl mu/m thin SOI CMOS core process a high competitive SOI NLDEMOS which presents excellent power switch and analog characteristics. Measurements have demonstrated that both drift and BC design rules allow to obtain HV devices (BV > 15V) with a low S.Ron and a low leakage.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121058937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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