Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563558
H. Fuwa, K. Hayakawa
Using TLP tester and device simulation, we investigated the I-V characteristics of two devices and the behavior of the NPN in high current region. The NPN is suitable device for ESD protection circuits. Especially, collector to base space is an important design parameter. We achieved low holding voltage, low on-resistance and high failure current by optimizing collector to base space of the NPN. Therefore we propose the ESD protection using circuits that consists of the NPN automotive applications.
{"title":"New design concept of ESD protection circuits in SOI BiCDMOS LSI for automotive applications","authors":"H. Fuwa, K. Hayakawa","doi":"10.1109/SOI.2005.1563558","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563558","url":null,"abstract":"Using TLP tester and device simulation, we investigated the I-V characteristics of two devices and the behavior of the NPN in high current region. The NPN is suitable device for ESD protection circuits. Especially, collector to base space is an important design parameter. We achieved low holding voltage, low on-resistance and high failure current by optimizing collector to base space of the NPN. Therefore we propose the ESD protection using circuits that consists of the NPN automotive applications.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132962907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563582
P. Gouker, B. Tyrrell, P. Wyatt, E. Austin, A. Soares, C.K. Chen, J. Burns
Static and dynamic circuits were fabricated in the MIT-LL 0.18-/spl mu/m FDSOI CMOS process, and exhibited a high tolerance to total dose radiation up to 1 Mrad (SiO/sub 2/). Circuits were designed using conventional design rules and layout techniques, i.e., they are not radhard-by-design. Hardening was done at the circuit fabrication level using process enhancements. These are the first circuit-level hardness results reported to date for these new enhancements.
{"title":"Total dose performance of conventional static and dynamic circuits in a radhard 0.18-/spl mu/m FDSOI process","authors":"P. Gouker, B. Tyrrell, P. Wyatt, E. Austin, A. Soares, C.K. Chen, J. Burns","doi":"10.1109/SOI.2005.1563582","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563582","url":null,"abstract":"Static and dynamic circuits were fabricated in the MIT-LL 0.18-/spl mu/m FDSOI CMOS process, and exhibited a high tolerance to total dose radiation up to 1 Mrad (SiO/sub 2/). Circuits were designed using conventional design rules and layout techniques, i.e., they are not radhard-by-design. Hardening was done at the circuit fabrication level using process enhancements. These are the first circuit-level hardness results reported to date for these new enhancements.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134609419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563530
M. Iijima, M. Kitamura, K. Hamada, K. Fukuoka, M. Numa, A. Tada, S. Maegawa
In this paper, we propose an active body-biasing controlled (ABC)-bootstrap PTL (pass-transistor logic) on PD-SOI at 0.5 V-V/sub DD/ for ultra low power design. Applying active body-biasing to bootstrap PTL is the key for higher performance without output voltage loss by boosting gate voltage with coupling capacitance between source and body. Lowering V/sub th/ by body biasing also contributes for high speed operation. Experimental results have shown improvement in both delay time and power consumption.
{"title":"Active body-biasing control technique for bootstrap pass-transistor logic on PD-SOI at 0.5V-V/sub DD/","authors":"M. Iijima, M. Kitamura, K. Hamada, K. Fukuoka, M. Numa, A. Tada, S. Maegawa","doi":"10.1109/SOI.2005.1563530","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563530","url":null,"abstract":"In this paper, we propose an active body-biasing controlled (ABC)-bootstrap PTL (pass-transistor logic) on PD-SOI at 0.5 V-V/sub DD/ for ultra low power design. Applying active body-biasing to bootstrap PTL is the key for higher performance without output voltage loss by boosting gate voltage with coupling capacitance between source and body. Lowering V/sub th/ by body biasing also contributes for high speed operation. Experimental results have shown improvement in both delay time and power consumption.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133476331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563572
Z.B. Zhang, S.C. Song, K. Choi, J. H. Sim, P. Majhi, B. Lee
This paper describes a simple process that can tune the work function of ALD TaCN gate electrode on HfO/sub 2/ from 4.47eV to 4.77eV by adding a CVD TiN overlayer. It also discusses the device characteristics of TaCN and TiN/TaCN (TaCN with a TiN overlayer) metal gate/high-k MOSFETs and presents a manufacturable process for integrating dual metal gate/high-k CMOS in a FD-FET technology.
{"title":"An integratable dual metal gate/high-k CMOS solution for FD-SOI and MuGFET technologies","authors":"Z.B. Zhang, S.C. Song, K. Choi, J. H. Sim, P. Majhi, B. Lee","doi":"10.1109/SOI.2005.1563572","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563572","url":null,"abstract":"This paper describes a simple process that can tune the work function of ALD TaCN gate electrode on HfO/sub 2/ from 4.47eV to 4.77eV by adding a CVD TiN overlayer. It also discusses the device characteristics of TaCN and TiN/TaCN (TaCN with a TiN overlayer) metal gate/high-k MOSFETs and presents a manufacturable process for integrating dual metal gate/high-k CMOS in a FD-FET technology.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130585162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563545
C. Tan, K.N. Chen, A. Fan, R. Reif
We have successfully demonstrated a back-to-face ultra-thin silicon layer stacking based on low temperature wafer bonding and etch-back. This type of silicon layer stacking can be expanded to wafers with device and interconnect layers to fabricate three-dimensional integrated circuits (3D ICs). Electrical connection between layers can be achieved by interlayer vertical via formed by bonded Cu layers.
{"title":"A back-to-face silicon layer stacking for three-dimensional integration","authors":"C. Tan, K.N. Chen, A. Fan, R. Reif","doi":"10.1109/SOI.2005.1563545","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563545","url":null,"abstract":"We have successfully demonstrated a back-to-face ultra-thin silicon layer stacking based on low temperature wafer bonding and etch-back. This type of silicon layer stacking can be expanded to wafers with device and interconnect layers to fabricate three-dimensional integrated circuits (3D ICs). Electrical connection between layers can be achieved by interlayer vertical via formed by bonded Cu layers.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123629057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563567
Y. Mishima, A. Mimura, M. Fukuda, H. Ochimizu
We describe a low-temperature process for fabricating strained silicon on insulator (SOI) substrates using excimer laser annealing technology. We used an excimer laser to relax the SiGe layer on the SOI substrate. We can fabricate ultra-thin strained SOI by removing the relaxed SiGe layer on the SOI after laser annealing. Strains are investigated using ultraviolet (UV)-Raman spectroscopy and transmission electron microscopy (TEM).
{"title":"Ultra-thin strained Si on insulator substrate using laser annealing","authors":"Y. Mishima, A. Mimura, M. Fukuda, H. Ochimizu","doi":"10.1109/SOI.2005.1563567","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563567","url":null,"abstract":"We describe a low-temperature process for fabricating strained silicon on insulator (SOI) substrates using excimer laser annealing technology. We used an excimer laser to relax the SiGe layer on the SOI substrate. We can fabricate ultra-thin strained SOI by removing the relaxed SiGe layer on the SOI after laser annealing. Strains are investigated using ultraviolet (UV)-Raman spectroscopy and transmission electron microscopy (TEM).","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123798315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563524
S. Schwantes, A. Heid, F. Dietz, M. Graf, V. Dudek
Smart power SOI technologies are becoming popular because of better isolation. The SOI technology introduces a new electrode, the substrate electrode referred to as back gate. Several papers have reported back gate induced leakage current. This work reports a new leakage mechanism induced by the interaction of the neighbouring device and that back gate. Moreover, possible countermeasures for a 0.8 /spl mu/m 80V SOI technology are presented.
{"title":"A new leakage mechanism in SOI smart power technologies","authors":"S. Schwantes, A. Heid, F. Dietz, M. Graf, V. Dudek","doi":"10.1109/SOI.2005.1563524","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563524","url":null,"abstract":"Smart power SOI technologies are becoming popular because of better isolation. The SOI technology introduces a new electrode, the substrate electrode referred to as back gate. Several papers have reported back gate induced leakage current. This work reports a new leakage mechanism induced by the interaction of the neighbouring device and that back gate. Moreover, possible countermeasures for a 0.8 /spl mu/m 80V SOI technology are presented.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127265490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563589
O. Thomas, A. Vladimirescu, A. Amara
For SRAM circuits operated at 0.5V reliable readout of the stored information is challenging due to a voltage swing of tens of mV. Two readout topologies described in this paper for ultra-low-voltage (ULV) SOI-CMOS SRAMs exploit unique features of partially-depleted (PD)-SOI transistors to perform current rather than voltage sensing. The analysis presented leads to the dimensioning of the sense amplifier transistors for robust operation with a maximum number of cells per column of the SRAM. Simulations of the presented circuits demonstrate that the information stored in an SRAM with a four-transistor CMOS-SOI cell can be reliably accessed in 3ns with 180nW power consumption.
{"title":"Ultra-low-voltage current-sense read circuits for CMOS SOI SRAMs","authors":"O. Thomas, A. Vladimirescu, A. Amara","doi":"10.1109/SOI.2005.1563589","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563589","url":null,"abstract":"For SRAM circuits operated at 0.5V reliable readout of the stored information is challenging due to a voltage swing of tens of mV. Two readout topologies described in this paper for ultra-low-voltage (ULV) SOI-CMOS SRAMs exploit unique features of partially-depleted (PD)-SOI transistors to perform current rather than voltage sensing. The analysis presented leads to the dimensioning of the sense amplifier transistors for robust operation with a maximum number of cells per column of the SRAM. Simulations of the presented circuits demonstrate that the information stored in an SRAM with a four-transistor CMOS-SOI cell can be reliably accessed in 3ns with 180nW power consumption.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121662834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563535
D. Lederer, O. Rozeau, J. Raskin
In this work we present an original method based on 3-port RF measurements to accurately extract the body resistance (R/sub be/) in body-accessed PD SOI MOSFETs. This method can be used to assess the validity of compact models such as BSIMSOI. The RF body access also enabled a precise characterization of intrinsic and extrinsic body capacitances. A complete 3-port model was then derived and further validated on DT MOSFET measurements by connecting the body to the gate terminal.
在这项工作中，我们提出了一种基于3端口射频测量的原始方法，以准确提取体接入PD SOI mosfet中的体电阻(R/sub /)。该方法可用于评价BSIMSOI等紧凑模型的有效性。射频体接入也能够精确表征内在和外在体电容。然后推导出一个完整的3端口模型，并通过将主体连接到栅极终端在DT MOSFET测量上进一步验证。
{"title":"Wideband characterization of body-accessed PD SOI MOSFETs with multiport measurements","authors":"D. Lederer, O. Rozeau, J. Raskin","doi":"10.1109/SOI.2005.1563535","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563535","url":null,"abstract":"In this work we present an original method based on 3-port RF measurements to accurately extract the body resistance (R/sub be/) in body-accessed PD SOI MOSFETs. This method can be used to assess the validity of compact models such as BSIMSOI. The RF body access also enabled a precise characterization of intrinsic and extrinsic body capacitances. A complete 3-port model was then derived and further validated on DT MOSFET measurements by connecting the body to the gate terminal.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131390962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563579
N. Miura, Y. Domae, T. Sakata, M. Watanabe, T. Okamura, T. Chiba, K. Fukuda, J. Ida
In this paper, we present an undoped thin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS with source/drain-to-gate non-overlapped structure for ultra low leak (ULL) transistor. The fabricated device achieved a cutoff frequency f/sub T/ of 65GHz with I/sub off/< 0.1pA//spl mu/m (GIDL-free). The proposed inverted-gate implantation/planar-type SOI is practical and low-cost solution for coin-battery applications.
{"title":"Undoped thin film FD-SOI CMOS with source/drain-to-gate non-overlapped structure for ultra low leak applications","authors":"N. Miura, Y. Domae, T. Sakata, M. Watanabe, T. Okamura, T. Chiba, K. Fukuda, J. Ida","doi":"10.1109/SOI.2005.1563579","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563579","url":null,"abstract":"In this paper, we present an undoped thin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS with source/drain-to-gate non-overlapped structure for ultra low leak (ULL) transistor. The fabricated device achieved a cutoff frequency f/sub T/ of 65GHz with I/sub off/< 0.1pA//spl mu/m (GIDL-free). The proposed inverted-gate implantation/planar-type SOI is practical and low-cost solution for coin-battery applications.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116981167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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