Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815452
Shenjie Wang, C. Dehollain
A 460 kS/s 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with rail-to-rail input range is proposed for acquiring capacitive sensor. The specifications of ADC are optimized at system level, emphasizing the ADC following a switched-capacitor (SC) capacitance-to-voltage converter (C2V). A bootstrap switch with body effect reduction is adopted to provide the rail-to-rail processing ability. The charge redistribution converter is realized by a single-ended cascaded binary-weighted (CBW) capacitive digital-to-analog converter (DAC). Self-timing SAR logic borrows extra half cycle relaxing the settling of preamps and reduces the power consumption. At a sample rate of 460 kS/s, the 10-bit SAR ADC achieves an ENOB of 9.9 bit and consumes 35 μW with 1.8 V power supply, resulting in an energy efficiency of 80 fJ/step. The circuits are designed and simulated with parasitic models using a commercially available 180 nm CMOS process.
{"title":"Design of a rail-to-rail 460 kS/s 10-bit SAR ADC for capacitive sensor interface","authors":"Shenjie Wang, C. Dehollain","doi":"10.1109/ICECS.2013.6815452","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815452","url":null,"abstract":"A 460 kS/s 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with rail-to-rail input range is proposed for acquiring capacitive sensor. The specifications of ADC are optimized at system level, emphasizing the ADC following a switched-capacitor (SC) capacitance-to-voltage converter (C2V). A bootstrap switch with body effect reduction is adopted to provide the rail-to-rail processing ability. The charge redistribution converter is realized by a single-ended cascaded binary-weighted (CBW) capacitive digital-to-analog converter (DAC). Self-timing SAR logic borrows extra half cycle relaxing the settling of preamps and reduces the power consumption. At a sample rate of 460 kS/s, the 10-bit SAR ADC achieves an ENOB of 9.9 bit and consumes 35 μW with 1.8 V power supply, resulting in an energy efficiency of 80 fJ/step. The circuits are designed and simulated with parasitic models using a commercially available 180 nm CMOS process.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125096908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815486
Sherif H. Abdel Haleem, A. Radwan, S. Abd-El-Hafiz
This paper presents a new encryption scheme based on the combination between Linear Feedback Shift Register (LFSR) and generalized Feistel networks (GFN). The construction of each GFN depends on Substitution Boxes (S-Boxes) and its operation requires a key. The encryption key length is dynamic and can be controlled via the initial values of the LFSR, S-Boxes, and the number of GFN stages. The performance of the proposed scheme is tested using the standard statistical measures and the NIST statistical test suite. Moreover, sensitivity analysis of the encryption key is performed.
{"title":"Utilizing LFSR and Feistel networks in image encryption","authors":"Sherif H. Abdel Haleem, A. Radwan, S. Abd-El-Hafiz","doi":"10.1109/ICECS.2013.6815486","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815486","url":null,"abstract":"This paper presents a new encryption scheme based on the combination between Linear Feedback Shift Register (LFSR) and generalized Feistel networks (GFN). The construction of each GFN depends on Substitution Boxes (S-Boxes) and its operation requires a key. The encryption key length is dynamic and can be controlled via the initial values of the LFSR, S-Boxes, and the number of GFN stages. The performance of the proposed scheme is tested using the standard statistical measures and the NIST statistical test suite. Moreover, sensitivity analysis of the encryption key is performed.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"37 18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123660119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815508
Ayman A. Salem, Mohamed A. Abd El-Ghany, K. Hofmann
Bose-Chaudhuri-Hocquenghem (BCH) coding based on chip communication network is proposed to achieve optimal Energy-Performability trade-off. The proposed encoding and decoding scheme is applied to Butterfly-fat-tree (BFT) architecture. The proposed design improves Perform-ability range in comparison with conventional schemes while saving energy by 5%. BCH achieves high perform-ability (0.9) at high noise effect (σN =0.135V). At short wire lengths (0.05mm), BCH saves energy 5% while increasing perform-ability (0.9) and reliability.
{"title":"Performability measurement of coding algorithms for network on chip","authors":"Ayman A. Salem, Mohamed A. Abd El-Ghany, K. Hofmann","doi":"10.1109/ICECS.2013.6815508","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815508","url":null,"abstract":"Bose-Chaudhuri-Hocquenghem (BCH) coding based on chip communication network is proposed to achieve optimal Energy-Performability trade-off. The proposed encoding and decoding scheme is applied to Butterfly-fat-tree (BFT) architecture. The proposed design improves Perform-ability range in comparison with conventional schemes while saving energy by 5%. BCH achieves high perform-ability (0.9) at high noise effect (σN =0.135V). At short wire lengths (0.05mm), BCH saves energy 5% while increasing perform-ability (0.9) and reliability.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123667397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815504
A. Hakam, N. A. Aly, M. Khalid, S. Jimaa, S. Al-Araji
This paper addresses the performance of Multiple-Input-Multiple-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM), MIMO-OFDM communication system in environments where the interfering noise exhibits non-Gaussian behavior due to impulsive phenomena. It presents the design and simulation of an adaptive receiver technique that aims to minimize the effect of impulsive noise on the performance of the MIMO-OFDM communication system under Additive White Gaussian Noise (AWGN) channel. The proposed adaptive technique uses three different types of algorithms, an Adaptive Recursive least Square (RLS), Adaptive Normalized Least Mean Square (NLMS), and Variable Step-size Adaptive Normalized Least Mean Square (VSNLMS). The real concern in generating the impulsive noise is to have the main characteristics that emulate the actual impulsive noise. Hence the impulsive noise is generated and modeled based on reference [4] using Matlab/Simulink. The bit-error-rate (BER) performance of the MIMO-OFDM system in an impulsive noise environment was evaluated. The proposed adaptive receivers' technique offers a novel approach in reducing the effect of the impulsive noise in MIMO-OFDM system.
{"title":"Impulsive noise reduction in MIMO-OFDM systems using adaptive receiver structures","authors":"A. Hakam, N. A. Aly, M. Khalid, S. Jimaa, S. Al-Araji","doi":"10.1109/ICECS.2013.6815504","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815504","url":null,"abstract":"This paper addresses the performance of Multiple-Input-Multiple-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM), MIMO-OFDM communication system in environments where the interfering noise exhibits non-Gaussian behavior due to impulsive phenomena. It presents the design and simulation of an adaptive receiver technique that aims to minimize the effect of impulsive noise on the performance of the MIMO-OFDM communication system under Additive White Gaussian Noise (AWGN) channel. The proposed adaptive technique uses three different types of algorithms, an Adaptive Recursive least Square (RLS), Adaptive Normalized Least Mean Square (NLMS), and Variable Step-size Adaptive Normalized Least Mean Square (VSNLMS). The real concern in generating the impulsive noise is to have the main characteristics that emulate the actual impulsive noise. Hence the impulsive noise is generated and modeled based on reference [4] using Matlab/Simulink. The bit-error-rate (BER) performance of the MIMO-OFDM system in an impulsive noise environment was evaluated. The proposed adaptive receivers' technique offers a novel approach in reducing the effect of the impulsive noise in MIMO-OFDM system.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122672449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815538
Carlos J. Solis, G. Rincón-Mora
Battery-supplied systems demand fast, power efficient, and compact power supplies. Although linear regulators are quick and small, tiny batteries cannot sustain their losses for long. Pulse-width-modulated (PWM) switchers are considerably more efficient, but also slower. Luckily, hysteretic converters can respond within one switching cycle. Stabilizing the system for maximum speed with a hysteretic inductor-current loop, however, which is not linear, is not straightforward. This paper shows how load dumps delay the response of the hysteretic oscillator that the current loop implements. Knowing the worse-case dump and the delay it causes reveals the lowest output capacitance that maintains stable operation at maximum speed. The converter designed here can therefore recover, as predicted, from 100-mA load dumps in 2 μs with 10 μF and 45° of phase margin.
{"title":"Stability analysis & design of hysteretic current-mode switched-inductor buck DC-DC converters","authors":"Carlos J. Solis, G. Rincón-Mora","doi":"10.1109/ICECS.2013.6815538","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815538","url":null,"abstract":"Battery-supplied systems demand fast, power efficient, and compact power supplies. Although linear regulators are quick and small, tiny batteries cannot sustain their losses for long. Pulse-width-modulated (PWM) switchers are considerably more efficient, but also slower. Luckily, hysteretic converters can respond within one switching cycle. Stabilizing the system for maximum speed with a hysteretic inductor-current loop, however, which is not linear, is not straightforward. This paper shows how load dumps delay the response of the hysteretic oscillator that the current loop implements. Knowing the worse-case dump and the delay it causes reveals the lowest output capacitance that maintains stable operation at maximum speed. The converter designed here can therefore recover, as predicted, from 100-mA load dumps in 2 μs with 10 μF and 45° of phase margin.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123245309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815367
A. Adly, O. Mahgoub, S. Abd-El-Hafiz
Single-phase squirrel cage induction motors are vastly used in a wide variety of domestic and industrial applications. As a consequence of market globalization, motor manufacturers are facing an increasingly competitive environment that mandates the adoption of design strategies yielding better performance at lower costs. This fact highlights the importance of having innovative experimental testing means and setups within manufacturers R&D divisions. This paper presents the details of a low cost PC-controlled test bench that was designed and constructed for fractional horse power (FHP) single-phase induction motors. Inference of the various motor parameters and performance is carried out by utilizing the evolutionary particle swarm optimization (PSO) algorithm to solve an inverse problem involving a limited set of multi-speed loading measurements. Full details of the test bench as well as parameter inference evolutionary approach are given in paper.
{"title":"Design and construction of a low cost single-phase induction motor test bench","authors":"A. Adly, O. Mahgoub, S. Abd-El-Hafiz","doi":"10.1109/ICECS.2013.6815367","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815367","url":null,"abstract":"Single-phase squirrel cage induction motors are vastly used in a wide variety of domestic and industrial applications. As a consequence of market globalization, motor manufacturers are facing an increasingly competitive environment that mandates the adoption of design strategies yielding better performance at lower costs. This fact highlights the importance of having innovative experimental testing means and setups within manufacturers R&D divisions. This paper presents the details of a low cost PC-controlled test bench that was designed and constructed for fractional horse power (FHP) single-phase induction motors. Inference of the various motor parameters and performance is carried out by utilizing the evolutionary particle swarm optimization (PSO) algorithm to solve an inverse problem involving a limited set of multi-speed loading measurements. Full details of the test bench as well as parameter inference evolutionary approach are given in paper.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126595484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815416
I. Vourkas, G. Sirakoulis
Within a growing variety of systems that exhibit memristive behavior nowadays, most of the research has so far focused on the properties of these single devices, whereas very little is known about their response when they are organized into networks. In this work we study the composite characteristics of memristive elements connected in regular one-dimensional configurations. Using a nonlinear memristor model we carry out simulations and analyze the characteristics of complex memristor circuits, as well as investigate the relationships among the single devices. We show how composite memristive systems can be efficiently built out of individual memristive devices, presenting different electrical characteristics from their structural elements. Finally, we exploit the threshold-dependent nonlinear memristive behavior and elaborate the presented memristive networks to build analog computational circuits like a fully passive memristive analog decimal counter. The presented analysis provides intuition into the response of complex memristive networks and motivates for further elaboration of their composite and dynamic complexity for the creation of sophisticated memristive systems.
{"title":"On the analog computational characteristics of memristive networks","authors":"I. Vourkas, G. Sirakoulis","doi":"10.1109/ICECS.2013.6815416","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815416","url":null,"abstract":"Within a growing variety of systems that exhibit memristive behavior nowadays, most of the research has so far focused on the properties of these single devices, whereas very little is known about their response when they are organized into networks. In this work we study the composite characteristics of memristive elements connected in regular one-dimensional configurations. Using a nonlinear memristor model we carry out simulations and analyze the characteristics of complex memristor circuits, as well as investigate the relationships among the single devices. We show how composite memristive systems can be efficiently built out of individual memristive devices, presenting different electrical characteristics from their structural elements. Finally, we exploit the threshold-dependent nonlinear memristive behavior and elaborate the presented memristive networks to build analog computational circuits like a fully passive memristive analog decimal counter. The presented analysis provides intuition into the response of complex memristive networks and motivates for further elaboration of their composite and dynamic complexity for the creation of sophisticated memristive systems.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131831513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815385
C. Kauth, M. Pastre, M. Kayal
To foster the advent of miniaturized, self-controlled and highly sensitive nanoelectromechanical systems, a model for electromechanical resonator operation under the control of an adaptative phase locked loop is presented. The implications of limited observability, due to detectability thresholds and noise, on start-up and oscillation stability are analysed. Minimum system requirements, necessary for proper oscillation, are defined and a strategy for robust system design, under the constraint of finite real-world bandwidths, finally crystallizes.
{"title":"Robust control of oscillating NEMS sensors","authors":"C. Kauth, M. Pastre, M. Kayal","doi":"10.1109/ICECS.2013.6815385","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815385","url":null,"abstract":"To foster the advent of miniaturized, self-controlled and highly sensitive nanoelectromechanical systems, a model for electromechanical resonator operation under the control of an adaptative phase locked loop is presented. The implications of limited observability, due to detectability thresholds and noise, on start-up and oscillation stability are analysed. Minimum system requirements, necessary for proper oscillation, are defined and a strategy for robust system design, under the constraint of finite real-world bandwidths, finally crystallizes.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115080836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815512
Amine Ait Si Ali, A. Amira, F. Bensaali, M. Benammar
One of the significant stages in a gas identification system is dimensionality reduction to speed up the processing part. This is even more important when the system is implemented on a hardware platform where the resources are limited. This paper presents the design and the implementation of the learning and testing phases of principal component analysis (PCA) that can be used in a gas identification system on the heterogeneous Zynq platform. All steps of PCA starting from the mean computation to the projection of data onto the new space, passing by the normalization process, covariance matrix and the eigenvectors computation are developed in C and synthesized using the new Xilinx VIVADO high level synthesis (HLS). The computation of the eigenvectors was based on the iterative Jacobi method. The designed hardware for computing the learning part of PCA on the Zynq system on chip showed that it can be faster than its 64-bit Intel i7-3770 processor counterpart with a speed up of 1.41. Optimization techniques using HLS directives were also utilised in the hardware implementation of the testing part of the PCA to speed up the design and reduce its latency.
{"title":"Hardware PCA for gas identification systems using high level synthesis on the Zynq SoC","authors":"Amine Ait Si Ali, A. Amira, F. Bensaali, M. Benammar","doi":"10.1109/ICECS.2013.6815512","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815512","url":null,"abstract":"One of the significant stages in a gas identification system is dimensionality reduction to speed up the processing part. This is even more important when the system is implemented on a hardware platform where the resources are limited. This paper presents the design and the implementation of the learning and testing phases of principal component analysis (PCA) that can be used in a gas identification system on the heterogeneous Zynq platform. All steps of PCA starting from the mean computation to the projection of data onto the new space, passing by the normalization process, covariance matrix and the eigenvectors computation are developed in C and synthesized using the new Xilinx VIVADO high level synthesis (HLS). The computation of the eigenvectors was based on the iterative Jacobi method. The designed hardware for computing the learning part of PCA on the Zynq system on chip showed that it can be faster than its 64-bit Intel i7-3770 processor counterpart with a speed up of 1.41. Optimization techniques using HLS directives were also utilised in the hardware implementation of the testing part of the PCA to speed up the design and reduce its latency.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130208329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815380
T. Silva, L. Cruz, L. Agostini
Seeking for higher encoding efficiency, the emerging High Efficiency Video Coding (HEVC) standard has adopted new encoding techniques such as recursive quadtree structure, flexible block partitioning and larger size blocks. However, this improved efficiency leads to greater computational complexity. This paper deals with complexity reduction of the HEVC-based multiview video coding proposing a new inter-view prediction technique, fully compliant with the HEVC standard. This new technique uses the coding unit (CU) tree depths used in the base view as a depth threshold to be used in the dependent views. When compared to HEVC simulcast the proposed method achieves a complexity reduction of up to 50.32%, at the cost of an average BD-PSNR loss of 0.03 dB.
为了追求更高的编码效率，新兴的高效视频编码(High efficiency Video Coding, HEVC)标准采用了递归四叉树结构、灵活块划分和更大块大小等新的编码技术。然而，这种效率的提高导致了更大的计算复杂性。本文研究了基于HEVC的多视点视频编码的复杂度降低问题，提出了一种新的完全符合HEVC标准的视点间预测技术。这种新技术使用基视图中使用的编码单元(CU)树深度作为依赖视图中使用的深度阈值。与HEVC同时广播相比，该方法的复杂度降低了50.32%，而平均BD-PSNR损失为0.03 dB。
{"title":"Inter-view prediction of coding tree depth for HEVC-based multiview video coding","authors":"T. Silva, L. Cruz, L. Agostini","doi":"10.1109/ICECS.2013.6815380","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815380","url":null,"abstract":"Seeking for higher encoding efficiency, the emerging High Efficiency Video Coding (HEVC) standard has adopted new encoding techniques such as recursive quadtree structure, flexible block partitioning and larger size blocks. However, this improved efficiency leads to greater computational complexity. This paper deals with complexity reduction of the HEVC-based multiview video coding proposing a new inter-view prediction technique, fully compliant with the HEVC standard. This new technique uses the coding unit (CU) tree depths used in the base view as a depth threshold to be used in the dependent views. When compared to HEVC simulcast the proposed method achieves a complexity reduction of up to 50.32%, at the cost of an average BD-PSNR loss of 0.03 dB.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129687814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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