Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401829
A. Aita, K. Makinwa
Due to the trend towards low power operation, as in autonomous systems where power constraints are very high, sensors are increasingly being required to dissipate very low power (few microwatts). In this paper, a low-power version of a smart temperature sensor in 0.7 mum CMOS technology is presented. Based on accuracy requirements, a minimum biasing current Ibias for the sensor's bipolar core is determined. Measurement results for Ibias = 250 nA and CS = 1.25 pF (ADC sampling capacitor) are shown. An inaccuracy below plusmn0.15degC from -55degC to 125degC is achievable with a two-point calibration.
{"title":"Low-power and accurate operation of a CMOS smart temperature sensor based on bipolar devices and Σ̄ A/D converter","authors":"A. Aita, K. Makinwa","doi":"10.1109/RME.2007.4401829","DOIUrl":"https://doi.org/10.1109/RME.2007.4401829","url":null,"abstract":"Due to the trend towards low power operation, as in autonomous systems where power constraints are very high, sensors are increasingly being required to dissipate very low power (few microwatts). In this paper, a low-power version of a smart temperature sensor in 0.7 mum CMOS technology is presented. Based on accuracy requirements, a minimum biasing current Ibias for the sensor's bipolar core is determined. Measurement results for Ibias = 250 nA and CS = 1.25 pF (ADC sampling capacitor) are shown. An inaccuracy below plusmn0.15degC from -55degC to 125degC is achievable with a two-point calibration.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115602556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401840
Zhipeng Ye, Michael Peter Kennedy
A novel noise reduction technique for a fractional-N frequency synthesizer using a multiphase voltage-controlled oscillator (VCO) is presented in this paper. It is shown that both in-band and out-of-band noise can be reduced by 6 dB for every two-fold increase in the number of phases. A reduced complexity multi-input multi-modulus delta-sigma modulator controlled frequency divider is proposed which combines the functions of frequency division and phase selection. Its power and area consumption are much less than those of conventional multi-phase frequency dividers. Simulation results confirm the analytical predictions.
{"title":"Noise reduction in fractional-N frequency synthesizers with multiphase VCO","authors":"Zhipeng Ye, Michael Peter Kennedy","doi":"10.1109/RME.2007.4401840","DOIUrl":"https://doi.org/10.1109/RME.2007.4401840","url":null,"abstract":"A novel noise reduction technique for a fractional-N frequency synthesizer using a multiphase voltage-controlled oscillator (VCO) is presented in this paper. It is shown that both in-band and out-of-band noise can be reduced by 6 dB for every two-fold increase in the number of phases. A reduced complexity multi-input multi-modulus delta-sigma modulator controlled frequency divider is proposed which combines the functions of frequency division and phase selection. Its power and area consumption are much less than those of conventional multi-phase frequency dividers. Simulation results confirm the analytical predictions.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131741477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401804
C. Sahnine, D. Callonnec, N. Zergainoh, F. Pétrot
OFDM modulation is widely used in several communications systems. An advanced modulation scheme, called OFDM/OQAM with IOTA pulse shaping has been identified as one potential method to enhance the performance of these systems. Nevertheless, the IOTA filtering increases the architecture complexity. Moreover, for high-throughput communication of the order of about of hundreds of MHz, we showed that pipelined FFT architecture combined with IOTA filter are not area and power-efficient coarse-grained configurable architecture using parallel architecture and combined with pipelined strategy, offers a better tradeoff between scalability, performance and low power.
{"title":"Efficient design approach and advanced architectures for universal OFDM systems","authors":"C. Sahnine, D. Callonnec, N. Zergainoh, F. Pétrot","doi":"10.1109/RME.2007.4401804","DOIUrl":"https://doi.org/10.1109/RME.2007.4401804","url":null,"abstract":"OFDM modulation is widely used in several communications systems. An advanced modulation scheme, called OFDM/OQAM with IOTA pulse shaping has been identified as one potential method to enhance the performance of these systems. Nevertheless, the IOTA filtering increases the architecture complexity. Moreover, for high-throughput communication of the order of about of hundreds of MHz, we showed that pipelined FFT architecture combined with IOTA filter are not area and power-efficient coarse-grained configurable architecture using parallel architecture and combined with pipelined strategy, offers a better tradeoff between scalability, performance and low power.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133484143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401816
A. Lombardi, P. Malcovati, A. Basto, E. Bonizzoni, F. Maloberti
This paper presents the design of a low power sinc3 filter implementing a decimation factor by 16 and suitable for a second order SigmaDelta modulators running at 256 MHz. The circuit uses the cascade of two stages and consumes only 48.1 muW, with 1.2 V voltage supply. The ultra-low power features come from both an architectural optimization and the use of suitable transistor level schemes. The circuit, simulated in a 0.18-mum CMOS technology, improves the overall power consumption by about 75.4% with respect to an already optimum conventional design.
本文设计了一种低功耗的sinc3滤波器，实现了16的抽取因子，适用于工作在256mhz的二阶SigmaDelta调制器。该电路采用两级级联，功耗仅为48.1 muW，电压为1.2 V。超低功耗特性来自架构优化和使用合适的晶体管级方案。该电路采用0.18 μ m CMOS技术进行模拟，与已经达到最佳的传统设计相比，总功耗提高了约75.4%。
{"title":"An optimized two stages low power sinc3 filter for ΣΔ modulators","authors":"A. Lombardi, P. Malcovati, A. Basto, E. Bonizzoni, F. Maloberti","doi":"10.1109/RME.2007.4401816","DOIUrl":"https://doi.org/10.1109/RME.2007.4401816","url":null,"abstract":"This paper presents the design of a low power sinc3 filter implementing a decimation factor by 16 and suitable for a second order SigmaDelta modulators running at 256 MHz. The circuit uses the cascade of two stages and consumes only 48.1 muW, with 1.2 V voltage supply. The ultra-low power features come from both an architectural optimization and the use of suitable transistor level schemes. The circuit, simulated in a 0.18-mum CMOS technology, improves the overall power consumption by about 75.4% with respect to an already optimum conventional design.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133644126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401853
A. De Marcellis, G. Ferri, V. Stornelli
In this paper we present fully integrable, grounded and floating, positive and negative capacitance multipliers, all designed starting from the well-known negative impedance converter (NIC) circuit, implemented through operational amplifiers (Op-Amp). The proposed topologies are very simple and employ a reduced number of active elements. Negative and positive capacitance behaviour can be simulated for a large frequency range depending on the active component performance in terms of DC gain and band-width. The sign can be regulated either by cascading two or more stages of the same simulator or introducing a further NIC circuit, replacing an appropriate resistor into the scheme. Theoretical formulations are addressed and compared with PSpice simulation results, showing their complete agreement. Since high values of capacitance can be easily obtained, the proposed circuit is suitable for low-frequency integrated low-pass active filter implementation where tunability is also easily allowed by varying only a resistance value.
{"title":"NIC-based capacitance multipliers for low-frequency integrated active filter applications","authors":"A. De Marcellis, G. Ferri, V. Stornelli","doi":"10.1109/RME.2007.4401853","DOIUrl":"https://doi.org/10.1109/RME.2007.4401853","url":null,"abstract":"In this paper we present fully integrable, grounded and floating, positive and negative capacitance multipliers, all designed starting from the well-known negative impedance converter (NIC) circuit, implemented through operational amplifiers (Op-Amp). The proposed topologies are very simple and employ a reduced number of active elements. Negative and positive capacitance behaviour can be simulated for a large frequency range depending on the active component performance in terms of DC gain and band-width. The sign can be regulated either by cascading two or more stages of the same simulator or introducing a further NIC circuit, replacing an appropriate resistor into the scheme. Theoretical formulations are addressed and compared with PSpice simulation results, showing their complete agreement. Since high values of capacitance can be easily obtained, the proposed circuit is suitable for low-frequency integrated low-pass active filter implementation where tunability is also easily allowed by varying only a resistance value.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130283250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401833
J. Wernehag, H. Sjöland
Two different frequency doubling power amplifier topologies have been compared, one with differential input and one with single-ended, both with single-ended output at 60 GHz. The frequency doubling capability is valuable from at least two perspectives, 1) the high frequency signal is on the chip as little as possible 2) the voltage controlled oscillator and power amplifier are at different frequencies easing the isolation of the two in a transceiver. The topologies have been simulated in a 1p8M 130-nm CMOS process. The resonant nodes are tuned with on-chip transmission lines. These have been simulated in ADS and compared to a standard Cadence component, tline3. The Cadence component gives a somewhat pessimistic estimation of the losses in the transmission line. The single ended input amplifier outputs a maximum of 3.7 dBm and draws 27 mA from a 1.2 V supply, while the one with differential input outputs 5.0 dBm and draws 28 mA. TTwo different frequency doubling power amplifier topologies have been compared, one with differential input and one with single-ended, both with single-ended output at 60 GHz. The frequency doubling capability is valuable from at least two perspectives, 1) the high frequency signal is on the chip as little as possible 2) the voltage controlled oscillator and power amplifier are at different frequencies easing the isolation of the two in a transceiver. The topologies have been simulated in a 1p8M 130-nm CMOS process. The resonant nodes are tuned with on-chip transmission lines. These have been simulated in ADS and compared to a standard Cadence component, tline3. The Cadence component gives a somewhat pessimistic estimation of the losses in the transmission line. The single ended input amplifier outputs a maximum of 3.7 dBm and draws 27 mA from a 1.2 V supply, while the one with differential input outputs 5.0 dBm and draws 28 mA. The 3-dB bandwidth of the amplifiers are 5.9 GHz and 6.8 GHz, respectively.he 3-dB bandwidth of the amplifiers are 5.9 GHz and 6.8 GHz, respectively.
{"title":"Second harmonic 60-GHz power amplifiers in 130-nm CMOS","authors":"J. Wernehag, H. Sjöland","doi":"10.1109/RME.2007.4401833","DOIUrl":"https://doi.org/10.1109/RME.2007.4401833","url":null,"abstract":"Two different frequency doubling power amplifier topologies have been compared, one with differential input and one with single-ended, both with single-ended output at 60 GHz. The frequency doubling capability is valuable from at least two perspectives, 1) the high frequency signal is on the chip as little as possible 2) the voltage controlled oscillator and power amplifier are at different frequencies easing the isolation of the two in a transceiver. The topologies have been simulated in a 1p8M 130-nm CMOS process. The resonant nodes are tuned with on-chip transmission lines. These have been simulated in ADS and compared to a standard Cadence component, tline3. The Cadence component gives a somewhat pessimistic estimation of the losses in the transmission line. The single ended input amplifier outputs a maximum of 3.7 dBm and draws 27 mA from a 1.2 V supply, while the one with differential input outputs 5.0 dBm and draws 28 mA. TTwo different frequency doubling power amplifier topologies have been compared, one with differential input and one with single-ended, both with single-ended output at 60 GHz. The frequency doubling capability is valuable from at least two perspectives, 1) the high frequency signal is on the chip as little as possible 2) the voltage controlled oscillator and power amplifier are at different frequencies easing the isolation of the two in a transceiver. The topologies have been simulated in a 1p8M 130-nm CMOS process. The resonant nodes are tuned with on-chip transmission lines. These have been simulated in ADS and compared to a standard Cadence component, tline3. The Cadence component gives a somewhat pessimistic estimation of the losses in the transmission line. The single ended input amplifier outputs a maximum of 3.7 dBm and draws 27 mA from a 1.2 V supply, while the one with differential input outputs 5.0 dBm and draws 28 mA. The 3-dB bandwidth of the amplifiers are 5.9 GHz and 6.8 GHz, respectively.he 3-dB bandwidth of the amplifiers are 5.9 GHz and 6.8 GHz, respectively.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130995359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401806
A. Fonte, D. Zito
An ultra-low noise amplifier (LNA) of a fully integrated microwave radiometer on silicon at 13 GHz for the civil and environmental safeguard is presented. The LNA represents the front-end stage of the radiometric sensor, which consists of an ultra-low noise receiver characterized by high performance in terms of sensitivity and gain stability. The LNA is realized by means of two cascode stages coupled each other by a transformer-based inter-stage matching network and provides differential outputs from single-ended input signal available from the antenna. The LNA exhibits a noise figure of 1.4 dB, a power gain of 20 dB and a power consumption of 12 mA with a supply voltage of 1 V, which represent one of the best set of performance among those presented in the literature.
{"title":"1-V 13-GHz ultra low noise amplifier for system-on-a-chip radiometer in CMOS 90 nm","authors":"A. Fonte, D. Zito","doi":"10.1109/RME.2007.4401806","DOIUrl":"https://doi.org/10.1109/RME.2007.4401806","url":null,"abstract":"An ultra-low noise amplifier (LNA) of a fully integrated microwave radiometer on silicon at 13 GHz for the civil and environmental safeguard is presented. The LNA represents the front-end stage of the radiometric sensor, which consists of an ultra-low noise receiver characterized by high performance in terms of sensitivity and gain stability. The LNA is realized by means of two cascode stages coupled each other by a transformer-based inter-stage matching network and provides differential outputs from single-ended input signal available from the antenna. The LNA exhibits a noise figure of 1.4 dB, a power gain of 20 dB and a power consumption of 12 mA with a supply voltage of 1 V, which represent one of the best set of performance among those presented in the literature.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131663918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401817
V. Stornelli, G. Ferri, A. De Marcellis
A CMOS low-voltage low-power switched OTA, optimized for its buffer configuration, suitable for both many portable applications and as input stage in digital architectures, is here presented. The circuit is a fully differential topology based on a symmetrical OTA featuring a rail-to-rail input and a reduced CMRR. It has been designed in a standard CMOS 0.35 mum technology and operates at 2V single supply voltage, showing a maximum power consumption of about 560 muW. Simulation results have confirmed the validity of the proposed architecture and have shown a -85dB THD for 100 kHz clock frequency, when a single tone input with lVpp amplitude at 10 kHz is applied.
{"title":"A fully-differential symmetrical OTA-based rail-to-rail switched buffer","authors":"V. Stornelli, G. Ferri, A. De Marcellis","doi":"10.1109/RME.2007.4401817","DOIUrl":"https://doi.org/10.1109/RME.2007.4401817","url":null,"abstract":"A CMOS low-voltage low-power switched OTA, optimized for its buffer configuration, suitable for both many portable applications and as input stage in digital architectures, is here presented. The circuit is a fully differential topology based on a symmetrical OTA featuring a rail-to-rail input and a reduced CMRR. It has been designed in a standard CMOS 0.35 mum technology and operates at 2V single supply voltage, showing a maximum power consumption of about 560 muW. Simulation results have confirmed the validity of the proposed architecture and have shown a -85dB THD for 100 kHz clock frequency, when a single tone input with lVpp amplitude at 10 kHz is applied.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130546934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401819
Julien Dalmasso, M. Flottes, B. Rouzeyre
During the production phase of microelectronics systems, one of the fundamental steps is to check if the system works fine. This step is called the test of integrated circuits. Furthermore, cost reduction of these tests has become a major axe of research in microelectronics. Several techniques allow reducing these costs, whether by reducing the test data volume (vertical compression) whether by reducing the need in Automatic Test Equipment to send the test data to the Circuit Under Test (horizontal compression). This is called Test Data Compression. But most of these techniques can only be applied to single cores. Yet actual systems-on-chip are now composed of numerous cores. This paper first presents a new horizontal compression method that is perfectly applicable in the multiple-cores systems framework. Then, two applications of this method to systems (1/bus-based and 2/Network-on-Chip-based systems) are presented. Compression allows here an increase in test parallelism and thus a decrease in test time of the whole system.
{"title":"Systems-on-chip: Use of test data compression technique for reducing test time","authors":"Julien Dalmasso, M. Flottes, B. Rouzeyre","doi":"10.1109/RME.2007.4401819","DOIUrl":"https://doi.org/10.1109/RME.2007.4401819","url":null,"abstract":"During the production phase of microelectronics systems, one of the fundamental steps is to check if the system works fine. This step is called the test of integrated circuits. Furthermore, cost reduction of these tests has become a major axe of research in microelectronics. Several techniques allow reducing these costs, whether by reducing the test data volume (vertical compression) whether by reducing the need in Automatic Test Equipment to send the test data to the Circuit Under Test (horizontal compression). This is called Test Data Compression. But most of these techniques can only be applied to single cores. Yet actual systems-on-chip are now composed of numerous cores. This paper first presents a new horizontal compression method that is perfectly applicable in the multiple-cores systems framework. Then, two applications of this method to systems (1/bus-based and 2/Network-on-Chip-based systems) are presented. Compression allows here an increase in test parallelism and thus a decrease in test time of the whole system.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126805151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401858
V. Maingot, R. Leveugle
When designing circuits for security-related applications, the robustness depends on its capability to globally resist to various types of attacks, based either on the observation of the device (e.g. differential power analysis) or its perturbation (e.g. injecting faults with a laser). To deal with perturbations, two strategies are developed: detecting the attack or maintaining the proper functioning of the device. This paper discusses characteristics of these two types of approaches when using information redundancy.
{"title":"On the use of error correcting and detecting codes in secured circuits","authors":"V. Maingot, R. Leveugle","doi":"10.1109/RME.2007.4401858","DOIUrl":"https://doi.org/10.1109/RME.2007.4401858","url":null,"abstract":"When designing circuits for security-related applications, the robustness depends on its capability to globally resist to various types of attacks, based either on the observation of the device (e.g. differential power analysis) or its perturbation (e.g. injecting faults with a laser). To deal with perturbations, two strategies are developed: detecting the attack or maintaining the proper functioning of the device. This paper discusses characteristics of these two types of approaches when using information redundancy.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"45 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114007337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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