Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313873
B. Saft, Eric Schaefer, Alexander Rolapp, E. Hennig
We present a novel ultra-low power capacitance extrema and modulation ratio detector for electrostatic micro vibration energy harvesters. The circuit signals the points in time where a varying harvester capacitance Cn(t) reaches its minimum and maximum values o min and o max in each oscillation period. A novel feature is that the circuit allows the capacitance modulation ratio ac = Cmax/Cmin between two consecutive extrema to be determined digitally. Using a self-clocked charge pumping scheme implemented with two low-power comparators and a pulse generator, our detector circuit keeps the voltage across a dedicated sense capacitor within a predefined margin around a fixed reference level. Transitions through capacitance extrema are indicated by polarity reversals of the charge packets. The number of charge packets transferred between two polarity reversals is nonlinearly but uniquely related to ac. The proposed circuit was implemented and fabricated in a commercial 0.35-/xm CMOS process. Measurements were performed using a rotating capacitor with Cmax = 150 pF and adjustable ac spinning with up to 110 Hz. Transitions through capacitance extrema were measured for ac = 1.3 ... 4.4 and were signalled accurately within the systematic time resolution limits of the method. In the presented configuration, the circuit draws a current of 60 nA from a 3.8-V supply.
{"title":"An ultra-low power capacitance extrema and ratio detector for electrostatic energy harvesters","authors":"B. Saft, Eric Schaefer, Alexander Rolapp, E. Hennig","doi":"10.1109/ESSCIRC.2015.7313873","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313873","url":null,"abstract":"We present a novel ultra-low power capacitance extrema and modulation ratio detector for electrostatic micro vibration energy harvesters. The circuit signals the points in time where a varying harvester capacitance Cn(t) reaches its minimum and maximum values o min and o max in each oscillation period. A novel feature is that the circuit allows the capacitance modulation ratio ac = Cmax/Cmin between two consecutive extrema to be determined digitally. Using a self-clocked charge pumping scheme implemented with two low-power comparators and a pulse generator, our detector circuit keeps the voltage across a dedicated sense capacitor within a predefined margin around a fixed reference level. Transitions through capacitance extrema are indicated by polarity reversals of the charge packets. The number of charge packets transferred between two polarity reversals is nonlinearly but uniquely related to ac. The proposed circuit was implemented and fabricated in a commercial 0.35-/xm CMOS process. Measurements were performed using a rotating capacitor with Cmax = 150 pF and adjustable ac spinning with up to 110 Hz. Transitions through capacitance extrema were measured for ac = 1.3 ... 4.4 and were signalled accurately within the systematic time resolution limits of the method. In the presented configuration, the circuit draws a current of 60 nA from a 3.8-V supply.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89223402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313865
Chongjun Ding, Y. Manoli, M. Keller
A third-order continuous-time Delta-Sigma modulator in a 130 nm CMOS technology is presented. It features a 3-bit quantizer with an intrinsic excess loop delay compensation for half a clock cycle. The compensation is performed by means of adapting the reference voltages of the comparators on a sampling-to-sampling base, thus overcoming a power consuming summation of signals in front of the quantizer. Occupying merely 0.086mm2, the modulator achieves 66.4 dB SNDR and 74.6 dB DR in a 20 MHz bandwidth using a 640 MHz clock frequency. The power consumption equals 5.1 mW drawn from a 1.2 V supply voltage, which yields a state-of-the-art Walden figure of merit FOMW of 74.7 fJ/conv-step.
提出了一种基于130纳米CMOS技术的三阶连续时间Delta-Sigma调制器。它具有一个3位量化器，具有半个时钟周期的内在超额环路延迟补偿。补偿是通过在采样到采样的基础上调整比较器的参考电压来实现的，从而克服了量化器前面信号的功耗求和。该调制器仅占用0.086mm2，在20mhz带宽下使用640 MHz时钟频率实现66.4 dB SNDR和74.6 dB DR。在1.2 V电源电压下，功耗为5.1 mW，这就产生了最先进的瓦尔登优点曲线，即74.7 fJ/逆变步长。
{"title":"A 5.1mW 74dB DR CT ΔΣ modulator with quantizer intrinsic ELD compensation achieving 75fJ/conv.-step in a 20MHz BW","authors":"Chongjun Ding, Y. Manoli, M. Keller","doi":"10.1109/ESSCIRC.2015.7313865","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313865","url":null,"abstract":"A third-order continuous-time Delta-Sigma modulator in a 130 nm CMOS technology is presented. It features a 3-bit quantizer with an intrinsic excess loop delay compensation for half a clock cycle. The compensation is performed by means of adapting the reference voltages of the comparators on a sampling-to-sampling base, thus overcoming a power consuming summation of signals in front of the quantizer. Occupying merely 0.086mm2, the modulator achieves 66.4 dB SNDR and 74.6 dB DR in a 20 MHz bandwidth using a 640 MHz clock frequency. The power consumption equals 5.1 mW drawn from a 1.2 V supply voltage, which yields a state-of-the-art Walden figure of merit FOMW of 74.7 fJ/conv-step.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90599234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313903
S. Jahromi, Jussi-Pekka Jansson, I. Nissinen, J. Nissinen, J. Kostamovaara
A single chip receiver for pulsed laser time-of-flight rangefinding applications has been realized in a standard 0.35um HV CMOS technology. It includes a 9×9 SPAD array and a 10-channel time-to-digital converter with 10ps single shot precision. Any of the 3×3 sub-arrays can be selected for simultaneous measurement. The selected SPAD array can be gated to be operative only within a selected time window in order to suppress dark and background light induced counts. Functional tests in a laser radar environment indicate full functionality over a range of nearly 80 metres.
{"title":"A single chip laser radar receiver with a 9×9 SPAD detector array and a 10-channel TDC","authors":"S. Jahromi, Jussi-Pekka Jansson, I. Nissinen, J. Nissinen, J. Kostamovaara","doi":"10.1109/ESSCIRC.2015.7313903","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313903","url":null,"abstract":"A single chip receiver for pulsed laser time-of-flight rangefinding applications has been realized in a standard 0.35um HV CMOS technology. It includes a 9×9 SPAD array and a 10-channel time-to-digital converter with 10ps single shot precision. Any of the 3×3 sub-arrays can be selected for simultaneous measurement. The selected SPAD array can be gated to be operative only within a selected time window in order to suppress dark and background light induced counts. Functional tests in a laser radar environment indicate full functionality over a range of nearly 80 metres.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86967692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313882
Peng Chen, Xiongchuan Huang, Yao-Hong Liu, M. Ding, Cui Zhou, A. Ba, K. Philips, H. D. Groot, R. Staszewski
The newly proposed phase-prediction counter-based ADPLL has achieved a wireless standard-compliant performance at ultra-low power consumption. The digital-to-time converter (DTC) is the key enabler but is nonlinearity can easily create fractional spurs. This paper analyzes the effect of the DTC nonlinearity on in-band fractional spurs and proposes a method to characterize it in a built-in fashion by means of a fine-resolution ΔΣ TDC that forms an outer loop with the DTC. The TDC is realized in 40nm CMOS and exhibits only 1.8ps rms of random jitter.
{"title":"Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs","authors":"Peng Chen, Xiongchuan Huang, Yao-Hong Liu, M. Ding, Cui Zhou, A. Ba, K. Philips, H. D. Groot, R. Staszewski","doi":"10.1109/ESSCIRC.2015.7313882","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313882","url":null,"abstract":"The newly proposed phase-prediction counter-based ADPLL has achieved a wireless standard-compliant performance at ultra-low power consumption. The digital-to-time converter (DTC) is the key enabler but is nonlinearity can easily create fractional spurs. This paper analyzes the effect of the DTC nonlinearity on in-band fractional spurs and proposes a method to characterize it in a built-in fashion by means of a fine-resolution ΔΣ TDC that forms an outer loop with the DTC. The TDC is realized in 40nm CMOS and exhibits only 1.8ps rms of random jitter.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91381180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313883
M. Kuhl, Y. Manoli
This work presents an area-efficient fully-differential 2-stage amplifier as analog pre-amplifier for active neural recording probes. It features an architecture-switching-scheme to reduce the overhead of unused feedback elements in variable-bandwidth-systems, as well as a double-differential self-defining common mode feedback to minimize the biasing overhead. Its area including all feedback elements measures 9,977 μm2, which is more than 2x smaller than previously published neural readout bandpass LNAs. It offers a switchable lower (1 or 140 Hz) and tunable upper (0.24-49 kHz) cut-off frequency with a gain of 26-32 dB and an input noise down to 11.9 μVrms. The LNA consumes 0.1-8.2 μA at 1.8 V and was implemented in a 0.18 μm CMOS technology.
{"title":"A 0.01 mm2 fully-differential 2-stage amplifier with reference-free CMFB using an architecture-switching-scheme for bandwidth variation","authors":"M. Kuhl, Y. Manoli","doi":"10.1109/ESSCIRC.2015.7313883","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313883","url":null,"abstract":"This work presents an area-efficient fully-differential 2-stage amplifier as analog pre-amplifier for active neural recording probes. It features an architecture-switching-scheme to reduce the overhead of unused feedback elements in variable-bandwidth-systems, as well as a double-differential self-defining common mode feedback to minimize the biasing overhead. Its area including all feedback elements measures 9,977 μm2, which is more than 2x smaller than previously published neural readout bandpass LNAs. It offers a switchable lower (1 or 140 Hz) and tunable upper (0.24-49 kHz) cut-off frequency with a gain of 26-32 dB and an input noise down to 11.9 μVrms. The LNA consumes 0.1-8.2 μA at 1.8 V and was implemented in a 0.18 μm CMOS technology.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73509807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313914
S. Nessler, M. Marx, M. Maurer, S. Rombach, Y. Manoli
A front-end circuit for closed loop continuous-time delta-sigma (CT ΔΣ) micro-electro-mechanical gyroscope readout circuits is implemented. This work presents for the first time a CT collocated feedback, which simultaneously uses the detection capacitors of the sensor for the signal readout and the feedback. This is realized by the modulation of the input common mode of the readout amplifier and relies solely on CT techniques to achieve a low noise floor. Additionally, the concept decreases the number and the complexity of the signals in the high voltage (HV) domain. Therefore, the power and area demands of the developed HV interface for quadrature compensation and mode matching are reduced. The circuit is implemented in a 0.35 μm technology, requires an area of 0.65 mm2 and consumes 770 μW.
{"title":"A Continuous-Time Collocated Force-Feedback and Readout Front-End for MEM Gyroscopes","authors":"S. Nessler, M. Marx, M. Maurer, S. Rombach, Y. Manoli","doi":"10.1109/ESSCIRC.2015.7313914","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313914","url":null,"abstract":"A front-end circuit for closed loop continuous-time delta-sigma (CT ΔΣ) micro-electro-mechanical gyroscope readout circuits is implemented. This work presents for the first time a CT collocated feedback, which simultaneously uses the detection capacitors of the sensor for the signal readout and the feedback. This is realized by the modulation of the input common mode of the readout amplifier and relies solely on CT techniques to achieve a low noise floor. Additionally, the concept decreases the number and the complexity of the signals in the high voltage (HV) domain. Therefore, the power and area demands of the developed HV interface for quadrature compensation and mode matching are reduced. The circuit is implemented in a 0.35 μm technology, requires an area of 0.65 mm2 and consumes 770 μW.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74317500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313904
P. Ciccarella, M. Carminati, G. Ferrari, F. Morichetti, M. Sampietro
In order to address the challenges posed by the growing complexity of silicon photonic chips integrating more and more photonics devices, which require tuning and reconfiguration, a 32-channel 0.35 μm CMOS ASIC for a recently developed in-line non-invasive light power monitor has been designed. By combining a low-noise front-end with a carefully optimized low-parasitic multiplexer and with two square-wave multipliers (real and imaginary components) the waveguide admittance (affected by the local light power) can be measured on chip over a 100 MHz bandwidth with 10 pS resolution in four simultaneous channels, suitable for closed-loop stabilization of photonic devices such as microring resonators. The results of the chip experimental characterization here reported demonstrate dramatic miniaturization, a 20-fold improvement in resolution and a 10-fold bandwidth extension with respect to a state-of-the-art bench-top instrumentation.
{"title":"32-Channel low-noise lock-in ASIC for non-invasive light detection in silicon photonics","authors":"P. Ciccarella, M. Carminati, G. Ferrari, F. Morichetti, M. Sampietro","doi":"10.1109/ESSCIRC.2015.7313904","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313904","url":null,"abstract":"In order to address the challenges posed by the growing complexity of silicon photonic chips integrating more and more photonics devices, which require tuning and reconfiguration, a 32-channel 0.35 μm CMOS ASIC for a recently developed in-line non-invasive light power monitor has been designed. By combining a low-noise front-end with a carefully optimized low-parasitic multiplexer and with two square-wave multipliers (real and imaginary components) the waveguide admittance (affected by the local light power) can be measured on chip over a 100 MHz bandwidth with 10 pS resolution in four simultaneous channels, suitable for closed-loop stabilization of photonic devices such as microring resonators. The results of the chip experimental characterization here reported demonstrate dramatic miniaturization, a 20-fold improvement in resolution and a 10-fold bandwidth extension with respect to a state-of-the-art bench-top instrumentation.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83133223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313848
Philipp Greiner, J. Grosinger, C. Steffan, G. Holweg, W. Bösch
A fully integrated all CMOS oscillator frequency reference is presented that is suitable for crystal replacement in relaxed requirement applications. The frequency reference constitutes a new approach of CMOS frequency control based on a reference-less non-trimmable LC oscillator (LCO) with a resonance frequency of approximately 3.15 GHz and a low jitter fractional divider. The fractional frequency divider consists of an integer divider and a programmable delay and thus provides a wide range of possible output frequencies from 1 to 180 MHz. A complex control logic comprising a nonvolatile memory (NVM) performs the calibration, frequency setup, and temperature compensation of the device. A planar magnetic decoupling structure is used to reduce the sensitivity of the LCO to its environment. This implementation allows the assembly of the LCO chip in a standard plastic package without using a Faraday shield. The device achieves an initial frequency stability of ±50 ppm over a temperature region of -20 to 85°C. The presented architecture overall dissipates 6.5mA from a 1.8-3.6V power supply (buffer neglected) and is competitive to already existing integer divider based LCO frequency reference realisations.
{"title":"Non-trimmable LC oscillator for all CMOS frequency control","authors":"Philipp Greiner, J. Grosinger, C. Steffan, G. Holweg, W. Bösch","doi":"10.1109/ESSCIRC.2015.7313848","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313848","url":null,"abstract":"A fully integrated all CMOS oscillator frequency reference is presented that is suitable for crystal replacement in relaxed requirement applications. The frequency reference constitutes a new approach of CMOS frequency control based on a reference-less non-trimmable LC oscillator (LCO) with a resonance frequency of approximately 3.15 GHz and a low jitter fractional divider. The fractional frequency divider consists of an integer divider and a programmable delay and thus provides a wide range of possible output frequencies from 1 to 180 MHz. A complex control logic comprising a nonvolatile memory (NVM) performs the calibration, frequency setup, and temperature compensation of the device. A planar magnetic decoupling structure is used to reduce the sensitivity of the LCO to its environment. This implementation allows the assembly of the LCO chip in a standard plastic package without using a Faraday shield. The device achieves an initial frequency stability of ±50 ppm over a temperature region of -20 to 85°C. The presented architecture overall dissipates 6.5mA from a 1.8-3.6V power supply (buffer neglected) and is competitive to already existing integer divider based LCO frequency reference realisations.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82465524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313891
Sameer Singh, M. Govindarajan, T. Venkatesh, W. Evans, A. Kansal, S. S. Murali
This paper describes the techniques used in the design of a 12-bit 290MS/s two stage time interleaved (TI) SAR ADC that minimizes the sampling skew and gain mismatches between multiple high resolution cores without the need for background digital calibration. A timing scheme which allows sharing of a single reference buffer and optimal distribution of conversion time among MSB and LSB bits is used. Further optimization in power is achieved by use of a process, voltage and temperature (PVT) invariant asynchronous timing loop that avoids pessimistic margins and simplifies design. The ADC is implemented in TSMC 28HPM process and achieves high input frequency figure of merit (FoM) of 23fJ/conv-step. Its high frequency Schreier FoM is 165.3dB, which is the highest reported number at this sampling range. The architecture is extended towards implementation of a 12-bit 460MS/s ADC, where two such instances are interleaved to achieve FoM of 30fJ/conv-step and greater than 70dB SFDR.
本文介绍了一种12位290MS/s两级时间交错(TI) SAR ADC的设计技术，该ADC在不需要背景数字校准的情况下，最大限度地减少了多个高分辨率核心之间的采样倾斜和增益不匹配。使用了一种允许共享单个参考缓冲区和在MSB和LSB位之间最佳分配转换时间的定时方案。通过使用过程、电压和温度(PVT)不变异步定时环路，进一步优化功率，避免了悲观余量并简化了设计。该ADC在台积电28HPM工艺中实现，实现了23fJ/反步的高输入频率优值(FoM)。其高频Schreier FoM为165.3dB，是该采样范围内报道的最高数值。该架构扩展为实现12位460MS/s的ADC，其中两个这样的实例交错以实现30fJ/反步的FoM和大于70dB的SFDR。
{"title":"A 23fJ/conv-step 12b 290MS/s time interleaved pipelined SAR ADC","authors":"Sameer Singh, M. Govindarajan, T. Venkatesh, W. Evans, A. Kansal, S. S. Murali","doi":"10.1109/ESSCIRC.2015.7313891","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313891","url":null,"abstract":"This paper describes the techniques used in the design of a 12-bit 290MS/s two stage time interleaved (TI) SAR ADC that minimizes the sampling skew and gain mismatches between multiple high resolution cores without the need for background digital calibration. A timing scheme which allows sharing of a single reference buffer and optimal distribution of conversion time among MSB and LSB bits is used. Further optimization in power is achieved by use of a process, voltage and temperature (PVT) invariant asynchronous timing loop that avoids pessimistic margins and simplifies design. The ADC is implemented in TSMC 28HPM process and achieves high input frequency figure of merit (FoM) of 23fJ/conv-step. Its high frequency Schreier FoM is 165.3dB, which is the highest reported number at this sampling range. The architecture is extended towards implementation of a 12-bit 460MS/s ADC, where two such instances are interleaved to achieve FoM of 30fJ/conv-step and greater than 70dB SFDR.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82470120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313832
T. Siriburanon, Hanli Liu, K. Nakata, W. Deng, J. Son, D. Lee, K. Okada, A. Matsuzawa
This paper presents a 27.5-29.6GHz fractional-N frequency synthesizer using reference and frequency doublers to achieve low in-band and out-of-band phase-noise for 5G mobile communications. The push-push amplifier and 28GHz balun help achieving differential signals with low out-of-band phase noise while consuming low power. A charge pump with gated offset as well as reference doubler help reducing noise-folding effect resulting low in-band phase noise while sampling loop filter helps reducing spurs. The proposed synthesizer has been implemented in 65nm CMOS technology achieving an in-band and out-of-band phase noise of -78dBc/Hz and -126dBc/Hz, respectively while consuming only 33mW. The jitter-power figure-of-merit (FoM) is -231dB which is the highest among the state-of-the-art >20GHz fractional-N PLLs. Reference spurs are less than -80 dBc.
{"title":"A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular","authors":"T. Siriburanon, Hanli Liu, K. Nakata, W. Deng, J. Son, D. Lee, K. Okada, A. Matsuzawa","doi":"10.1109/ESSCIRC.2015.7313832","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313832","url":null,"abstract":"This paper presents a 27.5-29.6GHz fractional-N frequency synthesizer using reference and frequency doublers to achieve low in-band and out-of-band phase-noise for 5G mobile communications. The push-push amplifier and 28GHz balun help achieving differential signals with low out-of-band phase noise while consuming low power. A charge pump with gated offset as well as reference doubler help reducing noise-folding effect resulting low in-band phase noise while sampling loop filter helps reducing spurs. The proposed synthesizer has been implemented in 65nm CMOS technology achieving an in-band and out-of-band phase noise of -78dBc/Hz and -126dBc/Hz, respectively while consuming only 33mW. The jitter-power figure-of-merit (FoM) is -231dB which is the highest among the state-of-the-art >20GHz fractional-N PLLs. Reference spurs are less than -80 dBc.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79891159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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