Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616955
C. Shahnaz, W. Zhu, M. Ahmad
A new method based on temporal matching is presented in this paper for pitch determination from noisy speech signals. At first, a variable-length average magnitude sum function (VLAMSF) that exhibits a periodicity similar to the pitch period of the voiced speech, has been proposed. We argue that the discrete cosine transform (DCT) power spectrum of the VLAMSF is capable of revealing an estimate of a pitch-harmonic (PH) more accurately even in a heavy noisy scenario. Then, exploiting the extracted PH, we formulate an impulse train with a variable-period that is used to temporally match the periodicity of the proposed VLAMSF for pitch determination. It has been shown through extensive simulations using the Keele database that our new approach consistently outperforms the other existing methods especially at low signal-to-noise ratios (SNRs).
{"title":"A temporal matching method for pitch determination from noisy speech signals","authors":"C. Shahnaz, W. Zhu, M. Ahmad","doi":"10.1109/MWSCAS.2008.4616955","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616955","url":null,"abstract":"A new method based on temporal matching is presented in this paper for pitch determination from noisy speech signals. At first, a variable-length average magnitude sum function (VLAMSF) that exhibits a periodicity similar to the pitch period of the voiced speech, has been proposed. We argue that the discrete cosine transform (DCT) power spectrum of the VLAMSF is capable of revealing an estimate of a pitch-harmonic (PH) more accurately even in a heavy noisy scenario. Then, exploiting the extracted PH, we formulate an impulse train with a variable-period that is used to temporally match the periodicity of the proposed VLAMSF for pitch determination. It has been shown through extensive simulations using the Keele database that our new approach consistently outperforms the other existing methods especially at low signal-to-noise ratios (SNRs).","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121167217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616772
P. Pranav, B. Giraud, A. Amara
Double-gate fully-depleted (DGFD) SOI circuits are regarded as the next generation ULSI circuits. In this paper we propose a high performance voltage sense amplifier in sub 32-nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed design improves the sensing delay and shows excellent tolerance to threshold voltage mismatch (9%) and L mismatch (9%) even at a voltage as low as 0.6 V. The proposed architecture is compared to two other architectures directly converted to DGSOI Technology and proves to be 50-60% faster and more (300-400%) insensitive to mismatch. The reliability and process variation insensitivity is also analyzed through Monte Carlo analysis.
{"title":"An innovative ultra low voltage sub-32nm SRAM voltage sense amplifier in DG-SOI technology","authors":"P. Pranav, B. Giraud, A. Amara","doi":"10.1109/MWSCAS.2008.4616772","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616772","url":null,"abstract":"Double-gate fully-depleted (DGFD) SOI circuits are regarded as the next generation ULSI circuits. In this paper we propose a high performance voltage sense amplifier in sub 32-nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed design improves the sensing delay and shows excellent tolerance to threshold voltage mismatch (9%) and L mismatch (9%) even at a voltage as low as 0.6 V. The proposed architecture is compared to two other architectures directly converted to DGSOI Technology and proves to be 50-60% faster and more (300-400%) insensitive to mismatch. The reliability and process variation insensitivity is also analyzed through Monte Carlo analysis.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121262149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616848
J. Dobes
Many software tools of the PSpice class do not contain an implementation of the steady-state algorithm, especially for autonomous circuits. In the paper, an add-on is described to the algorithm for implicit numerical integration which determines the steady state of both nonautonomous and autonomous circuits by an extrapolation method. The extrapolation procedure is based on scalar epsilon-algorithm which is relatively easy for programing and efficient in terms of number of required iterations. Since the selected algorithm for the implicit numerical integration gives values of derivatives at any time, the determination of unknown periods of autonomous circuits can be performed by modified Newton-Raphson method. The efficiency of the procedure is demonstrated by the steady-state analysis of a tunable distributed microwave oscillator with the results compared with measured data.
{"title":"A steady-state add-on to the algorithm for implicit numerical integration","authors":"J. Dobes","doi":"10.1109/MWSCAS.2008.4616848","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616848","url":null,"abstract":"Many software tools of the PSpice class do not contain an implementation of the steady-state algorithm, especially for autonomous circuits. In the paper, an add-on is described to the algorithm for implicit numerical integration which determines the steady state of both nonautonomous and autonomous circuits by an extrapolation method. The extrapolation procedure is based on scalar epsilon-algorithm which is relatively easy for programing and efficient in terms of number of required iterations. Since the selected algorithm for the implicit numerical integration gives values of derivatives at any time, the determination of unknown periods of autonomous circuits can be performed by modified Newton-Raphson method. The efficiency of the procedure is demonstrated by the steady-state analysis of a tunable distributed microwave oscillator with the results compared with measured data.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128937538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616889
S. Rahaman, M. Chowdhury
As technology scales, inductive crosstalk becomes prominent along with capacitive crosstalk, and it is creating a significant bottleneck in high-speed deep sub-micron and nanoscale integrated circuits. For inductive coupling, worst-case delay occurs when all the bus lines simultaneously switch in the same direction. This switching case is the best case switching pattern for capacitive-dominant on-chip buses. Therefore, various existing coding techniques for capacitive crosstalk reduction are not suitable for high-speed circuits, where electromagnetic effect can not be ignored. In this paper, various hybrid bus-invert (BI) coding methods have been proposed for RLC coupling-aware on-chip buses. Simulation results show that simultaneous switching noise (SSN) for inductance-dominant buses can be reduced by roughly 40% and, thereby, worst case coupling delay is also reduced. Besides, a joint coding approach is proposed for simultaneous reduction of SSN and higher reliability to errors due to deep-submicron (DSM) noise.
{"title":"Joint coding for RLC coupling-aware on-chip buses","authors":"S. Rahaman, M. Chowdhury","doi":"10.1109/MWSCAS.2008.4616889","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616889","url":null,"abstract":"As technology scales, inductive crosstalk becomes prominent along with capacitive crosstalk, and it is creating a significant bottleneck in high-speed deep sub-micron and nanoscale integrated circuits. For inductive coupling, worst-case delay occurs when all the bus lines simultaneously switch in the same direction. This switching case is the best case switching pattern for capacitive-dominant on-chip buses. Therefore, various existing coding techniques for capacitive crosstalk reduction are not suitable for high-speed circuits, where electromagnetic effect can not be ignored. In this paper, various hybrid bus-invert (BI) coding methods have been proposed for RLC coupling-aware on-chip buses. Simulation results show that simultaneous switching noise (SSN) for inductance-dominant buses can be reduced by roughly 40% and, thereby, worst case coupling delay is also reduced. Besides, a joint coding approach is proposed for simultaneous reduction of SSN and higher reliability to errors due to deep-submicron (DSM) noise.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127497161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616924
S. Mahmoud
A novel current-mode CMOS digitally controlled variable gain amplifier (VGA) is presented in this paper. The proposed VGA is based on new plusmn0.75 V digitally programmable second-generation current conveyors (DPCCII) with digital current gain control. The input stage of the DPCCII is realized using two complementary MOS differential pairs connected in parallel to ensure rail-to-rail operation. The output stage consists of a class-AB push-pull circuit, which guarantees high current driving capability. The digital control of the DPCCII, based on transistor arrays and MOS switches, provides variable current gain using an n-bits code-word. All proposed circuits are simulated using PSPICE with CMOS TSMC 0.25 mum technology.
{"title":"Low voltage current-mode digitally controlled VGA based on digitally programmble current conveyors","authors":"S. Mahmoud","doi":"10.1109/MWSCAS.2008.4616924","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616924","url":null,"abstract":"A novel current-mode CMOS digitally controlled variable gain amplifier (VGA) is presented in this paper. The proposed VGA is based on new plusmn0.75 V digitally programmable second-generation current conveyors (DPCCII) with digital current gain control. The input stage of the DPCCII is realized using two complementary MOS differential pairs connected in parallel to ensure rail-to-rail operation. The output stage consists of a class-AB push-pull circuit, which guarantees high current driving capability. The digital control of the DPCCII, based on transistor arrays and MOS switches, provides variable current gain using an n-bits code-word. All proposed circuits are simulated using PSPICE with CMOS TSMC 0.25 mum technology.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129167018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616741
B. Taskin, Jianchao Lu
In mainstream ASIC design, industry standard automation tools are used in generating circuit implementations that satisfy the timing and power budgets. A typical timing budget follows the specifications of a clock frequency governed by the longest data path in the circuit. To satisfy this constraint, a zero-skew clock network that minimizes or bounds the clock skew is synthesized. Due to variations, however, zero clock skew cannot always be maintained and timing violations occur. This paper describes a post-clock-tree synthesis (CTS) delay insertion process on the clock tree network in order to fix timing violations that occur after such automated design tools are used. A mathematical formulation is presented which computes the minimum amount of delay to be inserted on each branch of the clock network. Experimental results show that the clock networks of the largest ISCASpsila89 circuits can be corrected post-CTS to resolve the timing conflicts in approximately 90% of the circuits with minimal delay insertion (0.159timesclock period per clock path on average).
{"title":"Post-CTS delay insertion to fix timing violations","authors":"B. Taskin, Jianchao Lu","doi":"10.1109/MWSCAS.2008.4616741","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616741","url":null,"abstract":"In mainstream ASIC design, industry standard automation tools are used in generating circuit implementations that satisfy the timing and power budgets. A typical timing budget follows the specifications of a clock frequency governed by the longest data path in the circuit. To satisfy this constraint, a zero-skew clock network that minimizes or bounds the clock skew is synthesized. Due to variations, however, zero clock skew cannot always be maintained and timing violations occur. This paper describes a post-clock-tree synthesis (CTS) delay insertion process on the clock tree network in order to fix timing violations that occur after such automated design tools are used. A mathematical formulation is presented which computes the minimum amount of delay to be inserted on each branch of the clock network. Experimental results show that the clock networks of the largest ISCASpsila89 circuits can be corrected post-CTS to resolve the timing conflicts in approximately 90% of the circuits with minimal delay insertion (0.159timesclock period per clock path on average).","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134011226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616931
Yu Song, E. Moule, Z. Ignjatovic
In this paper, we propose an adaptable-order single-loop digital DeltaSigma modulator which offers flexible noise shaping performance to maximize hardware sharing and power efficiency in multi-band frequency synthesizer applications. The proposed architecture utilizes feedback coefficients that allow computationally efficient digital implementation and also yield good noise shaping. Fixed-magnitude quantizer dithering is employed to eliminate idle channel tones and also to suppress in-band noise more efficiently than input dithering structures. MATLAB simulation was carried out. Finally, the proposed architecture was implemented and verified in an FPGA device.
{"title":"Adaptable digital delta-sigma modulator for multiband frequency synthesizer","authors":"Yu Song, E. Moule, Z. Ignjatovic","doi":"10.1109/MWSCAS.2008.4616931","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616931","url":null,"abstract":"In this paper, we propose an adaptable-order single-loop digital DeltaSigma modulator which offers flexible noise shaping performance to maximize hardware sharing and power efficiency in multi-band frequency synthesizer applications. The proposed architecture utilizes feedback coefficients that allow computationally efficient digital implementation and also yield good noise shaping. Fixed-magnitude quantizer dithering is employed to eliminate idle channel tones and also to suppress in-band noise more efficiently than input dithering structures. MATLAB simulation was carried out. Finally, the proposed architecture was implemented and verified in an FPGA device.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130450462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616824
H. Cao, R. Weber
We present a method for characterizing three-port (RF, IF, image) conversion scattering parameters for microwave mixers. A diplexer is used to separate the image signal from the IF signal. The de-embedding and un-terminating methods have been used for calculating the scattering-parameter matrix. The conversion scattering parameters have been obtained at different local-oscillator (LO) power levels for a commercial microwave mixer. We also show how the termination of the image signal will affect the conversion loss of the microwave mixer.
{"title":"Three-port conversion scattering parameters characterization for microwave mixers","authors":"H. Cao, R. Weber","doi":"10.1109/MWSCAS.2008.4616824","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616824","url":null,"abstract":"We present a method for characterizing three-port (RF, IF, image) conversion scattering parameters for microwave mixers. A diplexer is used to separate the image signal from the IF signal. The de-embedding and un-terminating methods have been used for calculating the scattering-parameter matrix. The conversion scattering parameters have been obtained at different local-oscillator (LO) power levels for a commercial microwave mixer. We also show how the termination of the image signal will affect the conversion loss of the microwave mixer.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131913440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616800
K. Lin, Yen Hung Lin
Modular multiplication is a very important arithmetic operation in cryptography systems and residue-based computation. This paper presents a synchronous modular multiplier that has variable computation latency depending on operand values. The modular reduction operation is based on SRT radix-2 division. However, the quotient selection function in certain stages is adapted for reducing delay and area. The proposed variable latency design was synthesized and verified with TSMC 0.18 mum technology. It can achieve significant computation time reduction compared to a fixed-latency design, while needing only 4 % larger area.
{"title":"A synchronous modular multiplier with variable latency","authors":"K. Lin, Yen Hung Lin","doi":"10.1109/MWSCAS.2008.4616800","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616800","url":null,"abstract":"Modular multiplication is a very important arithmetic operation in cryptography systems and residue-based computation. This paper presents a synchronous modular multiplier that has variable computation latency depending on operand values. The modular reduction operation is based on SRT radix-2 division. However, the quotient selection function in certain stages is adapted for reducing delay and area. The proposed variable latency design was synthesized and verified with TSMC 0.18 mum technology. It can achieve significant computation time reduction compared to a fixed-latency design, while needing only 4 % larger area.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134263540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616875
B. Degnan, P. Hasler, C. Twigg
Floating-gate transistors that have contacts to the lowest metal to the polysilicon floating-gate were fabricated to determine if the lowest metal flow alone could normalize charge across multiple floating gates. The metal contacts did not normalize charge for different numbers of contacts to polysilicon; however, a decreased variance of trapped charge was found when compared to polysilicon floating-gates that have no contacts to lowestmetal. The charge leakage from the floating-gate was negligible after one year, suggesting that layout may play a critical factor in leakage.
{"title":"Trapped charge characterization and removal on floating-gate transistors","authors":"B. Degnan, P. Hasler, C. Twigg","doi":"10.1109/MWSCAS.2008.4616875","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616875","url":null,"abstract":"Floating-gate transistors that have contacts to the lowest metal to the polysilicon floating-gate were fabricated to determine if the lowest metal flow alone could normalize charge across multiple floating gates. The metal contacts did not normalize charge for different numbers of contacts to polysilicon; however, a decreased variance of trapped charge was found when compared to polysilicon floating-gates that have no contacts to lowestmetal. The charge leakage from the floating-gate was negligible after one year, suggesting that layout may play a critical factor in leakage.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133224041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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