Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616794
S. Trendelenburg, D. De Dorigo, F. Henrici, J. Becker, Y. Manoli
This work presents techniques for mapping various Gm-C filter topologies on a specialized field-programmable analog array (FPAA) for continuous-time filters. Through its unique hexagonal architecture, it is possible to map most well-known Gm-C filter topologies to the array, including cascaded biquads, simulated LC-ladders, as well as integrator feedback and feed-forward structures. Through tuning of the digitally programmable filter elements, the properties of the resulting filters, such as bandwidth, filter type or cutoff frequencies can be varied after the filter topology has been instantiated.
{"title":"Instantiation of higher order filters on a continuous-time field-programmable analog array","authors":"S. Trendelenburg, D. De Dorigo, F. Henrici, J. Becker, Y. Manoli","doi":"10.1109/MWSCAS.2008.4616794","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616794","url":null,"abstract":"This work presents techniques for mapping various Gm-C filter topologies on a specialized field-programmable analog array (FPAA) for continuous-time filters. Through its unique hexagonal architecture, it is possible to map most well-known Gm-C filter topologies to the array, including cascaded biquads, simulated LC-ladders, as well as integrator feedback and feed-forward structures. Through tuning of the digitally programmable filter elements, the properties of the resulting filters, such as bandwidth, filter type or cutoff frequencies can be varied after the filter topology has been instantiated.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125040764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616772
P. Pranav, B. Giraud, A. Amara
Double-gate fully-depleted (DGFD) SOI circuits are regarded as the next generation ULSI circuits. In this paper we propose a high performance voltage sense amplifier in sub 32-nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed design improves the sensing delay and shows excellent tolerance to threshold voltage mismatch (9%) and L mismatch (9%) even at a voltage as low as 0.6 V. The proposed architecture is compared to two other architectures directly converted to DGSOI Technology and proves to be 50-60% faster and more (300-400%) insensitive to mismatch. The reliability and process variation insensitivity is also analyzed through Monte Carlo analysis.
{"title":"An innovative ultra low voltage sub-32nm SRAM voltage sense amplifier in DG-SOI technology","authors":"P. Pranav, B. Giraud, A. Amara","doi":"10.1109/MWSCAS.2008.4616772","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616772","url":null,"abstract":"Double-gate fully-depleted (DGFD) SOI circuits are regarded as the next generation ULSI circuits. In this paper we propose a high performance voltage sense amplifier in sub 32-nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed design improves the sensing delay and shows excellent tolerance to threshold voltage mismatch (9%) and L mismatch (9%) even at a voltage as low as 0.6 V. The proposed architecture is compared to two other architectures directly converted to DGSOI Technology and proves to be 50-60% faster and more (300-400%) insensitive to mismatch. The reliability and process variation insensitivity is also analyzed through Monte Carlo analysis.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121262149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616921
R. Wu, Chen Wang
A novel amplifier design technique based on negative impedance compensation has been proposed in our recent paper. In this paper, we investigate the stability of this amplifier system. The parameter space approach has been used to determine system parameters in the negative impedance circuit such that the stability of the amplifier system can be guaranteed in a certain region represented by those parameters. The simulation results have demonstrated that stable circuit behavior for the amplifier can be achieved.
{"title":"Stability analysis of an amplifier with negative impedance compensation","authors":"R. Wu, Chen Wang","doi":"10.1109/MWSCAS.2008.4616921","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616921","url":null,"abstract":"A novel amplifier design technique based on negative impedance compensation has been proposed in our recent paper. In this paper, we investigate the stability of this amplifier system. The parameter space approach has been used to determine system parameters in the negative impedance circuit such that the stability of the amplifier system can be guaranteed in a certain region represented by those parameters. The simulation results have demonstrated that stable circuit behavior for the amplifier can be achieved.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122470420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616818
B. Shastri, N. Kheder, D. Plant
We experimentally study the effect of channel impairments on the performance of a burst-mode receiver (BMRx) in a 622 Mb/s 20-km Gigabit-capable passive optical network (GPON) uplink. Specifically, we study the impact of mode-partition noise in the GPON uplink in terms of the bit-error rate (BER) and the packet loss ratio (PLR) performance of the system. Our receiver features automatic phase acquisition using a clock phase aligner (CPA), and forward-error correction using (255, 239) Reed-Solomon codes. The BMRx provides instantaneous (0 preamble bit) phase acquisition and a PLR < 10-6 for any phase step (plusmn2pi rads) between consecutive packets. The receiver also accomplishes a 3 dB coding gain at a BER = 10-10. The CPA makes use of a phase picking algorithm and an oversampling clock and data recovery circuit operated at twice the bit rate.
{"title":"Effect of channel impairments on the performance of burst-mode receivers in gigabit PON","authors":"B. Shastri, N. Kheder, D. Plant","doi":"10.1109/MWSCAS.2008.4616818","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616818","url":null,"abstract":"We experimentally study the effect of channel impairments on the performance of a burst-mode receiver (BMRx) in a 622 Mb/s 20-km Gigabit-capable passive optical network (GPON) uplink. Specifically, we study the impact of mode-partition noise in the GPON uplink in terms of the bit-error rate (BER) and the packet loss ratio (PLR) performance of the system. Our receiver features automatic phase acquisition using a clock phase aligner (CPA), and forward-error correction using (255, 239) Reed-Solomon codes. The BMRx provides instantaneous (0 preamble bit) phase acquisition and a PLR < 10-6 for any phase step (plusmn2pi rads) between consecutive packets. The receiver also accomplishes a 3 dB coding gain at a BER = 10-10. The CPA makes use of a phase picking algorithm and an oversampling clock and data recovery circuit operated at twice the bit rate.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129761134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616931
Yu Song, E. Moule, Z. Ignjatovic
In this paper, we propose an adaptable-order single-loop digital DeltaSigma modulator which offers flexible noise shaping performance to maximize hardware sharing and power efficiency in multi-band frequency synthesizer applications. The proposed architecture utilizes feedback coefficients that allow computationally efficient digital implementation and also yield good noise shaping. Fixed-magnitude quantizer dithering is employed to eliminate idle channel tones and also to suppress in-band noise more efficiently than input dithering structures. MATLAB simulation was carried out. Finally, the proposed architecture was implemented and verified in an FPGA device.
{"title":"Adaptable digital delta-sigma modulator for multiband frequency synthesizer","authors":"Yu Song, E. Moule, Z. Ignjatovic","doi":"10.1109/MWSCAS.2008.4616931","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616931","url":null,"abstract":"In this paper, we propose an adaptable-order single-loop digital DeltaSigma modulator which offers flexible noise shaping performance to maximize hardware sharing and power efficiency in multi-band frequency synthesizer applications. The proposed architecture utilizes feedback coefficients that allow computationally efficient digital implementation and also yield good noise shaping. Fixed-magnitude quantizer dithering is employed to eliminate idle channel tones and also to suppress in-band noise more efficiently than input dithering structures. MATLAB simulation was carried out. Finally, the proposed architecture was implemented and verified in an FPGA device.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130450462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616848
J. Dobes
Many software tools of the PSpice class do not contain an implementation of the steady-state algorithm, especially for autonomous circuits. In the paper, an add-on is described to the algorithm for implicit numerical integration which determines the steady state of both nonautonomous and autonomous circuits by an extrapolation method. The extrapolation procedure is based on scalar epsilon-algorithm which is relatively easy for programing and efficient in terms of number of required iterations. Since the selected algorithm for the implicit numerical integration gives values of derivatives at any time, the determination of unknown periods of autonomous circuits can be performed by modified Newton-Raphson method. The efficiency of the procedure is demonstrated by the steady-state analysis of a tunable distributed microwave oscillator with the results compared with measured data.
{"title":"A steady-state add-on to the algorithm for implicit numerical integration","authors":"J. Dobes","doi":"10.1109/MWSCAS.2008.4616848","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616848","url":null,"abstract":"Many software tools of the PSpice class do not contain an implementation of the steady-state algorithm, especially for autonomous circuits. In the paper, an add-on is described to the algorithm for implicit numerical integration which determines the steady state of both nonautonomous and autonomous circuits by an extrapolation method. The extrapolation procedure is based on scalar epsilon-algorithm which is relatively easy for programing and efficient in terms of number of required iterations. Since the selected algorithm for the implicit numerical integration gives values of derivatives at any time, the determination of unknown periods of autonomous circuits can be performed by modified Newton-Raphson method. The efficiency of the procedure is demonstrated by the steady-state analysis of a tunable distributed microwave oscillator with the results compared with measured data.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128937538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616939
J. Gray, P. Hasler
Floating-gate charge storage is a key analog VLSI system technique. As the number of floating-gate elements in such VLSI systems increase, the relative area of the analog memory cell and its supporting circuitry become more critical. The compact floating-gate selection and isolation circuitry used in large-scale analog arrays is often based on a flawed assumption: that subthreshold conduction is the dominant source of parasitic charge movement associated with array isolation. The parasitic charge movement is primarily a combination of subthreshold conduction, PN-junction reverse bias current enhanced by gate-overlap, and Fowler-Nordheim tunneling. As a result, array isolation designed specifically to minimize subthreshold conduction can actually enhance the overall parasitic charge movement, leading to programming accuracy degradation. A procedure and experimental data demonstrating parasitic charge movement is shown for a device in an array fabricated on a 0.35 um process. Software and hardware hardware techniques for addressing and eliminating parasitic charge movement are discussed.
{"title":"Parasitic charge movement in floating-gate array programming","authors":"J. Gray, P. Hasler","doi":"10.1109/MWSCAS.2008.4616939","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616939","url":null,"abstract":"Floating-gate charge storage is a key analog VLSI system technique. As the number of floating-gate elements in such VLSI systems increase, the relative area of the analog memory cell and its supporting circuitry become more critical. The compact floating-gate selection and isolation circuitry used in large-scale analog arrays is often based on a flawed assumption: that subthreshold conduction is the dominant source of parasitic charge movement associated with array isolation. The parasitic charge movement is primarily a combination of subthreshold conduction, PN-junction reverse bias current enhanced by gate-overlap, and Fowler-Nordheim tunneling. As a result, array isolation designed specifically to minimize subthreshold conduction can actually enhance the overall parasitic charge movement, leading to programming accuracy degradation. A procedure and experimental data demonstrating parasitic charge movement is shown for a device in an array fabricated on a 0.35 um process. Software and hardware hardware techniques for addressing and eliminating parasitic charge movement are discussed.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"2005 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125808290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616935
A. Mvuma, S. Nishimura, T. Hinamoto
Tracking behavior of a gradient-based simplified algorithm for an adaptive infinite impulse response (IIR) notch filter with a sinusoidally-varying input signal frequency is presented in this paper. A first-order difference equation with respect to a steady-state instantaneous frequency tracking error is derived. The difference equation is used to derive tracking error and tracking mean square error (MSE) expressions based on the power spectral density (PSD) method. Extensive computer simulations are included to substantiate the analysis and show its limits.
{"title":"Tracking characteristics of an adaptive IIR notch filter for sinusoidal frequency variation","authors":"A. Mvuma, S. Nishimura, T. Hinamoto","doi":"10.1109/MWSCAS.2008.4616935","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616935","url":null,"abstract":"Tracking behavior of a gradient-based simplified algorithm for an adaptive infinite impulse response (IIR) notch filter with a sinusoidally-varying input signal frequency is presented in this paper. A first-order difference equation with respect to a steady-state instantaneous frequency tracking error is derived. The difference equation is used to derive tracking error and tracking mean square error (MSE) expressions based on the power spectral density (PSD) method. Extensive computer simulations are included to substantiate the analysis and show its limits.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126180488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616920
Frank Tuffner, J. Pierre, R. Kubichek
In this paper we introduce a computationally efficient method for updating a weighted Welch periodogram for nonstationary signals. Non-parametric spectral estimation techniques, such as the Welch periodogram, are highly mature topics in signal processing. They have a wide variety of applications in signal analysis including real-time applications with modern test and measurement systems. In many of these real-time applications the data is nonstationary having a power spectrum that is changing over time. This paper introduces a method of generating a weighted update of the Welch periodogram as more data becomes available. We find that for a certain class of weighting functions a computationally efficient algorithm can be found. The paper also presents calculations of the computational complexity of the updating algorithm and simulations for nonstationary signals.
{"title":"Computationally efficient updating of a weighted Welch periodogram for nonstationary signals","authors":"Frank Tuffner, J. Pierre, R. Kubichek","doi":"10.1109/MWSCAS.2008.4616920","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616920","url":null,"abstract":"In this paper we introduce a computationally efficient method for updating a weighted Welch periodogram for nonstationary signals. Non-parametric spectral estimation techniques, such as the Welch periodogram, are highly mature topics in signal processing. They have a wide variety of applications in signal analysis including real-time applications with modern test and measurement systems. In many of these real-time applications the data is nonstationary having a power spectrum that is changing over time. This paper introduces a method of generating a weighted update of the Welch periodogram as more data becomes available. We find that for a certain class of weighting functions a computationally efficient algorithm can be found. The paper also presents calculations of the computational complexity of the updating algorithm and simulations for nonstationary signals.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114262998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616925
A. C. Parker, J. Joshi, Chih-Chieh Hsu, N.A.D. Singh
A neural dendritic computational circuit design is presented here. The circuit models the result of action potentials applied to biological synapses on a portion of a dendritic tree. The resultant excitatory post synaptic potentials (EPSPs) are combined in a dendritic tree that demonstrates linear, superlinear and sublinear summation of both spatially and temporally separated EPSPs. The synapse circuit models include neurotransmitter action, reuptake and membrane potentials. The output of the circuit is a combined Excitatory Post Synaptic Potential (EPSP). The circuit is simulated using carbon nanotube SPICE models. Variations of this design can be implemented to create a variety of dendritic computational subunits.
{"title":"A carbon nanotube implementation of temporal and spatial dendritic computations","authors":"A. C. Parker, J. Joshi, Chih-Chieh Hsu, N.A.D. Singh","doi":"10.1109/MWSCAS.2008.4616925","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616925","url":null,"abstract":"A neural dendritic computational circuit design is presented here. The circuit models the result of action potentials applied to biological synapses on a portion of a dendritic tree. The resultant excitatory post synaptic potentials (EPSPs) are combined in a dendritic tree that demonstrates linear, superlinear and sublinear summation of both spatially and temporally separated EPSPs. The synapse circuit models include neurotransmitter action, reuptake and membrane potentials. The output of the circuit is a combined Excitatory Post Synaptic Potential (EPSP). The circuit is simulated using carbon nanotube SPICE models. Variations of this design can be implemented to create a variety of dendritic computational subunits.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123011625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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