Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616882
Jipeng Wang, B. Jalali-Farahani
This paper reports the transistor-level design of a continuous-time 2-1 MASH sigma delta modulator with digital adaptive tuning of the cancellation logic. The modulator is designed for broadband wireless applications and provides 12 bits of resolution for a 10 MHz signal bandwidth. A direct approach to design the CT MASH modulator is used which reduces the coupling between the MASH stages. The problems of excess loop delay and clock jitter are addressed. Excess delay compensation loops are used to overcome the problem of excess loop delay. Multi-bit quantizers with NRZ DACs are used to reduce the effect of clock jitter. It is shown that without calibration, the performance of a CT MASH modulator would be severely degraded due to different analog imperfections such as finite gain and bandwidth of the Opamp, clock jitter and even addition of the excess delay compensation loops. The catastrophic degradation is due to the leakage of lower order noise to the output of the modulator. An adaptive digital tuning of the digital filters is used in this design to regain the performance of the modulator in presence of the above errors. Simulation results show that the modulator provides the required resolution while consuming 20 mW of power from 1.8 V supply voltage.
{"title":"A CT MASH ΣΔ modulator with adaptive digital tuning for analog circuit imperfections","authors":"Jipeng Wang, B. Jalali-Farahani","doi":"10.1109/MWSCAS.2008.4616882","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616882","url":null,"abstract":"This paper reports the transistor-level design of a continuous-time 2-1 MASH sigma delta modulator with digital adaptive tuning of the cancellation logic. The modulator is designed for broadband wireless applications and provides 12 bits of resolution for a 10 MHz signal bandwidth. A direct approach to design the CT MASH modulator is used which reduces the coupling between the MASH stages. The problems of excess loop delay and clock jitter are addressed. Excess delay compensation loops are used to overcome the problem of excess loop delay. Multi-bit quantizers with NRZ DACs are used to reduce the effect of clock jitter. It is shown that without calibration, the performance of a CT MASH modulator would be severely degraded due to different analog imperfections such as finite gain and bandwidth of the Opamp, clock jitter and even addition of the excess delay compensation loops. The catastrophic degradation is due to the leakage of lower order noise to the output of the modulator. An adaptive digital tuning of the digital filters is used in this design to regain the performance of the modulator in presence of the above errors. Simulation results show that the modulator provides the required resolution while consuming 20 mW of power from 1.8 V supply voltage.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133380879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616821
M. E. Heidari, A. Mirzaei, R. Bagheri, S. Chehrazi, A. Abidi
By applying basic geometrical rules we analyze an LC quadrature oscillator. Various oscillation modes and their stabilities are investigated and impacts of mismatches on the quadrature accuracy are calculated.
{"title":"Geometrical analysis of LC quadrature oscillator","authors":"M. E. Heidari, A. Mirzaei, R. Bagheri, S. Chehrazi, A. Abidi","doi":"10.1109/MWSCAS.2008.4616821","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616821","url":null,"abstract":"By applying basic geometrical rules we analyze an LC quadrature oscillator. Various oscillation modes and their stabilities are investigated and impacts of mismatches on the quadrature accuracy are calculated.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131816404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616730
T. Ragheb, J. Laska, H. Nejati, S. Kirolos, Richard Baraniuk, Y. Massoud
In this paper, we utilize recent advances in compressive sensing theory to enable signal acquisition beyond Nyquist sampling constraints. We successfully recover signals sampled at sub-Nyquist sampling rates by exploiting additional structure other than bandlimitedness. We present a working prototype of compressive analog-to-digital converter (CADC) based on a random demodulation architecture. The architecture is particularly suitable for wideband signals that are sparse in the time-frequency plane. CADC has the advantage of enhancing the performance of communication and multimedia systems by increasing the transmission rate for the same bandwidth. We report successful reconstruction of AM modulated signals at sampling rates down to 1/8 of the Nyquist-rate, which represents an up to 87.5% savings in the bandwidth and the storage memory.
{"title":"A prototype hardware for random demodulation based compressive analog-to-digital conversion","authors":"T. Ragheb, J. Laska, H. Nejati, S. Kirolos, Richard Baraniuk, Y. Massoud","doi":"10.1109/MWSCAS.2008.4616730","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616730","url":null,"abstract":"In this paper, we utilize recent advances in compressive sensing theory to enable signal acquisition beyond Nyquist sampling constraints. We successfully recover signals sampled at sub-Nyquist sampling rates by exploiting additional structure other than bandlimitedness. We present a working prototype of compressive analog-to-digital converter (CADC) based on a random demodulation architecture. The architecture is particularly suitable for wideband signals that are sparse in the time-frequency plane. CADC has the advantage of enhancing the performance of communication and multimedia systems by increasing the transmission rate for the same bandwidth. We report successful reconstruction of AM modulated signals at sampling rates down to 1/8 of the Nyquist-rate, which represents an up to 87.5% savings in the bandwidth and the storage memory.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132119392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616776
P. P. Kundu, Oishila Bandyopadhyay, Amitabha Sinha
In this paper a novel technique to determine the optimal moduli set has been introduced and an efficient RNS multiplier based on Wallace tree multiplier (for 32 bit arithmetic unit) for DSP applications is presented. Performance analysis on a number of DSP functions like FIR, FFT etc. clearly indicates the novelty of the scheme.
{"title":"An efficient architecture of RNS based Wallace Tree multiplier for DSP applications","authors":"P. P. Kundu, Oishila Bandyopadhyay, Amitabha Sinha","doi":"10.1109/MWSCAS.2008.4616776","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616776","url":null,"abstract":"In this paper a novel technique to determine the optimal moduli set has been introduced and an efficient RNS multiplier based on Wallace tree multiplier (for 32 bit arithmetic unit) for DSP applications is presented. Performance analysis on a number of DSP functions like FIR, FFT etc. clearly indicates the novelty of the scheme.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"55 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113969476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616722
Huan-Chien Yang, H. Huang, Chi-Lin Chen, Ming-Hsin Huang, Ke-Horng Chen
Current feedback compensation technique (CFC) can adaptively adjust the phase margin for achieving better transient response than that with variant phase margin at different load current conditions. Not only fast transient response is attained due to suitable phase margin but also the minimum load current limitation can be greatly reduced to about 50 muA without sacrificing bandwidth at light load current condition. Besides, CFC technique can have high PSRR bandwidth with compatible compensation capacitors compared to the Q-reduction technique (Lau, 2007). The capacitor-free LDO regulator with CFC technique is fabricated by TSMC 0.35 mum 2P4M CMOS process with small compensation capacitors 5pF and 1.5 pF. Experimental results demonstrate that the minimum load can be reduced to 50 muA and transient response time with adaptively phase margin control is smaller than 1 mus.
{"title":"Current feedback compensation (CFC) technique for adaptively adjusting the phase margin in capacitor-free LDO regulators","authors":"Huan-Chien Yang, H. Huang, Chi-Lin Chen, Ming-Hsin Huang, Ke-Horng Chen","doi":"10.1109/MWSCAS.2008.4616722","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616722","url":null,"abstract":"Current feedback compensation technique (CFC) can adaptively adjust the phase margin for achieving better transient response than that with variant phase margin at different load current conditions. Not only fast transient response is attained due to suitable phase margin but also the minimum load current limitation can be greatly reduced to about 50 muA without sacrificing bandwidth at light load current condition. Besides, CFC technique can have high PSRR bandwidth with compatible compensation capacitors compared to the Q-reduction technique (Lau, 2007). The capacitor-free LDO regulator with CFC technique is fabricated by TSMC 0.35 mum 2P4M CMOS process with small compensation capacitors 5pF and 1.5 pF. Experimental results demonstrate that the minimum load can be reduced to 50 muA and transient response time with adaptively phase margin control is smaller than 1 mus.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122609240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616795
Y. Takahashi, T. Sekine, M. Yokoyama
The common subexpression elimination (CSE) techniques address the issue of minimizing the number of adders needed to implement the multiple constant multiplication (MCM) blocks. In this paper, we provide a comparison of hardware reductions achieved using the horizontal, vertical, oblique and combining horizontal and vertical CSEs in realizing constant multipliers. Our FPGA implementation results included in 52 MCM examples show that three different (horizontal, horizontal and vertical, and efficient horizontal and vertical) CSEs have a good area-time product performance, in the MCM matrix range of 800 and over.
{"title":"A comparison of multiplierless multiple constant multiplication using common subexpression elimination method","authors":"Y. Takahashi, T. Sekine, M. Yokoyama","doi":"10.1109/MWSCAS.2008.4616795","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616795","url":null,"abstract":"The common subexpression elimination (CSE) techniques address the issue of minimizing the number of adders needed to implement the multiple constant multiplication (MCM) blocks. In this paper, we provide a comparison of hardware reductions achieved using the horizontal, vertical, oblique and combining horizontal and vertical CSEs in realizing constant multipliers. Our FPGA implementation results included in 52 MCM examples show that three different (horizontal, horizontal and vertical, and efficient horizontal and vertical) CSEs have a good area-time product performance, in the MCM matrix range of 800 and over.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128984420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616804
Shih-Yu Chiu, Jia-Rui Zhang, L. Lan
As a nonparametric statistical method, the mean shift algorithm has recently attracted much attention in the computer vision community due to its efficiency in motion tracking and clustering analysis. Its convergence rate is, however, slow around the convergence point. One way to tackle this problem is to switch the search mechanism to Newtonpsilas method which has a quadratic order of convergence rate. This article thus presents a dual-mode mean-shift algorithm which combines both merits of the mean-shift and Newtonpsilas algorithms. Some numerical experiments were conducted to confirm the effectiveness of the proposed approach.
{"title":"A dual-mode mean-shift algorithm","authors":"Shih-Yu Chiu, Jia-Rui Zhang, L. Lan","doi":"10.1109/MWSCAS.2008.4616804","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616804","url":null,"abstract":"As a nonparametric statistical method, the mean shift algorithm has recently attracted much attention in the computer vision community due to its efficiency in motion tracking and clustering analysis. Its convergence rate is, however, slow around the convergence point. One way to tackle this problem is to switch the search mechanism to Newtonpsilas method which has a quadratic order of convergence rate. This article thus presents a dual-mode mean-shift algorithm which combines both merits of the mean-shift and Newtonpsilas algorithms. Some numerical experiments were conducted to confirm the effectiveness of the proposed approach.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129309731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616936
P. Sumathi, P. Janakiraman
An ultrasonic range finder for mobile robots has been proposed which uses the sliding discrete Fourier transform (SDFT) for extracting the low frequency sinusoidal envelope of a modulated ultrasonic signal. The continuous wave method uses the phase shift between the envelopes of infrared and ultrasonic carriers modulated by identical low frequency sine waves, for range measurement. The infrared sensor receives the reference waveform almost instantaneously, while the envelope of the modulated ultrasonic signal undergoes a phase-shift proportional to the distance traversed. Any frequency-drift in the envelope, which may occur at the sending or the receiving end, is tracked and compensated by the integrated phase locked loop (PLL). The fundamental components corresponding to the envelopes of the received reference (IR) as well as the ultrasonic signals are extracted using the SDFT procedure, in real time. The phase shift is determined by the Park transform procedure. Extensive simulation studies have been made, in the MATLAB DSP Builder environment so as to implement the scheme into a single Cyclone-II FPGA chip.
{"title":"Sliding DFT based ultrasonic ranger","authors":"P. Sumathi, P. Janakiraman","doi":"10.1109/MWSCAS.2008.4616936","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616936","url":null,"abstract":"An ultrasonic range finder for mobile robots has been proposed which uses the sliding discrete Fourier transform (SDFT) for extracting the low frequency sinusoidal envelope of a modulated ultrasonic signal. The continuous wave method uses the phase shift between the envelopes of infrared and ultrasonic carriers modulated by identical low frequency sine waves, for range measurement. The infrared sensor receives the reference waveform almost instantaneously, while the envelope of the modulated ultrasonic signal undergoes a phase-shift proportional to the distance traversed. Any frequency-drift in the envelope, which may occur at the sending or the receiving end, is tracked and compensated by the integrated phase locked loop (PLL). The fundamental components corresponding to the envelopes of the received reference (IR) as well as the ultrasonic signals are extracted using the SDFT procedure, in real time. The phase shift is determined by the Park transform procedure. Extensive simulation studies have been made, in the MATLAB DSP Builder environment so as to implement the scheme into a single Cyclone-II FPGA chip.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128441467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616751
N. Ekekwe, R. Etienne-Cummings
This paper presents the design of an adaptive hysteretic comparator optimized for noisy environment. It features an input rail-to-rail opamp which uses feedback networks to set varying hysteretic thresholds while maintaining a constant hysteretic band for increased noise immunity and stability. The chip which can resolve up to 9 bits consumes a total power of 3.8 mW and takes an active area of 0.021 mm2 in a 2P3M 0.5 mum CMOS process with 20 ns propagation delay.
{"title":"Adaptive hysteretic comparator with opamp threshold level setting","authors":"N. Ekekwe, R. Etienne-Cummings","doi":"10.1109/MWSCAS.2008.4616751","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616751","url":null,"abstract":"This paper presents the design of an adaptive hysteretic comparator optimized for noisy environment. It features an input rail-to-rail opamp which uses feedback networks to set varying hysteretic thresholds while maintaining a constant hysteretic band for increased noise immunity and stability. The chip which can resolve up to 9 bits consumes a total power of 3.8 mW and takes an active area of 0.021 mm2 in a 2P3M 0.5 mum CMOS process with 20 ns propagation delay.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128457966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616739
Xin Zhang, Yazi Cao, Q. Zhang
A new approach for via modeling in multilayer circuits is presented in this paper. The proposed technique combines transfer function with neural network to enhance the learning ability of neural network. It is capable of providing accurate simulation models even if an equivalent circuit is not available. It retains the EM level accuracy and reduces CPU time significantly compared to EM simulator. Examples of via holes for both multilayer printed circuit boards and integrated circuits are presented to demonstrate the accuracy and efficiency of this proposed method.
{"title":"A combined transfer function and neural network method for modeling via in multilayer circuits","authors":"Xin Zhang, Yazi Cao, Q. Zhang","doi":"10.1109/MWSCAS.2008.4616739","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616739","url":null,"abstract":"A new approach for via modeling in multilayer circuits is presented in this paper. The proposed technique combines transfer function with neural network to enhance the learning ability of neural network. It is capable of providing accurate simulation models even if an equivalent circuit is not available. It retains the EM level accuracy and reduces CPU time significantly compared to EM simulator. Examples of via holes for both multilayer printed circuit boards and integrated circuits are presented to demonstrate the accuracy and efficiency of this proposed method.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116421725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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