Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616889
S. Rahaman, M. Chowdhury
As technology scales, inductive crosstalk becomes prominent along with capacitive crosstalk, and it is creating a significant bottleneck in high-speed deep sub-micron and nanoscale integrated circuits. For inductive coupling, worst-case delay occurs when all the bus lines simultaneously switch in the same direction. This switching case is the best case switching pattern for capacitive-dominant on-chip buses. Therefore, various existing coding techniques for capacitive crosstalk reduction are not suitable for high-speed circuits, where electromagnetic effect can not be ignored. In this paper, various hybrid bus-invert (BI) coding methods have been proposed for RLC coupling-aware on-chip buses. Simulation results show that simultaneous switching noise (SSN) for inductance-dominant buses can be reduced by roughly 40% and, thereby, worst case coupling delay is also reduced. Besides, a joint coding approach is proposed for simultaneous reduction of SSN and higher reliability to errors due to deep-submicron (DSM) noise.
{"title":"Joint coding for RLC coupling-aware on-chip buses","authors":"S. Rahaman, M. Chowdhury","doi":"10.1109/MWSCAS.2008.4616889","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616889","url":null,"abstract":"As technology scales, inductive crosstalk becomes prominent along with capacitive crosstalk, and it is creating a significant bottleneck in high-speed deep sub-micron and nanoscale integrated circuits. For inductive coupling, worst-case delay occurs when all the bus lines simultaneously switch in the same direction. This switching case is the best case switching pattern for capacitive-dominant on-chip buses. Therefore, various existing coding techniques for capacitive crosstalk reduction are not suitable for high-speed circuits, where electromagnetic effect can not be ignored. In this paper, various hybrid bus-invert (BI) coding methods have been proposed for RLC coupling-aware on-chip buses. Simulation results show that simultaneous switching noise (SSN) for inductance-dominant buses can be reduced by roughly 40% and, thereby, worst case coupling delay is also reduced. Besides, a joint coding approach is proposed for simultaneous reduction of SSN and higher reliability to errors due to deep-submicron (DSM) noise.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127497161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616924
S. Mahmoud
A novel current-mode CMOS digitally controlled variable gain amplifier (VGA) is presented in this paper. The proposed VGA is based on new plusmn0.75 V digitally programmable second-generation current conveyors (DPCCII) with digital current gain control. The input stage of the DPCCII is realized using two complementary MOS differential pairs connected in parallel to ensure rail-to-rail operation. The output stage consists of a class-AB push-pull circuit, which guarantees high current driving capability. The digital control of the DPCCII, based on transistor arrays and MOS switches, provides variable current gain using an n-bits code-word. All proposed circuits are simulated using PSPICE with CMOS TSMC 0.25 mum technology.
{"title":"Low voltage current-mode digitally controlled VGA based on digitally programmble current conveyors","authors":"S. Mahmoud","doi":"10.1109/MWSCAS.2008.4616924","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616924","url":null,"abstract":"A novel current-mode CMOS digitally controlled variable gain amplifier (VGA) is presented in this paper. The proposed VGA is based on new plusmn0.75 V digitally programmable second-generation current conveyors (DPCCII) with digital current gain control. The input stage of the DPCCII is realized using two complementary MOS differential pairs connected in parallel to ensure rail-to-rail operation. The output stage consists of a class-AB push-pull circuit, which guarantees high current driving capability. The digital control of the DPCCII, based on transistor arrays and MOS switches, provides variable current gain using an n-bits code-word. All proposed circuits are simulated using PSPICE with CMOS TSMC 0.25 mum technology.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129167018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616741
B. Taskin, Jianchao Lu
In mainstream ASIC design, industry standard automation tools are used in generating circuit implementations that satisfy the timing and power budgets. A typical timing budget follows the specifications of a clock frequency governed by the longest data path in the circuit. To satisfy this constraint, a zero-skew clock network that minimizes or bounds the clock skew is synthesized. Due to variations, however, zero clock skew cannot always be maintained and timing violations occur. This paper describes a post-clock-tree synthesis (CTS) delay insertion process on the clock tree network in order to fix timing violations that occur after such automated design tools are used. A mathematical formulation is presented which computes the minimum amount of delay to be inserted on each branch of the clock network. Experimental results show that the clock networks of the largest ISCASpsila89 circuits can be corrected post-CTS to resolve the timing conflicts in approximately 90% of the circuits with minimal delay insertion (0.159timesclock period per clock path on average).
{"title":"Post-CTS delay insertion to fix timing violations","authors":"B. Taskin, Jianchao Lu","doi":"10.1109/MWSCAS.2008.4616741","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616741","url":null,"abstract":"In mainstream ASIC design, industry standard automation tools are used in generating circuit implementations that satisfy the timing and power budgets. A typical timing budget follows the specifications of a clock frequency governed by the longest data path in the circuit. To satisfy this constraint, a zero-skew clock network that minimizes or bounds the clock skew is synthesized. Due to variations, however, zero clock skew cannot always be maintained and timing violations occur. This paper describes a post-clock-tree synthesis (CTS) delay insertion process on the clock tree network in order to fix timing violations that occur after such automated design tools are used. A mathematical formulation is presented which computes the minimum amount of delay to be inserted on each branch of the clock network. Experimental results show that the clock networks of the largest ISCASpsila89 circuits can be corrected post-CTS to resolve the timing conflicts in approximately 90% of the circuits with minimal delay insertion (0.159timesclock period per clock path on average).","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134011226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616776
P. P. Kundu, Oishila Bandyopadhyay, Amitabha Sinha
In this paper a novel technique to determine the optimal moduli set has been introduced and an efficient RNS multiplier based on Wallace tree multiplier (for 32 bit arithmetic unit) for DSP applications is presented. Performance analysis on a number of DSP functions like FIR, FFT etc. clearly indicates the novelty of the scheme.
{"title":"An efficient architecture of RNS based Wallace Tree multiplier for DSP applications","authors":"P. P. Kundu, Oishila Bandyopadhyay, Amitabha Sinha","doi":"10.1109/MWSCAS.2008.4616776","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616776","url":null,"abstract":"In this paper a novel technique to determine the optimal moduli set has been introduced and an efficient RNS multiplier based on Wallace tree multiplier (for 32 bit arithmetic unit) for DSP applications is presented. Performance analysis on a number of DSP functions like FIR, FFT etc. clearly indicates the novelty of the scheme.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"55 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113969476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616722
Huan-Chien Yang, H. Huang, Chi-Lin Chen, Ming-Hsin Huang, Ke-Horng Chen
Current feedback compensation technique (CFC) can adaptively adjust the phase margin for achieving better transient response than that with variant phase margin at different load current conditions. Not only fast transient response is attained due to suitable phase margin but also the minimum load current limitation can be greatly reduced to about 50 muA without sacrificing bandwidth at light load current condition. Besides, CFC technique can have high PSRR bandwidth with compatible compensation capacitors compared to the Q-reduction technique (Lau, 2007). The capacitor-free LDO regulator with CFC technique is fabricated by TSMC 0.35 mum 2P4M CMOS process with small compensation capacitors 5pF and 1.5 pF. Experimental results demonstrate that the minimum load can be reduced to 50 muA and transient response time with adaptively phase margin control is smaller than 1 mus.
{"title":"Current feedback compensation (CFC) technique for adaptively adjusting the phase margin in capacitor-free LDO regulators","authors":"Huan-Chien Yang, H. Huang, Chi-Lin Chen, Ming-Hsin Huang, Ke-Horng Chen","doi":"10.1109/MWSCAS.2008.4616722","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616722","url":null,"abstract":"Current feedback compensation technique (CFC) can adaptively adjust the phase margin for achieving better transient response than that with variant phase margin at different load current conditions. Not only fast transient response is attained due to suitable phase margin but also the minimum load current limitation can be greatly reduced to about 50 muA without sacrificing bandwidth at light load current condition. Besides, CFC technique can have high PSRR bandwidth with compatible compensation capacitors compared to the Q-reduction technique (Lau, 2007). The capacitor-free LDO regulator with CFC technique is fabricated by TSMC 0.35 mum 2P4M CMOS process with small compensation capacitors 5pF and 1.5 pF. Experimental results demonstrate that the minimum load can be reduced to 50 muA and transient response time with adaptively phase margin control is smaller than 1 mus.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122609240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616795
Y. Takahashi, T. Sekine, M. Yokoyama
The common subexpression elimination (CSE) techniques address the issue of minimizing the number of adders needed to implement the multiple constant multiplication (MCM) blocks. In this paper, we provide a comparison of hardware reductions achieved using the horizontal, vertical, oblique and combining horizontal and vertical CSEs in realizing constant multipliers. Our FPGA implementation results included in 52 MCM examples show that three different (horizontal, horizontal and vertical, and efficient horizontal and vertical) CSEs have a good area-time product performance, in the MCM matrix range of 800 and over.
{"title":"A comparison of multiplierless multiple constant multiplication using common subexpression elimination method","authors":"Y. Takahashi, T. Sekine, M. Yokoyama","doi":"10.1109/MWSCAS.2008.4616795","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616795","url":null,"abstract":"The common subexpression elimination (CSE) techniques address the issue of minimizing the number of adders needed to implement the multiple constant multiplication (MCM) blocks. In this paper, we provide a comparison of hardware reductions achieved using the horizontal, vertical, oblique and combining horizontal and vertical CSEs in realizing constant multipliers. Our FPGA implementation results included in 52 MCM examples show that three different (horizontal, horizontal and vertical, and efficient horizontal and vertical) CSEs have a good area-time product performance, in the MCM matrix range of 800 and over.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128984420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616804
Shih-Yu Chiu, Jia-Rui Zhang, L. Lan
As a nonparametric statistical method, the mean shift algorithm has recently attracted much attention in the computer vision community due to its efficiency in motion tracking and clustering analysis. Its convergence rate is, however, slow around the convergence point. One way to tackle this problem is to switch the search mechanism to Newtonpsilas method which has a quadratic order of convergence rate. This article thus presents a dual-mode mean-shift algorithm which combines both merits of the mean-shift and Newtonpsilas algorithms. Some numerical experiments were conducted to confirm the effectiveness of the proposed approach.
{"title":"A dual-mode mean-shift algorithm","authors":"Shih-Yu Chiu, Jia-Rui Zhang, L. Lan","doi":"10.1109/MWSCAS.2008.4616804","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616804","url":null,"abstract":"As a nonparametric statistical method, the mean shift algorithm has recently attracted much attention in the computer vision community due to its efficiency in motion tracking and clustering analysis. Its convergence rate is, however, slow around the convergence point. One way to tackle this problem is to switch the search mechanism to Newtonpsilas method which has a quadratic order of convergence rate. This article thus presents a dual-mode mean-shift algorithm which combines both merits of the mean-shift and Newtonpsilas algorithms. Some numerical experiments were conducted to confirm the effectiveness of the proposed approach.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129309731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616936
P. Sumathi, P. Janakiraman
An ultrasonic range finder for mobile robots has been proposed which uses the sliding discrete Fourier transform (SDFT) for extracting the low frequency sinusoidal envelope of a modulated ultrasonic signal. The continuous wave method uses the phase shift between the envelopes of infrared and ultrasonic carriers modulated by identical low frequency sine waves, for range measurement. The infrared sensor receives the reference waveform almost instantaneously, while the envelope of the modulated ultrasonic signal undergoes a phase-shift proportional to the distance traversed. Any frequency-drift in the envelope, which may occur at the sending or the receiving end, is tracked and compensated by the integrated phase locked loop (PLL). The fundamental components corresponding to the envelopes of the received reference (IR) as well as the ultrasonic signals are extracted using the SDFT procedure, in real time. The phase shift is determined by the Park transform procedure. Extensive simulation studies have been made, in the MATLAB DSP Builder environment so as to implement the scheme into a single Cyclone-II FPGA chip.
{"title":"Sliding DFT based ultrasonic ranger","authors":"P. Sumathi, P. Janakiraman","doi":"10.1109/MWSCAS.2008.4616936","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616936","url":null,"abstract":"An ultrasonic range finder for mobile robots has been proposed which uses the sliding discrete Fourier transform (SDFT) for extracting the low frequency sinusoidal envelope of a modulated ultrasonic signal. The continuous wave method uses the phase shift between the envelopes of infrared and ultrasonic carriers modulated by identical low frequency sine waves, for range measurement. The infrared sensor receives the reference waveform almost instantaneously, while the envelope of the modulated ultrasonic signal undergoes a phase-shift proportional to the distance traversed. Any frequency-drift in the envelope, which may occur at the sending or the receiving end, is tracked and compensated by the integrated phase locked loop (PLL). The fundamental components corresponding to the envelopes of the received reference (IR) as well as the ultrasonic signals are extracted using the SDFT procedure, in real time. The phase shift is determined by the Park transform procedure. Extensive simulation studies have been made, in the MATLAB DSP Builder environment so as to implement the scheme into a single Cyclone-II FPGA chip.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128441467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616751
N. Ekekwe, R. Etienne-Cummings
This paper presents the design of an adaptive hysteretic comparator optimized for noisy environment. It features an input rail-to-rail opamp which uses feedback networks to set varying hysteretic thresholds while maintaining a constant hysteretic band for increased noise immunity and stability. The chip which can resolve up to 9 bits consumes a total power of 3.8 mW and takes an active area of 0.021 mm2 in a 2P3M 0.5 mum CMOS process with 20 ns propagation delay.
{"title":"Adaptive hysteretic comparator with opamp threshold level setting","authors":"N. Ekekwe, R. Etienne-Cummings","doi":"10.1109/MWSCAS.2008.4616751","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616751","url":null,"abstract":"This paper presents the design of an adaptive hysteretic comparator optimized for noisy environment. It features an input rail-to-rail opamp which uses feedback networks to set varying hysteretic thresholds while maintaining a constant hysteretic band for increased noise immunity and stability. The chip which can resolve up to 9 bits consumes a total power of 3.8 mW and takes an active area of 0.021 mm2 in a 2P3M 0.5 mum CMOS process with 20 ns propagation delay.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128457966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616739
Xin Zhang, Yazi Cao, Q. Zhang
A new approach for via modeling in multilayer circuits is presented in this paper. The proposed technique combines transfer function with neural network to enhance the learning ability of neural network. It is capable of providing accurate simulation models even if an equivalent circuit is not available. It retains the EM level accuracy and reduces CPU time significantly compared to EM simulator. Examples of via holes for both multilayer printed circuit boards and integrated circuits are presented to demonstrate the accuracy and efficiency of this proposed method.
{"title":"A combined transfer function and neural network method for modeling via in multilayer circuits","authors":"Xin Zhang, Yazi Cao, Q. Zhang","doi":"10.1109/MWSCAS.2008.4616739","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616739","url":null,"abstract":"A new approach for via modeling in multilayer circuits is presented in this paper. The proposed technique combines transfer function with neural network to enhance the learning ability of neural network. It is capable of providing accurate simulation models even if an equivalent circuit is not available. It retains the EM level accuracy and reduces CPU time significantly compared to EM simulator. Examples of via holes for both multilayer printed circuit boards and integrated circuits are presented to demonstrate the accuracy and efficiency of this proposed method.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116421725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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