Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486242
Chip-Hong Chang, B. Falkowski
A new algorithm that generates optimal fixed polarity Reed-Muller expansions based on user specified optimization criteria is shown. The algorithm accepts reduced representation of Boolean functions in form of an array of cubes and operates on an Algebraic Ternary Decision Tree together with lookup tables of flexible sizes. Allocation of don't care minterms is performed in an non exhaustive way by a heuristic approach based on the properties of Reed-Muller expansions.
{"title":"Flexible optimization of fixed polarity Reed-Muller expansions for multiple output completely and incompletely specified Boolean functions","authors":"Chip-Hong Chang, B. Falkowski","doi":"10.1109/ASPDAC.1995.486242","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486242","url":null,"abstract":"A new algorithm that generates optimal fixed polarity Reed-Muller expansions based on user specified optimization criteria is shown. The algorithm accepts reduced representation of Boolean functions in form of an array of cubes and operates on an Algebraic Ternary Decision Tree together with lookup tables of flexible sizes. Allocation of don't care minterms is performed in an non exhaustive way by a heuristic approach based on the properties of Reed-Muller expansions.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134239792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486357
T. Aoki, T. Toriyama, K. Ishikawa, K. Fukami
A prototype tool is developed for measuring the quality of test patterns for simulation to verify LSI functional designs. The tool is able to count activated conditional branches and evaluate the branch pass index of test patterns. The branch pass index indicates the ratio of the number of conditional branches validated by the pattern to the total number of conditional branches in a design. We developed the prototype tool for PARTHENON. The tool prints out branch identification names not examined by the test pattern. In using the tool for experimental designs, it helped designers to significantly improve pattern quality if a branch pass index of 100% for LSI verification patterns was not achieved. Only about 30 seconds of the processing time was required for a 1000 sentence module. Bugs can often be found in designs with little effort.
{"title":"A tool for measuring quality of test pattern for LSIs' functional design","authors":"T. Aoki, T. Toriyama, K. Ishikawa, K. Fukami","doi":"10.1109/ASPDAC.1995.486357","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486357","url":null,"abstract":"A prototype tool is developed for measuring the quality of test patterns for simulation to verify LSI functional designs. The tool is able to count activated conditional branches and evaluate the branch pass index of test patterns. The branch pass index indicates the ratio of the number of conditional branches validated by the pattern to the total number of conditional branches in a design. We developed the prototype tool for PARTHENON. The tool prints out branch identification names not examined by the test pattern. In using the tool for experimental designs, it helped designers to significantly improve pattern quality if a branch pass index of 100% for LSI verification patterns was not achieved. Only about 30 seconds of the processing time was required for a 1000 sentence module. Bugs can often be found in designs with little effort.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115651634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486218
W. Jung, Ghun-Up Cha, Young-Bae Kim, J. Baek, Choon-Kyung Kim
An integrated interconnect modelling system, SIMS, is developed with parametrized modeling of interconnect and an interface with schematic capture and editor. SIMS automatically drives numerical interconnect simulation as directed by technology engineers, creates a polynomial model library for interconnect parasitics, generates a netlist including the SPICE model for the interconnect structure, automatically drives circuit simulations and displays the simulation results through an advanced GUI. VLSI design with SIMS makes it possible to consider parasitic effects fast and accurately, which becomes more important in deep submicron circuit design. With this capability, circuit design with optimized interconnect layout can be achieved. Ultimately, the integrated system helps to reduce the cost of technology development and the time to market by building up the concept of design for manufacturability.
{"title":"Integrated interconnect circuit modeling for VLSI design","authors":"W. Jung, Ghun-Up Cha, Young-Bae Kim, J. Baek, Choon-Kyung Kim","doi":"10.1109/ASPDAC.1995.486218","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486218","url":null,"abstract":"An integrated interconnect modelling system, SIMS, is developed with parametrized modeling of interconnect and an interface with schematic capture and editor. SIMS automatically drives numerical interconnect simulation as directed by technology engineers, creates a polynomial model library for interconnect parasitics, generates a netlist including the SPICE model for the interconnect structure, automatically drives circuit simulations and displays the simulation results through an advanced GUI. VLSI design with SIMS makes it possible to consider parasitic effects fast and accurately, which becomes more important in deep submicron circuit design. With this capability, circuit design with optimized interconnect layout can be achieved. Ultimately, the integrated system helps to reduce the cost of technology development and the time to market by building up the concept of design for manufacturability.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122907445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486252
T. Koide, M. Ono, S. Wakabayashi, Y. Nishimaru
In this paper, we present a new performance driven placement method based on path delay constraint approach for large standard cell layout. The proposed method consists of three phases and uses the Elmore delay model to model interconnection delay precisely in each phase. In the first phase, initial placement is performed by an efficient performance driven mincut partitioning method. Next, an iterative improvement method by nonlinear programming improves the layout. The improvement is formulated as the problem of minimizing the total wire length subject to critical path delays. Finally, row assignment considering timing constraint is performed. From the experimental results, the proposed method is much better than RITUAL in point of the maximal violation ratio, the total wire length, and the cut size, and is more effective in the interconnection delay model and its extendability.
{"title":"A new performance driven placement method with the Elmore delay model for row based VLSIs","authors":"T. Koide, M. Ono, S. Wakabayashi, Y. Nishimaru","doi":"10.1109/ASPDAC.1995.486252","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486252","url":null,"abstract":"In this paper, we present a new performance driven placement method based on path delay constraint approach for large standard cell layout. The proposed method consists of three phases and uses the Elmore delay model to model interconnection delay precisely in each phase. In the first phase, initial placement is performed by an efficient performance driven mincut partitioning method. Next, an iterative improvement method by nonlinear programming improves the layout. The improvement is formulated as the problem of minimizing the total wire length subject to critical path delays. Finally, row assignment considering timing constraint is performed. From the experimental results, the proposed method is much better than RITUAL in point of the maximal violation ratio, the total wire length, and the cut size, and is more effective in the interconnection delay model and its extendability.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121837986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486349
H. Uno, T. Chiba, K. Kumatani, I. Shirakawa
A high performance design methodology is described for a digital demodulator, which is intended for the noise immune wireless infrared data communication. In this methodology, ASK (Amplitude Shift Keying) infrared signals detected by a photo detector are digitized into two logic-level pulses by an infrared receiver, and the demodulation of the digitized signals is implemented by a new architecture. On account of the interference with optical noises from fluorescent lamps, an ASK receiver is realized by a 1-bit digital demodulator, which is designed with use of a high level synthesis tool COMPASS so as to implement an algorithm for removing the noises. A part of experimental results is also shown to demonstrate the practicability.
{"title":"Synthesis and simulation of digital demodulator for infrared data communication","authors":"H. Uno, T. Chiba, K. Kumatani, I. Shirakawa","doi":"10.1109/ASPDAC.1995.486349","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486349","url":null,"abstract":"A high performance design methodology is described for a digital demodulator, which is intended for the noise immune wireless infrared data communication. In this methodology, ASK (Amplitude Shift Keying) infrared signals detected by a photo detector are digitized into two logic-level pulses by an infrared receiver, and the demodulation of the digitized signals is implemented by a new architecture. On account of the interference with optical noises from fluorescent lamps, an ASK receiver is realized by a 1-bit digital demodulator, which is designed with use of a high level synthesis tool COMPASS so as to implement an algorithm for removing the noises. A part of experimental results is also shown to demonstrate the practicability.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129086089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486348
R. Stankovic
In this paper we give a spectral transform interpretation of AND-EXOR representations of switching functions and related decision diagrams in the vector space over GF(2). The consideration is uniformly extended to the Fourier series-like expressions of functions in the complex vector space and the decision diagrams for integer-valued functions. It is shown that the multi-terminal decision diagrams, MTBDDs, and edge-valued decision diagrams, EVBDDs, for integer-valued functions are derived by using the same sets of basic functions already applied for the decision diagrams attached to some AND-EXOR expressions, but considered over the complex field. The algebraic transform decision diagrams, ATDDs, are considered as the integer counterparts of the functional decision diagrams, FDDs, attached to the algebraic transform in the same way as the FDDs are attached to the Reed-Muller expressions. It is shown that the EVBDDs are the ATDDs in different notation.
{"title":"Some remarks about spectral transform interpretation of MTBDDs and EVBDDs","authors":"R. Stankovic","doi":"10.1109/ASPDAC.1995.486348","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486348","url":null,"abstract":"In this paper we give a spectral transform interpretation of AND-EXOR representations of switching functions and related decision diagrams in the vector space over GF(2). The consideration is uniformly extended to the Fourier series-like expressions of functions in the complex vector space and the decision diagrams for integer-valued functions. It is shown that the multi-terminal decision diagrams, MTBDDs, and edge-valued decision diagrams, EVBDDs, for integer-valued functions are derived by using the same sets of basic functions already applied for the decision diagrams attached to some AND-EXOR expressions, but considered over the complex field. The algebraic transform decision diagrams, ATDDs, are considered as the integer counterparts of the functional decision diagrams, FDDs, attached to the algebraic transform in the same way as the FDDs are attached to the Reed-Muller expressions. It is shown that the EVBDDs are the ATDDs in different notation.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133631278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486209
Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, S. Ha
In this paper, we present a hardware-software cosimulation environment for heterogeneous systems. To be an efficient system verification environment for the rapid prototyping of heterogeneous systems, the environment provides interface transparency, simulation acceleration, smooth transition to cosynthesis, and integrated user interface and internal representation. As an experimental example, a heterogeneous system is cosimulated and prototyped successfully, which shows that our environment can be a useful heterogeneous system specification/verification environment for rapid prototyping.
{"title":"An integrated hardware-software cosimulation environment for heterogeneous systems prototyping","authors":"Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, S. Ha","doi":"10.1109/ASPDAC.1995.486209","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486209","url":null,"abstract":"In this paper, we present a hardware-software cosimulation environment for heterogeneous systems. To be an efficient system verification environment for the rapid prototyping of heterogeneous systems, the environment provides interface transparency, simulation acceleration, smooth transition to cosynthesis, and integrated user interface and internal representation. As an experimental example, a heterogeneous system is cosimulated and prototyped successfully, which shows that our environment can be a useful heterogeneous system specification/verification environment for rapid prototyping.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127928678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486236
J. Quintana, M. Avedillo, M.P. Parra, J. Huertas
This paper proposes an algorithm for optimum PLA folding based on its formulation as a problem of boolean satisfiability. A logical expression is derived such that the assignment of variables that satisfies it defines a folding with a minimum number of columns. The proposed algorithm uses BDDs to represent boolean functions and incorporates novel reduction techniques, obtaining satisfactory results.
{"title":"Optimum PLA folding through boolean satisfiability","authors":"J. Quintana, M. Avedillo, M.P. Parra, J. Huertas","doi":"10.1109/ASPDAC.1995.486236","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486236","url":null,"abstract":"This paper proposes an algorithm for optimum PLA folding based on its formulation as a problem of boolean satisfiability. A logical expression is derived such that the assignment of variables that satisfies it defines a folding with a minimum number of columns. The proposed algorithm uses BDDs to represent boolean functions and incorporates novel reduction techniques, obtaining satisfactory results.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128934309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486223
M. Tsuchiya, T. Koide, S. Wakabayashi, N. Yoshida
We present a new cell model for over-the-cell routing and a new over-the cell multi-channel routing method. In the proposed new cell model, terminals can be placed arbitrarily on the second layer of a cell so that each cell does not require the extra routing region on the first layer of a cell to align terminals. Unlike conventional cell models, some parts of the second layer are also utilized for the intra-cell routing in order to reduce the chip area. Therefore the size of the proposed cell model can be smaller than that of a conventional cell model. The proposed method consists of three phases. In order to utilize the proposed cell model, in phase 1, we simultaneously handle all channels to determine the most effective routing patterns from the set of possible routing patterns to minimize the chip area. In phase 2, for the effective routing patterns of nets selected in phase 1, over-the-cell routing nets are selected by a new greedy algorithm considering obstacles on over-the-cells. Finally, the conventional channel routing algorithm is applied for nets unrouted on over-the-cell. From the experimental results with MCNC benchmarks, the proposed cell model and algorithm produce smaller height of layouts as compared to those produced by conventional cell models and algorithms, and the effectiveness of the proposed method and cell model was shown.
{"title":"A three-layer over-the-cell multi-channel routing method for a new cell model","authors":"M. Tsuchiya, T. Koide, S. Wakabayashi, N. Yoshida","doi":"10.1109/ASPDAC.1995.486223","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486223","url":null,"abstract":"We present a new cell model for over-the-cell routing and a new over-the cell multi-channel routing method. In the proposed new cell model, terminals can be placed arbitrarily on the second layer of a cell so that each cell does not require the extra routing region on the first layer of a cell to align terminals. Unlike conventional cell models, some parts of the second layer are also utilized for the intra-cell routing in order to reduce the chip area. Therefore the size of the proposed cell model can be smaller than that of a conventional cell model. The proposed method consists of three phases. In order to utilize the proposed cell model, in phase 1, we simultaneously handle all channels to determine the most effective routing patterns from the set of possible routing patterns to minimize the chip area. In phase 2, for the effective routing patterns of nets selected in phase 1, over-the-cell routing nets are selected by a new greedy algorithm considering obstacles on over-the-cells. Finally, the conventional channel routing algorithm is applied for nets unrouted on over-the-cell. From the experimental results with MCNC benchmarks, the proposed cell model and algorithm produce smaller height of layouts as compared to those produced by conventional cell models and algorithms, and the effectiveness of the proposed method and cell model was shown.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116072937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486208
Hae-Dong Lee, Sun-Young Hwang
In this paper, we present a new scheduling algorithm that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm assigns an operation to a specific control step such that maximal sharing of functional units can be achieved with minimal number of memory ports, while satisfying given constraints. We propose a measure of multiport memory cost, MAV (Multiple Access Variable) which is defined as a variable accessed at several control steps, and overall memory cost is reduced by equally distributing the MAVs throughout all the control steps. When compared with previous approaches for several benchmarks available from the literature, the proposed algorithm generates the datapaths with less memory modules and interconnection structures by reflecting the memory cost in the scheduling process.
{"title":"A scheduling algorithm for multiport memory minimization in datapath synthesis","authors":"Hae-Dong Lee, Sun-Young Hwang","doi":"10.1109/ASPDAC.1995.486208","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486208","url":null,"abstract":"In this paper, we present a new scheduling algorithm that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm assigns an operation to a specific control step such that maximal sharing of functional units can be achieved with minimal number of memory ports, while satisfying given constraints. We propose a measure of multiport memory cost, MAV (Multiple Access Variable) which is defined as a variable accessed at several control steps, and overall memory cost is reduced by equally distributing the MAVs throughout all the control steps. When compared with previous approaches for several benchmarks available from the literature, the proposed algorithm generates the datapaths with less memory modules and interconnection structures by reflecting the memory cost in the scheduling process.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127829898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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