Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486230
A. Kondratyev, M. Kishinevsky, A. Yakovlev
We investigate the problem of hazard free gate level implementation of speed independent circuits specified by event based models, such as signal transition Graph (for processes with AND causality and input choice) or its extension, called change diagram (which allows OR causality). The main result of the paper is twofold: the proof that any speed independent behavior can be implemented at the gate level without hazards; and an efficient method for such an implementation. This method is based on transformations of the specification to the form satisfying the monotonous cover requirement. Since this method is based on standard gate cells it can be used both in the full custom and semi custom VLSI design. Experimental results demonstrate area and performance efficiency of our method.
{"title":"On hazard-free implementation of speed-independent circuits","authors":"A. Kondratyev, M. Kishinevsky, A. Yakovlev","doi":"10.1109/ASPDAC.1995.486230","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486230","url":null,"abstract":"We investigate the problem of hazard free gate level implementation of speed independent circuits specified by event based models, such as signal transition Graph (for processes with AND causality and input choice) or its extension, called change diagram (which allows OR causality). The main result of the paper is twofold: the proof that any speed independent behavior can be implemented at the gate level without hazards; and an efficient method for such an implementation. This method is based on transformations of the specification to the form satisfying the monotonous cover requirement. Since this method is based on standard gate cells it can be used both in the full custom and semi custom VLSI design. Experimental results demonstrate area and performance efficiency of our method.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122674920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486211
Chunghee Kim, Hyunchul Shin, Young-Uk Yu
A new performance-driven partitioning algorithm has been developed to implement a large circuit by using multiple FPGA chips. Partitioning for multiple FPGAs has several constraints to satisfy so that each partitioned subcircuit can be implemented in a FPGA chip. To obtain satisfactory results under the constraints, the partitioning is performed in two phases which are the initial partitioning for global optimisation and the iterative partitioning improvements for constraint satisfaction. Experimental results using the MCNC benchmark examples show that our partition method produces better results than those of other recent approaches on the average and that performance-driven partitioning is effective in reducing critical time delays.
{"title":"Performance-driven circuit partitioning for prototyping by using multiple FPGA chips","authors":"Chunghee Kim, Hyunchul Shin, Young-Uk Yu","doi":"10.1109/ASPDAC.1995.486211","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486211","url":null,"abstract":"A new performance-driven partitioning algorithm has been developed to implement a large circuit by using multiple FPGA chips. Partitioning for multiple FPGAs has several constraints to satisfy so that each partitioned subcircuit can be implemented in a FPGA chip. To obtain satisfactory results under the constraints, the partitioning is performed in two phases which are the initial partitioning for global optimisation and the iterative partitioning improvements for constraint satisfaction. Experimental results using the MCNC benchmark examples show that our partition method produces better results than those of other recent approaches on the average and that performance-driven partitioning is effective in reducing critical time delays.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122853238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486253
M. S. Zamani, G. Hellestrand
In this paper, we introduce a new neural network approach to the placement of gate array designs. The network used is a Kohonen self-organising map. An abstract specification of the design is converted to a set of appropriate input vectors fed to the network at random. At the end of the process, the map shows a 2-dimensional plane of the design in which the modules with higher connectivity are placed adjacent to each other, hence minimising total connection length in the design. The approach can consider external connections and is able to place modules in a rectilinear boundary. These features makes the approach capable of being used in hierarchical floorplanning algorithms.
{"title":"A neural network approach to the placement problem","authors":"M. S. Zamani, G. Hellestrand","doi":"10.1109/ASPDAC.1995.486253","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486253","url":null,"abstract":"In this paper, we introduce a new neural network approach to the placement of gate array designs. The network used is a Kohonen self-organising map. An abstract specification of the design is converted to a set of appropriate input vectors fed to the network at random. At the end of the process, the map shows a 2-dimensional plane of the design in which the modules with higher connectivity are placed adjacent to each other, hence minimising total connection length in the design. The approach can consider external connections and is able to place modules in a rectilinear boundary. These features makes the approach capable of being used in hierarchical floorplanning algorithms.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124641076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486221
Jeongsik Yang, Chan-Hong Park, Beomsup Kim
A salient digital audio signal processor for a mobile communication receiver is described. With this IC, the complete audio signal processing system of an AMPS or a TACS cellular phone is easily implemented. The processor can be also applied to cellular radio, high performance cordless telephone, etc. In the paper, as an example of application, the implementation of the AMPS audio signal processing system is presented. To save power consumption, some special consideration of low power architectures has been made. The DSP core uses 4 stage pipelining without a routine memory access stage to reduce the power consumption and execution speed. The parallel calculations of data in the DSP and separated filter blocks also contribute to reduce the clock frequency and to save power. It also provides a power-down mode that turns off the IC except the internal bus interface in the standby mode. It uses a 3.3 V power supply, a 10 MHz 4-phase clock. The data sampling rate is 10 K-samples per second.
{"title":"A digital audio signal processor for cellular phone application","authors":"Jeongsik Yang, Chan-Hong Park, Beomsup Kim","doi":"10.1109/ASPDAC.1995.486221","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486221","url":null,"abstract":"A salient digital audio signal processor for a mobile communication receiver is described. With this IC, the complete audio signal processing system of an AMPS or a TACS cellular phone is easily implemented. The processor can be also applied to cellular radio, high performance cordless telephone, etc. In the paper, as an example of application, the implementation of the AMPS audio signal processing system is presented. To save power consumption, some special consideration of low power architectures has been made. The DSP core uses 4 stage pipelining without a routine memory access stage to reduce the power consumption and execution speed. The parallel calculations of data in the DSP and separated filter blocks also contribute to reduce the clock frequency and to save power. It also provides a power-down mode that turns off the IC except the internal bus interface in the standby mode. It uses a 3.3 V power supply, a 10 MHz 4-phase clock. The data sampling rate is 10 K-samples per second.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126412953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486250
S. Ishihara, S. Minato
We present a new technique that broadens the scope of BDD application. It is a method for manipulating regular expressions that represent sets of sequences including repetitions of symbols. In general, sequences in the set represented by a regular expression have an infinite length and this makes representing and manipulating them difficult. In this paper, we introduce length constraints into a representation of regular expressions. Under these constraints, our method can represent and manipulate large-scale sets of sequences of regular expressions compactly and uniquely and greatly accelerates operations of regular expressions. As regular expressions can represent behaviors of a finite state machine, our technique provides a useful analysis method of finite state machines and can be applied to formal hardware verification techniques.
{"title":"Manipulation of regular expressions under length constraints using zero-suppressed-BDDs","authors":"S. Ishihara, S. Minato","doi":"10.1109/ASPDAC.1995.486250","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486250","url":null,"abstract":"We present a new technique that broadens the scope of BDD application. It is a method for manipulating regular expressions that represent sets of sequences including repetitions of symbols. In general, sequences in the set represented by a regular expression have an infinite length and this makes representing and manipulating them difficult. In this paper, we introduce length constraints into a representation of regular expressions. Under these constraints, our method can represent and manipulate large-scale sets of sequences of regular expressions compactly and uniquely and greatly accelerates operations of regular expressions. As regular expressions can represent behaviors of a finite state machine, our technique provides a useful analysis method of finite state machines and can be applied to formal hardware verification techniques.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133859366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486233
A. Nagao, Chiyoshi Yoshioka, T. Kambe, I. Shirakawa
A layout approach is attempted dedicatedly for MMICs (monolithic microwave integrated circuits), on which predominant layout elements are transistors, resistors, capacitors, inductors, coplanar waveguides, T junctions, etc., formed by the GaAs fabrication process. The layout issue typical of such MMICs consists essentially in how to realize a single layer placement of different shapes of layout elements under a variety of spacing, orientating, and shaping constraints. Each layout element is modeled to simplify placement tasks subject to different placement constraints, and then a set of the interconnection requirements among elements is represented by a graph, to which a planarization algorithm is effectively applied. As a result of this planarization, a placement procedure is constructed mainly by repeated application of a merging scheme. A number of experimental results are also shown to demonstrate the practicability of the described layout approach.
{"title":"A layout approach to monolithic microwave IC","authors":"A. Nagao, Chiyoshi Yoshioka, T. Kambe, I. Shirakawa","doi":"10.1109/ASPDAC.1995.486233","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486233","url":null,"abstract":"A layout approach is attempted dedicatedly for MMICs (monolithic microwave integrated circuits), on which predominant layout elements are transistors, resistors, capacitors, inductors, coplanar waveguides, T junctions, etc., formed by the GaAs fabrication process. The layout issue typical of such MMICs consists essentially in how to realize a single layer placement of different shapes of layout elements under a variety of spacing, orientating, and shaping constraints. Each layout element is modeled to simplify placement tasks subject to different placement constraints, and then a set of the interconnection requirements among elements is represented by a graph, to which a planarization algorithm is effectively applied. As a result of this planarization, a placement procedure is constructed mainly by repeated application of a merging scheme. A number of experimental results are also shown to demonstrate the practicability of the described layout approach.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131122009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486266
T. Aoki, M. Murakata, T. Mitsuhashi, N. Goto
This paper proposes a fanout-tree restructuring algorithm for post-placement timing optimization to meet timing constraints. The proposed algorithm restructures a fanout-tree by finding a tree in a graph which represents a multi-terminal net, and inserts buffer cells and resizes cells based on an accurate interconnection RC delay without degrading routability. The algorithm has been implemented and applied to a number of layout data generated by timing driven placement. Application results show a 17% reduction in circuit delay on the average.
{"title":"Fanout-tree restructuring algorithm for post-placement timing optimization","authors":"T. Aoki, M. Murakata, T. Mitsuhashi, N. Goto","doi":"10.1109/ASPDAC.1995.486266","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486266","url":null,"abstract":"This paper proposes a fanout-tree restructuring algorithm for post-placement timing optimization to meet timing constraints. The proposed algorithm restructures a fanout-tree by finding a tree in a graph which represents a multi-terminal net, and inserts buffer cells and resizes cells based on an accurate interconnection RC delay without degrading routability. The algorithm has been implemented and applied to a number of layout data generated by timing driven placement. Application results show a 17% reduction in circuit delay on the average.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124951082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486195
S. Dhar, D.J. Gurney
CMOS circuits have significant amounts of dynamic short-circuit (or through) current. This can be as large as 20% of the total in well-designed circuits, and up to 80% of the total in circuits that have not been designed carefully. This current depends strongly on the relative sizes of the pull-up to pull-down paths. We introduce the dynamic short-circuit ratio to model this parameter. This allows accurate estimation of currents including the dynamic short-circuit current, and also results in improved delay estimation. Accuracy is typically within 10% of circuit-level simulation while operating at the switch-level abstraction.
{"title":"Current and charge estimation in CMOS circuits","authors":"S. Dhar, D.J. Gurney","doi":"10.1109/ASPDAC.1995.486195","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486195","url":null,"abstract":"CMOS circuits have significant amounts of dynamic short-circuit (or through) current. This can be as large as 20% of the total in well-designed circuits, and up to 80% of the total in circuits that have not been designed carefully. This current depends strongly on the relative sizes of the pull-up to pull-down paths. We introduce the dynamic short-circuit ratio to model this parameter. This allows accurate estimation of currents including the dynamic short-circuit current, and also results in improved delay estimation. Accuracy is typically within 10% of circuit-level simulation while operating at the switch-level abstraction.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131223265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486226
T. Damarla, Wei Su, G. T. Michael, M. Chung, C. Stroud
We present a novel approach for built-in self test (BIST) for VLSI. Many conventional BIST schemes use signatures generated by a linear feedback shift register (LFSR) or a multiple input signature register (MISR) for determining whether the device under test is faulty or fault free. In the approach presented, fault detection is made based on the number of different states the LFSR visits. This number is called the cycle length. It is also shown that such an approach results in the probability of aliasing of 2/sup -(2m-1+m/), where m denotes the number of registers in the LFSR, compared to 2/sup -m/ achieved by conventional signature analyzers. We also present the complexity of the additional hardware required to implement the scheme.
{"title":"A built-in self test scheme for VLSI","authors":"T. Damarla, Wei Su, G. T. Michael, M. Chung, C. Stroud","doi":"10.1109/ASPDAC.1995.486226","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486226","url":null,"abstract":"We present a novel approach for built-in self test (BIST) for VLSI. Many conventional BIST schemes use signatures generated by a linear feedback shift register (LFSR) or a multiple input signature register (MISR) for determining whether the device under test is faulty or fault free. In the approach presented, fault detection is made based on the number of different states the LFSR visits. This number is called the cycle length. It is also shown that such an approach results in the probability of aliasing of 2/sup -(2m-1+m/), where m denotes the number of registers in the LFSR, compared to 2/sup -m/ achieved by conventional signature analyzers. We also present the complexity of the additional hardware required to implement the scheme.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132394609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486360
M. Potkonjak, S. Dey, R. Roy
We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and partial scan cost than synthesis from the original specification. A two-stage objective function, that estimates the area and testability of the final implementation, and also captures enabling effects of the transformations, is developed. Optimization is done using a new randomized branch and bound steepest descent algorithm. Application of the transformation algorithm on several examples demonstrates significant simultaneous improvement in both area and testability of the final implementations.
{"title":"Synthesis-for-testability using transformations","authors":"M. Potkonjak, S. Dey, R. Roy","doi":"10.1109/ASPDAC.1995.486360","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486360","url":null,"abstract":"We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and partial scan cost than synthesis from the original specification. A two-stage objective function, that estimates the area and testability of the final implementation, and also captures enabling effects of the transformations, is developed. Optimization is done using a new randomized branch and bound steepest descent algorithm. Application of the transformation algorithm on several examples demonstrates significant simultaneous improvement in both area and testability of the final implementations.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130747359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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