Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188907
M. Andrade, J. Martino, M. Aoulaiche, N. Collaert, E. Simoen, C. Claeys
In this paper, the floating body effect used in one Transistor Floating Body Random Access Memory (1T-FBRAM) is experimentally investigated on Fully Depleted Ultra Thin Box Silicon On Insulator devices (FD UTBOX SOI). It is shown that using a positive back bias allows further scaling of 1T-FBRAM by increasing the current sense margin as well as the VG read window. Furthermore, the VD operating bias is reduced to the minimal drain voltage needed for impact ionization, which is beneficial for reliability.
{"title":"The impact of back bias on the floating body effect in UTBOX SOI devices for 1T-FBRAM memory applications","authors":"M. Andrade, J. Martino, M. Aoulaiche, N. Collaert, E. Simoen, C. Claeys","doi":"10.1109/ICCDCS.2012.6188907","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188907","url":null,"abstract":"In this paper, the floating body effect used in one Transistor Floating Body Random Access Memory (1T-FBRAM) is experimentally investigated on Fully Depleted Ultra Thin Box Silicon On Insulator devices (FD UTBOX SOI). It is shown that using a positive back bias allows further scaling of 1T-FBRAM by increasing the current sense margin as well as the VG read window. Furthermore, the VD operating bias is reduced to the minimal drain voltage needed for impact ionization, which is beneficial for reliability.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128464645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188879
T. M. Fraga, K. F. Albertin, I. Pereyra
The development of high sensitive miniaturized sensors is of special importance for "Lab on a Chip" and biosensors development. In this context and due to its n-type semiconductor character and its high chemical stability, TiO2 thin films have been proposed for application as pH and H sensors. Even more, taking advantage of their high specific surface, TiO2 nanotubes have been also considered as a natural candidate for application in pH detection.
{"title":"TiO2 nanotubes for application in sensors","authors":"T. M. Fraga, K. F. Albertin, I. Pereyra","doi":"10.1109/ICCDCS.2012.6188879","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188879","url":null,"abstract":"The development of high sensitive miniaturized sensors is of special importance for \"Lab on a Chip\" and biosensors development. In this context and due to its n-type semiconductor character and its high chemical stability, TiO2 thin films have been proposed for application as pH and H sensors. Even more, taking advantage of their high specific surface, TiO2 nanotubes have been also considered as a natural candidate for application in pH detection.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130906536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188909
B. González, J. Roldán, A. Roldán, B. Iñíguez, A. Lázaro, A. Cerdeira
An advanced drain current model for symmetrical Double-Gate MOSFETs (DGMOSFETs), including short channel, velocity saturation and self-heating effects, is presented. The temperature dependence of the low-field mobility, saturation velocity and inversion charge is analyzed and accurately included in the model. Self-heating is considered through the thermal resistance of the device, which is estimated in two ways: from an equivalent thermal circuit and from numerical output characteristic curves, obtained with a commercial TCAD tool (Sentaurus by Synopsys), and fitted with a drain current model. The validity of the model is checked by comparing with simulation results, for the typical bias range used in integrated circuits.
{"title":"An advanced drain current model for DGMOSFETs including self-heating effects","authors":"B. González, J. Roldán, A. Roldán, B. Iñíguez, A. Lázaro, A. Cerdeira","doi":"10.1109/ICCDCS.2012.6188909","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188909","url":null,"abstract":"An advanced drain current model for symmetrical Double-Gate MOSFETs (DGMOSFETs), including short channel, velocity saturation and self-heating effects, is presented. The temperature dependence of the low-field mobility, saturation velocity and inversion charge is analyzed and accurately included in the model. Self-heating is considered through the thermal resistance of the device, which is estimated in two ways: from an equivalent thermal circuit and from numerical output characteristic curves, obtained with a commercial TCAD tool (Sentaurus by Synopsys), and fitted with a drain current model. The validity of the model is checked by comparing with simulation results, for the typical bias range used in integrated circuits.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117092305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188949
G. Rehder, A. Serrano, F. S. Correra, M. Carrenõ
The use of MEMS as tuning elements is interesting for their higher performance in terms of loss and nonlinearity. Here, MEMS varactors are integrated to a patch filter through a flip-chip process in order to change the filter center frequency. The selected frequencies are the ones assigned to WiMAX frequency bands at 2.5 GHz and 3.5 GHz.
{"title":"Development of MEMS varactor for selectable-band patch filter","authors":"G. Rehder, A. Serrano, F. S. Correra, M. Carrenõ","doi":"10.1109/ICCDCS.2012.6188949","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188949","url":null,"abstract":"The use of MEMS as tuning elements is interesting for their higher performance in terms of loss and nonlinearity. Here, MEMS varactors are integrated to a patch filter through a flip-chip process in order to change the filter center frequency. The selected frequencies are the ones assigned to WiMAX frequency bands at 2.5 GHz and 3.5 GHz.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128065909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188901
R. Buhler, J. Martino, P. Agopian, R. Giacomini
This work analyzes the fin width dependence on induced uniaxial stress on n-type MuGFETs thought 3D simulations. A study on the stress distribution and the electric characterization of the device to measure the impact on its performance is accomplished. The stress distribution and the device performance exhibited dependence on the fin width, with higher stress transfer for narrower fins resulting in better electrical performance.
{"title":"Fin width influence on uniaxial stress of triple-gate SOI nMOSFETs","authors":"R. Buhler, J. Martino, P. Agopian, R. Giacomini","doi":"10.1109/ICCDCS.2012.6188901","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188901","url":null,"abstract":"This work analyzes the fin width dependence on induced uniaxial stress on n-type MuGFETs thought 3D simulations. A study on the stress distribution and the electric characterization of the device to measure the impact on its performance is accomplished. The stress distribution and the device performance exhibited dependence on the fin width, with higher stress transfer for narrower fins resulting in better electrical performance.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127172925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188886
J. Raskin
This last decade silicon-on-insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency (reaching cut-off frequencies close to 500 GHz for nMOSFETs) and for harsh environments (high temperature, radiation) commercial applications. SOI also presents high resistivity substrate capabilities, leading to substantially reduced substrate losses. SOI technology is also emerging as a major contender for heterogeneous microsystems applications. In this work, we demonstrate the advantages of SOI technology for RF CMOS integration as well as for building thin film sensors on thin dielectric membrane and three-dimensional microelectromechanical (MEMS) sensors and actuators co-integrated with their associated SOI CMOS circuitry.
{"title":"SOI substrates for More than Moore roadmap","authors":"J. Raskin","doi":"10.1109/ICCDCS.2012.6188886","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188886","url":null,"abstract":"This last decade silicon-on-insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency (reaching cut-off frequencies close to 500 GHz for nMOSFETs) and for harsh environments (high temperature, radiation) commercial applications. SOI also presents high resistivity substrate capabilities, leading to substantially reduced substrate losses. SOI technology is also emerging as a major contender for heterogeneous microsystems applications. In this work, we demonstrate the advantages of SOI technology for RF CMOS integration as well as for building thin film sensors on thin dielectric membrane and three-dimensional microelectromechanical (MEMS) sensors and actuators co-integrated with their associated SOI CMOS circuitry.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134101029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188878
R. Picos, E. Garcia, Miquel Roca, E. Isern, Benjamin Iniguez, A. Castro-Carranza, Magali Estrada, A. Cerdeira
In this paper we will analyze the feasibility of applying the well known IDDQ test technique to OTFT circuits. Specifically, we will analyze the implications of the leakage current, the Ion/Ioff ratio, and the S/N ratio on the applicability of IDDQ. It will be shown that, even if the IDDQ is applicable, some adaptation must be made, to allow detecting the possible faults over the background level. These adaptations may probably take the form of partitioning strategies, which must be adapted to the actual technology.
{"title":"Considerations on IDDQ test on OTFT circuits","authors":"R. Picos, E. Garcia, Miquel Roca, E. Isern, Benjamin Iniguez, A. Castro-Carranza, Magali Estrada, A. Cerdeira","doi":"10.1109/ICCDCS.2012.6188878","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188878","url":null,"abstract":"In this paper we will analyze the feasibility of applying the well known IDDQ test technique to OTFT circuits. Specifically, we will analyze the implications of the leakage current, the Ion/Ioff ratio, and the S/N ratio on the applicability of IDDQ. It will be shown that, even if the IDDQ is applicable, some adaptation must be made, to allow detecting the possible faults over the background level. These adaptations may probably take the form of partitioning strategies, which must be adapted to the actual technology.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129533698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6241466
P. Chaturvedi, N. Goyal
Gate leakage is one of the important parameter expected to limit the performance of Tunnel FETs. We have simulated the effect of gate dielectric thickness on gate leakage in Tunnel FETs, using two dimensional numerical simulations. It has been observed that gate leakage considerably affects the subthreshold characteristics of TFETs. It was found to be most important component of off-state current and should be considered in future TFET device design. Effects of gate metal workfunction on device characteristics, particularly, gate leakage and origin of reverse tunneling at drain have also been discussed.
{"title":"Effect of gate dielectric thickness on gate leakage in tunnel field effect transistor","authors":"P. Chaturvedi, N. Goyal","doi":"10.1109/ICCDCS.2012.6241466","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6241466","url":null,"abstract":"Gate leakage is one of the important parameter expected to limit the performance of Tunnel FETs. We have simulated the effect of gate dielectric thickness on gate leakage in Tunnel FETs, using two dimensional numerical simulations. It has been observed that gate leakage considerably affects the subthreshold characteristics of TFETs. It was found to be most important component of off-state current and should be considered in future TFET device design. Effects of gate metal workfunction on device characteristics, particularly, gate leakage and origin of reverse tunneling at drain have also been discussed.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121763776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188922
L. T. Da Silva, M. Evaldt, L. L. Pfitscher
Metallic equipment and objects require special attention for identification in a Radio Frequency Identification (RFID) system, due to their interference negative effects. This paper presents an application of ultra-high frequency RFID in a gateway configuration, used to identify metallic equipment. The main purpose of the proposed system is to identify items with metallic content and regardless of their position when passing through the gateway. The UHF (Ultra High Frequency) RFID technology with passive tagging was implemented. Different tagging configurations were tested and results for each configuration are presented.
{"title":"Ultra high frequency RFID gateway system for identification of metallic equipment","authors":"L. T. Da Silva, M. Evaldt, L. L. Pfitscher","doi":"10.1109/ICCDCS.2012.6188922","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188922","url":null,"abstract":"Metallic equipment and objects require special attention for identification in a Radio Frequency Identification (RFID) system, due to their interference negative effects. This paper presents an application of ultra-high frequency RFID in a gateway configuration, used to identify metallic equipment. The main purpose of the proposed system is to identify items with metallic content and regardless of their position when passing through the gateway. The UHF (Ultra High Frequency) RFID technology with passive tagging was implemented. Different tagging configurations were tested and results for each configuration are presented.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114707850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188884
D. Flandre, O. Bulteel, G. Gosset, B. Rue, D. Bol
In this paper, we describe circuits and microsystems applications of a disruptive ultra-low-leakage design technique for drastically reducing the off current in CMOS analog and digital functions without reducing the functional performance. The technique uses a pair of source-connected n- and p-MOSFETs, implementing an auto-bias of the stand-by gate-to-source voltage of the nMOS transistor at a negative voltage and that of the p-device at a positive level, thereby reducing the off current towards its physical limits. Changing the gate and drain connections, we propose a series of ultra-low-power basic blocks : a 2-terminal diode, a 3-terminal transistor and a voltage follower. These blocks can be combined to yield a 7-transistor SRAM cell and an MTCMOS latch with record low stand-by leakage but still high-speed performance, as well as high-efficiency power-management units for RF and PV energy harvesting and a microwatt interface for implanted capacitive sensors.
{"title":"Ultra-low-power analog and digital circuits and microsystems using disruptive ultra-low-leakage design techniques","authors":"D. Flandre, O. Bulteel, G. Gosset, B. Rue, D. Bol","doi":"10.1109/ICCDCS.2012.6188884","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188884","url":null,"abstract":"In this paper, we describe circuits and microsystems applications of a disruptive ultra-low-leakage design technique for drastically reducing the off current in CMOS analog and digital functions without reducing the functional performance. The technique uses a pair of source-connected n- and p-MOSFETs, implementing an auto-bias of the stand-by gate-to-source voltage of the nMOS transistor at a negative voltage and that of the p-device at a positive level, thereby reducing the off current towards its physical limits. Changing the gate and drain connections, we propose a series of ultra-low-power basic blocks : a 2-terminal diode, a 3-terminal transistor and a voltage follower. These blocks can be combined to yield a 7-transistor SRAM cell and an MTCMOS latch with record low stand-by leakage but still high-speed performance, as well as high-efficiency power-management units for RF and PV energy harvesting and a microwatt interface for implanted capacitive sensors.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114310626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：