Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188898
E. Contreras, A. Cerdeira, M. Pavanello
In this paper we present a methodology to use the Symmetric Doped Double-Gate Model implemented in Verilog-A to simulate analog circuits with FinFET Technology. A Miller operational Amplifier was simulated in SPICE simulator and the results were validated comparing them with experimental data published in previous works.
{"title":"Simulation of miller OpAmp analog circuit with FinFET transistors","authors":"E. Contreras, A. Cerdeira, M. Pavanello","doi":"10.1109/ICCDCS.2012.6188898","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188898","url":null,"abstract":"In this paper we present a methodology to use the Symmetric Doped Double-Gate Model implemented in Verilog-A to simulate analog circuits with FinFET Technology. A Miller operational Amplifier was simulated in SPICE simulator and the results were validated comparing them with experimental data published in previous works.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132867999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188911
U. Zschieschang, H. Klauk, T. Sekitani, T. Someya, M. Kang, K. Takimiya, T. Canzler, A. Werner, J. Blochwitz-Nimoth
Using the recently developed organic semiconductor C10-DNTT and a thin, high-capacitance gate dielectric we have fabricated flexible organic thin-film transistors that combine a field-effect mobility of 4.3 cm2/Vs, an on/off ratio of 108, and a subthreshold swing of 68 mV/decade. To improve the charge exchange between the organic semiconductor layer and the metal source and drain contacts, a thin layer of a non-alkylated organic semiconductor (DNTT) sandwiched between two thin layers of a strong organic dopant (NDP-9) were inserted between the C10-DNTT and the metal contacts. Flexible ring oscillators have a signal propagation delay of 5 μsec per stage at a supply voltage of 3 V.
{"title":"Performance and stability of flexible low-voltage organic thin-film transistors based on C10-DNTT","authors":"U. Zschieschang, H. Klauk, T. Sekitani, T. Someya, M. Kang, K. Takimiya, T. Canzler, A. Werner, J. Blochwitz-Nimoth","doi":"10.1109/ICCDCS.2012.6188911","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188911","url":null,"abstract":"Using the recently developed organic semiconductor C10-DNTT and a thin, high-capacitance gate dielectric we have fabricated flexible organic thin-film transistors that combine a field-effect mobility of 4.3 cm2/Vs, an on/off ratio of 108, and a subthreshold swing of 68 mV/decade. To improve the charge exchange between the organic semiconductor layer and the metal source and drain contacts, a thin layer of a non-alkylated organic semiconductor (DNTT) sandwiched between two thin layers of a strong organic dopant (NDP-9) were inserted between the C10-DNTT and the metal contacts. Flexible ring oscillators have a signal propagation delay of 5 μsec per stage at a supply voltage of 3 V.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121133893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188931
T. Fjeldly, U. Monga, S. Vishvakarma
A compact analytical model is presented for the 3D electrostatics of nanoscale gate-all-around MOSFET with a square and rectangular cross sections perpendicular to the source-drain axis. The model is based on solutions of the 3D Laplace equation (subthreshold) and Poisson's equation (above threshold), where suitable 2D isomorphic modeling functions are utilized to describe the potential distribution in the cross sections. From this, the device capacitances and the drain current can be calculated in the full range of bias voltages. The model compares well with numerical calculations obtained from the ATLAS device simulator. This model can be readily extended to include double gate and trigate MOSFETS and FinFETs.
{"title":"Compact unified modeling of multigate MOSFETs based on isomorphic modeling functions","authors":"T. Fjeldly, U. Monga, S. Vishvakarma","doi":"10.1109/ICCDCS.2012.6188931","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188931","url":null,"abstract":"A compact analytical model is presented for the 3D electrostatics of nanoscale gate-all-around MOSFET with a square and rectangular cross sections perpendicular to the source-drain axis. The model is based on solutions of the 3D Laplace equation (subthreshold) and Poisson's equation (above threshold), where suitable 2D isomorphic modeling functions are utilized to describe the potential distribution in the cross sections. From this, the device capacitances and the drain current can be calculated in the full range of bias voltages. The model compares well with numerical calculations obtained from the ATLAS device simulator. This model can be readily extended to include double gate and trigate MOSFETS and FinFETs.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"92 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114032495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188913
A. A. Palma-Rodriguez, Esteban Tlelo-Cuautle, S. Rodriguez-Chavez, Sheldon X.-D. Tan
Sensitivity analysis helps circuit designers to determine boundaries to predict the variations that a particular design variable will generate in a target specification, if it differs from what is previously assumed. It is quite important in designing active filters, but the major drawback is the need of generating the symbolic transfer function, from which the normalized sensitivity formula is usually applied. In this paper we show the usefulness of applying determinant decision diagrams (DDDs), to compute sensitivities without generating the symbolic transfer function, previously. Basically, we propose replacing all symbols in the DDD graph by their numerical values, except one, i.e. the variable of interest. Therefore, all sensitivities are computed by applying Cramer's rule and by constructing one DDD for each symbol. We demonstrate the computing time gain compared to generating the fully symbolic transfer function and then applying the normalized sensitivity formula.
{"title":"DDD-based symbolic sensitivity analysis of active filters","authors":"A. A. Palma-Rodriguez, Esteban Tlelo-Cuautle, S. Rodriguez-Chavez, Sheldon X.-D. Tan","doi":"10.1109/ICCDCS.2012.6188913","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188913","url":null,"abstract":"Sensitivity analysis helps circuit designers to determine boundaries to predict the variations that a particular design variable will generate in a target specification, if it differs from what is previously assumed. It is quite important in designing active filters, but the major drawback is the need of generating the symbolic transfer function, from which the normalized sensitivity formula is usually applied. In this paper we show the usefulness of applying determinant decision diagrams (DDDs), to compute sensitivities without generating the symbolic transfer function, previously. Basically, we propose replacing all symbols in the DDD graph by their numerical values, except one, i.e. the variable of interest. Therefore, all sensitivities are computed by applying Cramer's rule and by constructing one DDD for each symbol. We demonstrate the computing time gain compared to generating the fully symbolic transfer function and then applying the normalized sensitivity formula.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133271412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188932
M. de Souza, M. Pavanello, D. Flandre
This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric self-cascode.
{"title":"Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors","authors":"M. de Souza, M. Pavanello, D. Flandre","doi":"10.1109/ICCDCS.2012.6188932","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188932","url":null,"abstract":"This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric self-cascode.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134416798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188918
Chu-Hsiang Chia, Pui-Sun Lei, R. Chang, Pei-Wei Ko
This paper presents a multi-channel LED driver with PFM control which channels are independent of the LED numbers. Every channel can have almost the same driving current under different LED numbers. The current error is only 0.054% that is better than the previous design. It is designed by using TSMC 0.35μm 3.3V/5V CMOS technology. The proposed driver with the novel current balance circuit can have 15.6V output voltage and the maximum loading is 150mA.
{"title":"A multi-channel LED driver with accurate current control and adjustable LED numbers","authors":"Chu-Hsiang Chia, Pui-Sun Lei, R. Chang, Pei-Wei Ko","doi":"10.1109/ICCDCS.2012.6188918","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188918","url":null,"abstract":"This paper presents a multi-channel LED driver with PFM control which channels are independent of the LED numbers. Every channel can have almost the same driving current under different LED numbers. The current error is only 0.054% that is better than the previous design. It is designed by using TSMC 0.35μm 3.3V/5V CMOS technology. The proposed driver with the novel current balance circuit can have 15.6V output voltage and the maximum loading is 150mA.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124628206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188904
E. Santana, Raimundo C. S. Freire, Ana Isabela Araújo Cunha
This work presents a new architecture of analog four-quadrant multiplier in CMOS technology based on the behavior of MOSFET in the linear region from weak to strong inversion. The proposed multiplier has voltage and current inputs and a current output, thus being adequate for the implementation of compact synapses in analog Cellular Neural Network (CNN). Simulation results exhibit low power consumption and low distortion.
{"title":"A CMOS analog four-quadrant multiplier for CNN synapses","authors":"E. Santana, Raimundo C. S. Freire, Ana Isabela Araújo Cunha","doi":"10.1109/ICCDCS.2012.6188904","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188904","url":null,"abstract":"This work presents a new architecture of analog four-quadrant multiplier in CMOS technology based on the behavior of MOSFET in the linear region from weak to strong inversion. The proposed multiplier has voltage and current inputs and a current output, thus being adequate for the implementation of compact synapses in analog Cellular Neural Network (CNN). Simulation results exhibit low power consumption and low distortion.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122506585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188897
H. Vilchis, V. M. Sanchez-R, A. Escobosa
In this work the characterization of cubic GaN epitaxial films on templates obtained by nitridation of GaAs is reported. N- or p-type materials were obtained in Undoped or Mg-doped films respectively. The use of Mg compounds results in a tendency to incorporate the hexagonal phase in the films, but this effect can be avoided adjusting the experimental parameters. The results show that the materials can be suitable to the realization of optoelectronic devices.
{"title":"Structural studies of cubic GaN films grown by MOCVD","authors":"H. Vilchis, V. M. Sanchez-R, A. Escobosa","doi":"10.1109/ICCDCS.2012.6188897","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188897","url":null,"abstract":"In this work the characterization of cubic GaN epitaxial films on templates obtained by nitridation of GaAs is reported. N- or p-type materials were obtained in Undoped or Mg-doped films respectively. The use of Mg compounds results in a tendency to incorporate the hexagonal phase in the films, but this effect can be avoided adjusting the experimental parameters. The results show that the materials can be suitable to the realization of optoelectronic devices.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121349321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188920
J. Salcedo, D. Clarke, J. Hajjar
On-chip protection architecture for automotive ICs (integrated circuits) system-level robustness is introduced. It comprises three-level protection for interface pins with high bidirectional voltage swing. A first protection stage is optimized to sustain the largest portion of the ESD (electrostatic discharge) and EMI (electromagnetic interference)-induced stress. A second-level protection stage is customized to sustain the relatively lower IC-level ESD stress, and the third level protection stage absorbs the initial transient voltage impulse.
{"title":"On-chip protection for automotive integrated circuits robustness","authors":"J. Salcedo, D. Clarke, J. Hajjar","doi":"10.1109/ICCDCS.2012.6188920","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188920","url":null,"abstract":"On-chip protection architecture for automotive ICs (integrated circuits) system-level robustness is introduced. It comprises three-level protection for interface pins with high bidirectional voltage swing. A first protection stage is optimized to sustain the largest portion of the ESD (electrostatic discharge) and EMI (electromagnetic interference)-induced stress. A second-level protection stage is customized to sustain the relatively lower IC-level ESD stress, and the third level protection stage absorbs the initial transient voltage impulse.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"PP 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131062782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188935
S. Khandelwal, Y. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad, C. Hu
We present an efficient approach to model the effects of vertical non-uniform doping in bulk MOSFETs. The impact of vertical non-uniform doping on device characteristics is analyzed through systematic TCAD simulations. The qualitative nature of the observed effects is also confirmed by the experimental data available in the literature. A modeling methodology for these effects is developed on BSIM6 model framework. The proposed model is in good agreement with the TCAD simulations.
{"title":"Analysis and modeling of vertical non-uniform doping in bulk MOSFETs for circuit simulation","authors":"S. Khandelwal, Y. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad, C. Hu","doi":"10.1109/ICCDCS.2012.6188935","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188935","url":null,"abstract":"We present an efficient approach to model the effects of vertical non-uniform doping in bulk MOSFETs. The impact of vertical non-uniform doping on device characteristics is analyzed through systematic TCAD simulations. The qualitative nature of the observed effects is also confirmed by the experimental data available in the literature. A modeling methodology for these effects is developed on BSIM6 model framework. The proposed model is in good agreement with the TCAD simulations.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132215308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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