Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188917
M. Avila, F. Ulloa, J. Sánchez, M. Estrada
In this paper, we characterize MIS structures and PTFTs made with blends of P3HT:F8T2 as active layer and PMMA as dielectric. The properties of the interface between the dielectric and the active layer are analyzed using CV curves and compared to those obtained for P3HT and F8T2 as active layer. Mobility and its dependence with gate voltage, the distribution of states DOS in the active layer of the PTFTs and other device parameters were obtained and analyzed. It was found that the characteristic temperature of the distribution of States, DOS in P3HT is the lowest, increasing slightly for the blend, but quite significant in F8T2 PTFTs, while the density of localized states is highest for the blend. Mobility resulted lower than for P3HT devices, but higher than for F8T2. The interface density of states also increases.
{"title":"PTFTs with blends of P3HT:F8T2","authors":"M. Avila, F. Ulloa, J. Sánchez, M. Estrada","doi":"10.1109/ICCDCS.2012.6188917","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188917","url":null,"abstract":"In this paper, we characterize MIS structures and PTFTs made with blends of P3HT:F8T2 as active layer and PMMA as dielectric. The properties of the interface between the dielectric and the active layer are analyzed using CV curves and compared to those obtained for P3HT and F8T2 as active layer. Mobility and its dependence with gate voltage, the distribution of states DOS in the active layer of the PTFTs and other device parameters were obtained and analyzed. It was found that the characteristic temperature of the distribution of States, DOS in P3HT is the lowest, increasing slightly for the blend, but quite significant in F8T2 PTFTs, while the density of localized states is highest for the blend. Mobility resulted lower than for P3HT devices, but higher than for F8T2. The interface density of states also increases.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125172994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188912
S. Rodriguez-Chavez, E. Tlelo-Cuautle, A. A. Palma-Rodriguez, S. Tan
In this paper we present a tool based on determinant decision diagrams (DDDs) for the automatic generation of exact fully-symbolic noise expressions of analog integrated circuits containing MOSFETs. The formulation of the circuit equations is performed through modeling all MOSFETs with their nullor equivalents and by applying symbolic nodal analysis. The derived exact fully-symbolic noise expressions are evaluated from HSPICE™ simulations using the related noise equations for NLEV 0, 1 and 2. We show the good agreement between the derived symbolic-expressions and HSPICE™. Another advantage of our proposed DDD-based tool relies on its capability to compute the voltage noise generated at each circuit node, and in a simple post-processing step it can compute the current noise at each circuit branch.
{"title":"Symbolic DDD-based tool for the computation of noise in CMOS analog circuits","authors":"S. Rodriguez-Chavez, E. Tlelo-Cuautle, A. A. Palma-Rodriguez, S. Tan","doi":"10.1109/ICCDCS.2012.6188912","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188912","url":null,"abstract":"In this paper we present a tool based on determinant decision diagrams (DDDs) for the automatic generation of exact fully-symbolic noise expressions of analog integrated circuits containing MOSFETs. The formulation of the circuit equations is performed through modeling all MOSFETs with their nullor equivalents and by applying symbolic nodal analysis. The derived exact fully-symbolic noise expressions are evaluated from HSPICE™ simulations using the related noise equations for NLEV 0, 1 and 2. We show the good agreement between the derived symbolic-expressions and HSPICE™. Another advantage of our proposed DDD-based tool relies on its capability to compute the voltage noise generated at each circuit node, and in a simple post-processing step it can compute the current noise at each circuit branch.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127870504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188929
M. A. S. de Saouza, R. T. Doria, M. Pavanello, C. Claeys, E. Simoen
This work presents a study of the influence of mechanical stress on the low frequency noise in planar SOI transistors operating in saturation. Several channel lengths were measured, and the results show a reduction of the low frequency noise for strained devices independent of the channel length, and this reduction is more effective for smaller channel lengths.
{"title":"Uniaxial mechanical stress influence on the low frequency noise in FD SOI nMOSFETs operating in saturation","authors":"M. A. S. de Saouza, R. T. Doria, M. Pavanello, C. Claeys, E. Simoen","doi":"10.1109/ICCDCS.2012.6188929","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188929","url":null,"abstract":"This work presents a study of the influence of mechanical stress on the low frequency noise in planar SOI transistors operating in saturation. Several channel lengths were measured, and the results show a reduction of the low frequency noise for strained devices independent of the channel length, and this reduction is more effective for smaller channel lengths.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120998619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188927
F. Aldana, A. Zenteno, D. R. Mendavil, G. Regalado
The design of a ball grid array metalized particle interconnect (BGA MPI) socket is presented. A novel design using static force system using less force and components instead of a dynamic one is shown. The performance of MPI socket has been characterized mechanically as deformation value and electrically as S parameters for different compression force. The MPI has been validated at laboratory using continuity, resistance and validation test. All of tests successfully passed which probed the socket design.
{"title":"BGA MPI socket analysis and validation","authors":"F. Aldana, A. Zenteno, D. R. Mendavil, G. Regalado","doi":"10.1109/ICCDCS.2012.6188927","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188927","url":null,"abstract":"The design of a ball grid array metalized particle interconnect (BGA MPI) socket is presented. A novel design using static force system using less force and components instead of a dynamic one is shown. The performance of MPI socket has been characterized mechanically as deformation value and electrically as S parameters for different compression force. The MPI has been validated at laboratory using continuity, resistance and validation test. All of tests successfully passed which probed the socket design.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127341410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188933
G. Hernández‐Sosa, A. Sánchez
This paper introduces an analytical method for calculating the equivalent inductance associated to signal vias in parallel planes with arbitrary power/ground (P/G) via distribution. The proposal is corroborated by comparing the equivalent inductances predicted by a commercial electromagnetic solver (HFSS) and those predicted by the analytical method. Excellent results are obtained demonstrating the accuracy and validity of the proposal.
{"title":"Analytical calculation of the equivalent inductance for signal vias in parallel planes with arbitrary P/G via distribution","authors":"G. Hernández‐Sosa, A. Sánchez","doi":"10.1109/ICCDCS.2012.6188933","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188933","url":null,"abstract":"This paper introduces an analytical method for calculating the equivalent inductance associated to signal vias in parallel planes with arbitrary power/ground (P/G) via distribution. The proposal is corroborated by comparing the equivalent inductances predicted by a commercial electromagnetic solver (HFSS) and those predicted by the analytical method. Excellent results are obtained demonstrating the accuracy and validity of the proposal.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"251 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114488742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188889
C. Claeys, A. Firrincieli, K. Martens, J. Kittl, E. Simoen
For sub 22 nm technologies the use of both Ge and III-V based devices is extensively investigated because of their promising electrical performances. However, for both types of devices it is of utmost importance to achieve ohmic contacts with a low specific contact resistivity in the order of 1×10-8 Ωcm2 or below. This paper reviews some basic aspects and recent insights in contact technology schemes for both Ge and III-V based technologies.
{"title":"Contact technology schemes for advanced Ge and III-V CMOS technologies","authors":"C. Claeys, A. Firrincieli, K. Martens, J. Kittl, E. Simoen","doi":"10.1109/ICCDCS.2012.6188889","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188889","url":null,"abstract":"For sub 22 nm technologies the use of both Ge and III-V based devices is extensively investigated because of their promising electrical performances. However, for both types of devices it is of utmost importance to achieve ohmic contacts with a low specific contact resistivity in the order of 1×10-8 Ωcm2 or below. This paper reviews some basic aspects and recent insights in contact technology schemes for both Ge and III-V based technologies.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117194140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188903
K. Sasaki, L. Almeida, J. Martino, M. Aoulaiche, E. Simoen, C. Claeys
This paper investigates the temperature influence on Ultra Thin Buried Oxide (UTBOX) FDSOI devices used as a 1T-DRAM (single transistor dynamic random access memory cell) using GIDL (Gate Induced Drain Leakage) for writing operation through numerical simulations. At higher temperatures, it is observed that the memory window varies and the retention time is degraded, when using a standard read. To solve this issue, we suggest the ZTC read, which fixes the state-0 current independently of the temperature. Moreover, considering I0 current as a reference current for the memory cell operation results in improved retention time.
{"title":"Temperature influence on UTBOX 1T-DRAM using GIDL for writing operation","authors":"K. Sasaki, L. Almeida, J. Martino, M. Aoulaiche, E. Simoen, C. Claeys","doi":"10.1109/ICCDCS.2012.6188903","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188903","url":null,"abstract":"This paper investigates the temperature influence on Ultra Thin Buried Oxide (UTBOX) FDSOI devices used as a 1T-DRAM (single transistor dynamic random access memory cell) using GIDL (Gate Induced Drain Leakage) for writing operation through numerical simulations. At higher temperatures, it is observed that the memory window varies and the retention time is degraded, when using a standard read. To solve this issue, we suggest the ZTC read, which fixes the state-0 current independently of the temperature. Moreover, considering I0 current as a reference current for the memory cell operation results in improved retention time.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123495268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188923
W. A. Amaral, F. Castro, S. T. Coelho, M. Goes, C. O. Hamanaka, I. C. S. Junior, J. L. E. Júnior, W. B. Moraes, M. D. Pereira, R. L. O. Pinto, A. F. Ponchet, E. A. C. Sanchez, J. C. Silva, L. H. Spiller, A. Ximenes, S. D. Yamamoto, R. Lima, V. L. Sobral
A transceiver design will be presented in the following items. The circuit will be used in a wireless sensor network for precision irrigation in agriculture. The transceiver was designed to operate in the license - free ISM band of 2.4GHz. A complete top-down methodology was used, improving the coverage of the system functional verification. The design was made using XFAB 0.18um CMOS technology.
{"title":"A 2.4GHz transceiver for wireless sensor network","authors":"W. A. Amaral, F. Castro, S. T. Coelho, M. Goes, C. O. Hamanaka, I. C. S. Junior, J. L. E. Júnior, W. B. Moraes, M. D. Pereira, R. L. O. Pinto, A. F. Ponchet, E. A. C. Sanchez, J. C. Silva, L. H. Spiller, A. Ximenes, S. D. Yamamoto, R. Lima, V. L. Sobral","doi":"10.1109/ICCDCS.2012.6188923","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188923","url":null,"abstract":"A transceiver design will be presented in the following items. The circuit will be used in a wireless sensor network for precision irrigation in agriculture. The transceiver was designed to operate in the license - free ISM band of 2.4GHz. A complete top-down methodology was used, improving the coverage of the system functional verification. The design was made using XFAB 0.18um CMOS technology.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128926557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188916
J. Tejada, A. L. Rodriguez, A. Godoy, S. Rodríguez-Bolívar, J. Villanueva, O. Marinov, M. Deen
The effects of different parameters on the DC and low-frequency noise performance of four gate field effect transistors (G4-FET) are studied. Experimental data of the drain current and the current noise power spectral density (PSD) are compared with simulation results. The comparisons show that the drain current and its associated noise are very sensitive to the doping profile of the pn junctions that constitute the lateral gates of the device. The presence of recombination centers also modifies the performance of the device. These centers can degrade the excellent subthreshold slope that the G4-FET transistor exhibits. At the same time, the generation-recombination (g-r) noise produced by deep traps in the depletion regions of the device can be reduced by the presence of these recombination centers. In this work, we propose a procedure to determine an optimal dopant profile of the lateral pn junctions of the device that minimizes the subthreshold slope and the low frequency noise and maximizes the transconductance.
{"title":"DC and low-frequency noise optimization of four-gate transistors","authors":"J. Tejada, A. L. Rodriguez, A. Godoy, S. Rodríguez-Bolívar, J. Villanueva, O. Marinov, M. Deen","doi":"10.1109/ICCDCS.2012.6188916","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188916","url":null,"abstract":"The effects of different parameters on the DC and low-frequency noise performance of four gate field effect transistors (G4-FET) are studied. Experimental data of the drain current and the current noise power spectral density (PSD) are compared with simulation results. The comparisons show that the drain current and its associated noise are very sensitive to the doping profile of the pn junctions that constitute the lateral gates of the device. The presence of recombination centers also modifies the performance of the device. These centers can degrade the excellent subthreshold slope that the G4-FET transistor exhibits. At the same time, the generation-recombination (g-r) noise produced by deep traps in the depletion regions of the device can be reduced by the presence of these recombination centers. In this work, we propose a procedure to determine an optimal dopant profile of the lateral pn junctions of the device that minimizes the subthreshold slope and the low frequency noise and maximizes the transconductance.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127139000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188880
M. Cheralathan, Sungjae Chang, M. Bawedin, Burhan Bayraktaroglu, J.-H. Lee, Benjamin Iñiguez, S. Cristoloveanu
ZnO device technology provides numerous possible TFT applications. This paper investigates the transport properties in thin nanocrystalline ZnO films. Since these devices are bottom-gate controlled, their characteristics reveal the properties of the back channel located at the interface. Guided by systematic experimental results, we focus on analytical models matching the mobility behavior in ZnO TFTs. The gate leakage and subthreshold leakage currents are much lower than the drain current in inversion, where the mobility model holds. We present appropriate parameter extraction methods for two particular mobility models. A good agreement is obtained between the low temperature measurements and the models proposed.
{"title":"Mobility models for ZnO TFTs","authors":"M. Cheralathan, Sungjae Chang, M. Bawedin, Burhan Bayraktaroglu, J.-H. Lee, Benjamin Iñiguez, S. Cristoloveanu","doi":"10.1109/ICCDCS.2012.6188880","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188880","url":null,"abstract":"ZnO device technology provides numerous possible TFT applications. This paper investigates the transport properties in thin nanocrystalline ZnO films. Since these devices are bottom-gate controlled, their characteristics reveal the properties of the back channel located at the interface. Guided by systematic experimental results, we focus on analytical models matching the mobility behavior in ZnO TFTs. The gate leakage and subthreshold leakage currents are much lower than the drain current in inversion, where the mobility model holds. We present appropriate parameter extraction methods for two particular mobility models. A good agreement is obtained between the low temperature measurements and the models proposed.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127432405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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