Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188942
C. Ramirez-Perez, R. M. Ramos
Next generation networks will offer services with the best quality of service (QoS) providing the users with a feeling of permanent connectivity. To that end, it is crucial to integrate heterogeneous networks so as to provide collective services. Vertical handoff consists in handing off the traffic flows of applications running on a mobile device through heterogeneous networks in order to keep or improve the QoS. In this work, we propose an algorithm for decision making in vertical handoff which considers three active applications running on a mobile device. The selectivity of our algorithm can be adjusted as a function of a set of QoS requirements e.g., the minimal bit rate, delay, jitter, and packet error rate (PER) as well as the user preferences. We show by extensive simulations that the algorithm we propose gets a significant improvement in QoS, while at the same time obtains a more efficient use of resources.
{"title":"A QoS hierarchical decision scheme for vertical handoff","authors":"C. Ramirez-Perez, R. M. Ramos","doi":"10.1109/ICCDCS.2012.6188942","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188942","url":null,"abstract":"Next generation networks will offer services with the best quality of service (QoS) providing the users with a feeling of permanent connectivity. To that end, it is crucial to integrate heterogeneous networks so as to provide collective services. Vertical handoff consists in handing off the traffic flows of applications running on a mobile device through heterogeneous networks in order to keep or improve the QoS. In this work, we propose an algorithm for decision making in vertical handoff which considers three active applications running on a mobile device. The selectivity of our algorithm can be adjusted as a function of a set of QoS requirements e.g., the minimal bit rate, delay, jitter, and packet error rate (PER) as well as the user preferences. We show by extensive simulations that the algorithm we propose gets a significant improvement in QoS, while at the same time obtains a more efficient use of resources.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121669928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188893
O. Filio, S. Primak, V. Kontorovich
In this paper a new and original approach for power allocation for cognitive users is proposed. The approach is based on the application of the order statistics (maximum terms of the variation series) for instantaneous SNR levels. Contrary to the widely applied methods, in the proposed approach, power is allocated to the groups of the OFDM sub-carriers which suffer the same flat fading. It is shown by means of an example how results of this method can be compared with the sub-optimum results of the nonlinear programming presented before.
{"title":"Power allocation for cognitive users applying OFDM under dynamic spectrum activity","authors":"O. Filio, S. Primak, V. Kontorovich","doi":"10.1109/ICCDCS.2012.6188893","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188893","url":null,"abstract":"In this paper a new and original approach for power allocation for cognitive users is proposed. The approach is based on the application of the order statistics (maximum terms of the variation series) for instantaneous SNR levels. Contrary to the widely applied methods, in the proposed approach, power is allocated to the groups of the OFDM sub-carriers which suffer the same flat fading. It is shown by means of an example how results of this method can be compared with the sub-optimum results of the nonlinear programming presented before.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115797774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188945
C. Malheiro, A. S. N. Pereira, R. Giacomini
The FinFET spreading resistance is the component of the parasitic resistance of FinFETs caused by the curved shape of the current lines in drain and source regions, close to the junctions. This work proposes a very simple analytical model for the spreading resistance of Double-Gate FinFETs that is valid for any fin width from 16nm, without fitting parameters. The model output was compared to data extracted from numeric simulation and it showed accuracy better than 8% for the considered range of devices with three different doping concentrations.
{"title":"An analytical estimation model for the spreading resistance of Double-Gate FinFETs","authors":"C. Malheiro, A. S. N. Pereira, R. Giacomini","doi":"10.1109/ICCDCS.2012.6188945","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188945","url":null,"abstract":"The FinFET spreading resistance is the component of the parasitic resistance of FinFETs caused by the curved shape of the current lines in drain and source regions, close to the junctions. This work proposes a very simple analytical model for the spreading resistance of Double-Gate FinFETs that is valid for any fin width from 16nm, without fitting parameters. The model output was compared to data extracted from numeric simulation and it showed accuracy better than 8% for the considered range of devices with three different doping concentrations.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127855817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188930
J. Nemer, M. de Souza, M. Pavanello, D. Flandre
This paper aims to demonstrate the performance of GC SOI MOSFET devices in comparison to standard SOI MOS transistors, comparing the improvements achieved by the adoption of the GC architecture in a submicron fully depleted SOI technology varying the channel length. The results obtained by two-dimensional numerical simulations show that the best improvement is obtained when the length of lightly doped region length is approximately 100 nm, independently of the total channel length.
本文旨在展示GC SOI MOSFET器件与标准SOI MOS晶体管的性能，比较采用GC架构在亚微米完全耗尽SOI技术中改变通道长度所取得的改进。二维数值模拟结果表明，当轻掺杂区域长度约为100 nm时，与通道总长度无关，改善效果最好。
{"title":"Analog performance of submicron GC SOI MOSFETs","authors":"J. Nemer, M. de Souza, M. Pavanello, D. Flandre","doi":"10.1109/ICCDCS.2012.6188930","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188930","url":null,"abstract":"This paper aims to demonstrate the performance of GC SOI MOSFET devices in comparison to standard SOI MOS transistors, comparing the improvements achieved by the adoption of the GC architecture in a submicron fully depleted SOI technology varying the channel length. The results obtained by two-dimensional numerical simulations show that the best improvement is obtained when the length of lightly doped region length is approximately 100 nm, independently of the total channel length.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132042312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188896
M. Galeti, M. Rodrigues, J. Martino, N. Collaert, E. Simoen, M. Aoulaiche, C. Claeys
This work characterizes the analog performance of SOI n-MuGFETs with different source/drain configurations. Devices without source/drain extension lead to a larger intrinsic voltage gain, even with the reduced transconductance, due to the increased Early voltage. At the same time, they showed a degradation of the interface quality with a larger low-frequency noise and reduced linearity. On the other hand, they can achieve reduced GIDL current due to the suppressed vertical electric field.
{"title":"Analog parameters of MuGFET devices with different source/drain engineering","authors":"M. Galeti, M. Rodrigues, J. Martino, N. Collaert, E. Simoen, M. Aoulaiche, C. Claeys","doi":"10.1109/ICCDCS.2012.6188896","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188896","url":null,"abstract":"This work characterizes the analog performance of SOI n-MuGFETs with different source/drain configurations. Devices without source/drain extension lead to a larger intrinsic voltage gain, even with the reduced transconductance, due to the increased Early voltage. At the same time, they showed a degradation of the interface quality with a larger low-frequency noise and reduced linearity. On the other hand, they can achieve reduced GIDL current due to the suppressed vertical electric field.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132060202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188928
E. Miranda, J. Suñé, S. Kano, C. Dou, K. Kakushima, H. Iwai
The electron transport in electroformed W/CeOx/SiO2/NiSi2 capacitors grown onto a p+-type Si substrate is investigated within the framework of the Landauer theory for mesoscopic systems. It is shown that the devices exhibit bipolar resistive switching with conductance levels in the low resistance state (LRS) of the order of integer and half integer values of the quantum conductance unit G0 = 2e2/h. This is consistent with the so-called nonlinear conduction regime in quantum point contacts. A simple model for the LRS I-V characteristics which accounts for the available right- and left-going conduction modes allowed by the constriction's size and the voltage drop distribution along the filamentary path is presented.
{"title":"Electron transport in CeOx-based resistive switching devices","authors":"E. Miranda, J. Suñé, S. Kano, C. Dou, K. Kakushima, H. Iwai","doi":"10.1109/ICCDCS.2012.6188928","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188928","url":null,"abstract":"The electron transport in electroformed W/CeOx/SiO2/NiSi2 capacitors grown onto a p+-type Si substrate is investigated within the framework of the Landauer theory for mesoscopic systems. It is shown that the devices exhibit bipolar resistive switching with conductance levels in the low resistance state (LRS) of the order of integer and half integer values of the quantum conductance unit G0 = 2e2/h. This is consistent with the so-called nonlinear conduction regime in quantum point contacts. A simple model for the LRS I-V characteristics which accounts for the available right- and left-going conduction modes allowed by the constriction's size and the voltage drop distribution along the filamentary path is presented.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116970356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188902
L. Moreno-Ahedo, R. Carmona, R. Francisco, F. Ortiz, I. Cruz
This paper presents an electronic circuit that exhibits parametric resonance, namely a parametric RLC oscillator. The circuit exploits parametric resonance in an analog application, namely, a gain-frequency dependent switch. In such circuit, when the amplitude and frequency of the parametric excitation varies then a transition curves, in the parameter space, are computed by using an algorithm that calculates the symbolic monodromy matrix. Such curves are interpreted to implement an analog application.
{"title":"On the implementation of a parametric oscillator in analog applications","authors":"L. Moreno-Ahedo, R. Carmona, R. Francisco, F. Ortiz, I. Cruz","doi":"10.1109/ICCDCS.2012.6188902","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188902","url":null,"abstract":"This paper presents an electronic circuit that exhibits parametric resonance, namely a parametric RLC oscillator. The circuit exploits parametric resonance in an analog application, namely, a gain-frequency dependent switch. In such circuit, when the amplitude and frequency of the parametric excitation varies then a transition curves, in the parameter space, are computed by using an algorithm that calculates the symbolic monodromy matrix. Such curves are interpreted to implement an analog application.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"17 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120988217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188950
B. Soto-Cruz, F. López-Huerta
In the CMOS MEMS design the problems are centered on the sensor integration on-a-chip and its release post-process. The extracellular planar microelectrodes are straight form integrated due the layers CMOS possibilities, however the releasement of them must be done after the CMOS fabrication process. In this regard, the work presents the complete post-process methodology and the results of the technological post-process on 2.2mm×2.2mm square die. Preliminary results showed a) the viability of this post-process methodology and b) the on-chip functionality for extracellular in-vitro culture.
{"title":"Post-process methodology on-a CMOS chip to release an extracellular microelectrode array","authors":"B. Soto-Cruz, F. López-Huerta","doi":"10.1109/ICCDCS.2012.6188950","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188950","url":null,"abstract":"In the CMOS MEMS design the problems are centered on the sensor integration on-a-chip and its release post-process. The extracellular planar microelectrodes are straight form integrated due the layers CMOS possibilities, however the releasement of them must be done after the CMOS fabrication process. In this regard, the work presents the complete post-process methodology and the results of the technological post-process on 2.2mm×2.2mm square die. Preliminary results showed a) the viability of this post-process methodology and b) the on-chip functionality for extracellular in-vitro culture.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130857489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188888
M. Shur
The feature sizes of short channel Si MOSFETs and FINFETs are now in the range, where ballistic or quasi-ballistic transport is dominant. In this regime, conventional notion of electron mobility becomes invalid, and electrons lose energy and momentum in the contacts rather than in the device channel. In these devices, electron inertia plays an important role, and oscillations of the electron density (called plasma oscillations) enable the device response at THz frequencies. At THz and sub-THz frequencies, electron inertia effects, which are the signature of the ballistic transport, are pronounced even in FETs with feature sizes as large as 1 micron. Due to these effects, the device impedance becomes an oscillatory function of frequency. Plasma wave THz detectors using oscillations of the electron density in device channels are expected to outperform more conventional THz detectors. Fig. 1 shows the calculated Si MOSFET THz detector responsivity versus frequency. Achieving their full potential of plasma wave electronics might require using grating gate structures and/or “plasmonic crystals implemented as 2D or 3D arrays of coherently operating plasmonic FETs.
{"title":"Ballistic transport in short channel field effect transistors","authors":"M. Shur","doi":"10.1109/ICCDCS.2012.6188888","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188888","url":null,"abstract":"The feature sizes of short channel Si MOSFETs and FINFETs are now in the range, where ballistic or quasi-ballistic transport is dominant. In this regime, conventional notion of electron mobility becomes invalid, and electrons lose energy and momentum in the contacts rather than in the device channel. In these devices, electron inertia plays an important role, and oscillations of the electron density (called plasma oscillations) enable the device response at THz frequencies. At THz and sub-THz frequencies, electron inertia effects, which are the signature of the ballistic transport, are pronounced even in FETs with feature sizes as large as 1 micron. Due to these effects, the device impedance becomes an oscillatory function of frequency. Plasma wave THz detectors using oscillations of the electron density in device channels are expected to outperform more conventional THz detectors. Fig. 1 shows the calculated Si MOSFET THz detector responsivity versus frequency. Achieving their full potential of plasma wave electronics might require using grating gate structures and/or “plasmonic crystals implemented as 2D or 3D arrays of coherently operating plasmonic FETs.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130905589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188915
A. Antonopoulos, K. Papathanasiou, M. Bucher
This paper presents a case study of LNA design at 30 GHz. Two single-stage LNA topologies are implemented, namely a magnetic feedback LNA and a cascode LNA. The simulation results reveal that a single-stage LNA can deliver adequate power gain along with low noise figure and high linearity even at mm-wave frequencies. The cascode LNA topology, using SNIM is analyzed and described in detail. The post layout simulations give a forward gain (S21) of 5.9 dB, a reverse isolation (-S12) of 18.1 dB, an input reflection (S11) of -11.8 dB and an output reflection (S22) of -11.4 dB. The NF of the circuit is 3.9 dB while the corresponding IIP3 is 4.9 dBm. The power consumption is 7.2 mW and the circuit occupies 0.37 mm2 including the pads. The design is implemented in TSMC's LP 90 nm CMOS process.
{"title":"CMOS LNA design at 30 GHz — A case study","authors":"A. Antonopoulos, K. Papathanasiou, M. Bucher","doi":"10.1109/ICCDCS.2012.6188915","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188915","url":null,"abstract":"This paper presents a case study of LNA design at 30 GHz. Two single-stage LNA topologies are implemented, namely a magnetic feedback LNA and a cascode LNA. The simulation results reveal that a single-stage LNA can deliver adequate power gain along with low noise figure and high linearity even at mm-wave frequencies. The cascode LNA topology, using SNIM is analyzed and described in detail. The post layout simulations give a forward gain (S21) of 5.9 dB, a reverse isolation (-S12) of 18.1 dB, an input reflection (S11) of -11.8 dB and an output reflection (S22) of -11.4 dB. The NF of the circuit is 3.9 dB while the corresponding IIP3 is 4.9 dBm. The power consumption is 7.2 mW and the circuit occupies 0.37 mm2 including the pads. The design is implemented in TSMC's LP 90 nm CMOS process.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123174960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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