Pub Date : 2025-03-18DOI: 10.1109/LSSC.2025.3551357
Young-Ju Oh;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong
This letter presents a compact single-stage buffer amplifier designed to drive a wide range of capacitive loads (CL). To further reduce power consumption and silicon area compared to previous single-stage rail-to-rail amplifiers, this letter proposes an asymmetric rail-to-rail class AB output structure. To achieve a high slew rate, the proposed amplifier employs positive feedback loops and a dynamic floating node. A prototype chip successfully drove a wide range of CL, from 250 pF to 15 nF, while achieving a fast transient response. The chip was fabricated using a 0.18-$mu $ m CMOS process.
这封信介绍了一个紧凑的单级缓冲放大器，设计用于驱动大范围的容性负载（CL）。与以前的单级轨对轨放大器相比，为了进一步降低功耗和硅面积，本信函提出了不对称轨对轨级AB输出结构。为了实现高摆率，该放大器采用了正反馈回路和动态浮动节点。原型芯片成功地驱动了宽范围的CL，从250 pF到15 nF，同时实现了快速的瞬态响应。该芯片采用0.18- $mu $ m CMOS工艺制备。
{"title":"Compact Single-Stage Input and Output Rail-to-Rail Class AB Buffer Amplifier With an Asymmetric Output Structure","authors":"Young-Ju Oh;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong","doi":"10.1109/LSSC.2025.3551357","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3551357","url":null,"abstract":"This letter presents a compact single-stage buffer amplifier designed to drive a wide range of capacitive loads (CL). To further reduce power consumption and silicon area compared to previous single-stage rail-to-rail amplifiers, this letter proposes an asymmetric rail-to-rail class AB output structure. To achieve a high slew rate, the proposed amplifier employs positive feedback loops and a dynamic floating node. A prototype chip successfully drove a wide range of CL, from 250 pF to 15 nF, while achieving a fast transient response. The chip was fabricated using a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"73-76"},"PeriodicalIF":2.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a global resonant clocking mesh architecture utilizing backside metal layers in an 18A class technology. Rotary traveling wave oscillators are implemented to provide synchronous low-skew, low-jitter, and 50% duty cycle clocks across a graphics core. To provide dynamic frequency and voltage scaling capabilities across a wide range of operating conditions, a high-speed fractional divider is designed. The proposed architecture is implemented on a 1.6 mm $times $ 1.6 mm graphics core achieving FoMJ of 246 dB FoMT 190.3dBc/Hz.
这封信介绍了一个利用18A级技术的背面金属层的全局谐振时钟网格架构。旋转行波振荡器的实现，以提供同步低斜，低抖动，和50%占空比时钟跨图形核心。为了在广泛的工作条件下提供动态频率和电压缩放能力，设计了高速分数分压器。所提出的架构在1.6 mm × 1.6 mm图形内核上实现，实现了246 dB的FoMJ 190.3dBc/Hz。
{"title":"A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology","authors":"Ragh Kuttappa;Vinayak Honkote;Amreesh Rao;Gaurav Kamalkar;Kailash Chandrashekar;Eric Finley;Chaitanya Sankuratri;Faran Rafiq;Robert Orton;Nils Hernandez;Anuradha Srinivasan;Tanay Karnik","doi":"10.1109/LSSC.2025.3552251","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3552251","url":null,"abstract":"This letter presents a global resonant clocking mesh architecture utilizing backside metal layers in an 18A class technology. Rotary traveling wave oscillators are implemented to provide synchronous low-skew, low-jitter, and 50% duty cycle clocks across a graphics core. To provide dynamic frequency and voltage scaling capabilities across a wide range of operating conditions, a high-speed fractional divider is designed. The proposed architecture is implemented on a 1.6 mm <inline-formula> <tex-math>$times $ </tex-math></inline-formula> 1.6 mm graphics core achieving FoMJ of 246 dB FoMT 190.3dBc/Hz.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"85-88"},"PeriodicalIF":2.2,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter introduces an active reflector for D-band communication utilizing 122-GHz wireless power transfer (WPT). The reflector consists of rectifiers with an integrated low-pass filter (LPF), an IF-band power combining network, and an 1-port amplifier composed of a circulator and IF-band amplifiers. The proposed rectifier not only works as an RF-DC converter but also operates as a self-heterodyne mixer by using the 122 GHz WPT signal as a LO. Since the rectifier operates in a fully passive manner, it can simultaneously perform the upconversion and downconversion required for Tx and Rx operations. The IF signal obtained from downconversion is efficiently amplified and then reinput into the IF distributing network and rectifier after 1-port amplifier for upconversion and reflectively transmission in the specular direction. According to probe measurements, the rectifier achieves a power conversion efficiency (PCE) of 12.2% with an input power of 9.3 dBm, and conversion gains of −15.9 and −17.7 dB for Tx and Rx modes, respectively. Additionally, the proposed rectifier supports a data rate of 48 Gb/s with a 64QAM modulation scheme and an 8-GHz bandwidth for both Tx and Rx.
{"title":"A 122 GHz Wirelessly Powered Active Reflector for D-Band Communications","authors":"Michihiro Ide;Keito Yuasa;Sena Kato;Shu Date;Takashi Tomura;Kenichi Okada;Atsushi Shirane","doi":"10.1109/LSSC.2025.3551244","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3551244","url":null,"abstract":"This letter introduces an active reflector for D-band communication utilizing 122-GHz wireless power transfer (WPT). The reflector consists of rectifiers with an integrated low-pass filter (LPF), an IF-band power combining network, and an 1-port amplifier composed of a circulator and IF-band amplifiers. The proposed rectifier not only works as an RF-DC converter but also operates as a self-heterodyne mixer by using the 122 GHz WPT signal as a LO. Since the rectifier operates in a fully passive manner, it can simultaneously perform the upconversion and downconversion required for Tx and Rx operations. The IF signal obtained from downconversion is efficiently amplified and then reinput into the IF distributing network and rectifier after 1-port amplifier for upconversion and reflectively transmission in the specular direction. According to probe measurements, the rectifier achieves a power conversion efficiency (PCE) of 12.2% with an input power of 9.3 dBm, and conversion gains of −15.9 and −17.7 dB for Tx and Rx modes, respectively. Additionally, the proposed rectifier supports a data rate of 48 Gb/s with a 64QAM modulation scheme and an 8-GHz bandwidth for both Tx and Rx.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"97-100"},"PeriodicalIF":2.2,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143835458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-10DOI: 10.1109/LSSC.2025.3549495
Yun Hao;Bo Zhou;Xukun Wang;Chunli Huang;Zhihua Wang
A bi-directional near-ground-output low-side-input current-sensing amplifier (CSA) is fabricated in 65-nm CMOS. Two negative-feedback paths drive dual pMOS transistors to conduct an auto-switching bi-directional current detection with configurable unidirectional gains, which reduces the conventional switching-point distortions and doubles the sensing accuracy. A DC shifter based on a negative-feedback loop, avoids an input large current to benefit the sensing linearity, and optimizes the common-mode rejection ratio (CMRR). Various noise and offset suppression mechanisms are also utilized. Experimental results show that the proposed CSA achieves an offset voltage of $1.58~mu $ V, a noise level of 37.5 nV/$surd $ Hz, and a CMRR up to 159 dB, with the power dissipation of 0.36 mW from a 1-V supply and an active area of 0.19 mm2. Reconfigurable or different unidirectional gains and near-ground input / output voltages are achieved, which are different from the existing designs.
{"title":"A Bi-Directional Near-Ground Current Sensor With Reconfigurable Unidirectional Gains","authors":"Yun Hao;Bo Zhou;Xukun Wang;Chunli Huang;Zhihua Wang","doi":"10.1109/LSSC.2025.3549495","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3549495","url":null,"abstract":"A bi-directional near-ground-output low-side-input current-sensing amplifier (CSA) is fabricated in 65-nm CMOS. Two negative-feedback paths drive dual pMOS transistors to conduct an auto-switching bi-directional current detection with configurable unidirectional gains, which reduces the conventional switching-point distortions and doubles the sensing accuracy. A DC shifter based on a negative-feedback loop, avoids an input large current to benefit the sensing linearity, and optimizes the common-mode rejection ratio (CMRR). Various noise and offset suppression mechanisms are also utilized. Experimental results show that the proposed CSA achieves an offset voltage of <inline-formula> <tex-math>$1.58~mu $ </tex-math></inline-formula>V, a noise level of 37.5 nV/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz, and a CMRR up to 159 dB, with the power dissipation of 0.36 mW from a 1-V supply and an active area of 0.19 mm2. Reconfigurable or different unidirectional gains and near-ground input / output voltages are achieved, which are different from the existing designs.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"77-80"},"PeriodicalIF":2.2,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-09DOI: 10.1109/LSSC.2025.3568061
Shaokang Zhao;Li Wang;C. Patrick Yue
This letter introduces the design of a 4-phase quadrature clock generator (QCG) featuring digital automatic calibration. The QCG architecture comprises a duty cycle correction (DCC) circuit, a digitally controlled delay line (DCDL), and an open-loop quadrature error correction (QEC) circuit utilizing phase interpolators (PIs). The DCDL generates clock signals with an initial coarse quadrature phase error, which is subsequently refined by the QEC to achieve a phase error of less than 1°. A finite state machine (FSM) conducts background calibration for the DCC and DCDL coarse correction, employing a pattern-detecting strategy to disable calibration, thereby eliminating spurious tones and deterministic jitter from the output clocks. Measurement results demonstrate that the proposed QCG achieves a phase error below 0.8° across a frequency range of 5–10 GHz, with an integrated jitter of 61.1 fs and a power consumption of 10.2 mW at 10-GHz operation.
{"title":"A 5–10-GHz Quadrature Clock Generator With Open-Loop Quadrature Error Correction in 28-nm CMOS","authors":"Shaokang Zhao;Li Wang;C. Patrick Yue","doi":"10.1109/LSSC.2025.3568061","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3568061","url":null,"abstract":"This letter introduces the design of a 4-phase quadrature clock generator (QCG) featuring digital automatic calibration. The QCG architecture comprises a duty cycle correction (DCC) circuit, a digitally controlled delay line (DCDL), and an open-loop quadrature error correction (QEC) circuit utilizing phase interpolators (PIs). The DCDL generates clock signals with an initial coarse quadrature phase error, which is subsequently refined by the QEC to achieve a phase error of less than 1°. A finite state machine (FSM) conducts background calibration for the DCC and DCDL coarse correction, employing a pattern-detecting strategy to disable calibration, thereby eliminating spurious tones and deterministic jitter from the output clocks. Measurement results demonstrate that the proposed QCG achieves a phase error below 0.8° across a frequency range of 5–10 GHz, with an integrated jitter of 61.1 fs and a power consumption of 10.2 mW at 10-GHz operation.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"149-152"},"PeriodicalIF":2.2,"publicationDate":"2025-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144139942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-07DOI: 10.1109/LSSC.2025.3567840
Hao Guo;Jiawei Chen;Hailong Jiao
A 15-transistor (15T) SRAM cell-based fully-digital computing-in-memory (CIM) macro is proposed for artificial intelligence accelerations. The CIM macro not only supports simultaneous read + write + multiply-accumulate (MAC) operations, but also supports ultrawide-range voltage scaling, digital design flow, and cell-wise bit interleaving. A fine-grained weight update scheme is introduced to perform write and MAC operations simultaneously. A specialized two’s complement processing strategy is proposed to enable efficient signed MAC operations without in-array sign extension. Fabricated in a 55-nm CMOS technology, the proposed fully-digital CIM macro enhances the peak energy efficiency by up to $3.46times $ compared with the state-of-the-art digital CIM schemes.
{"title":"A 15T SRAM Cell-Based Fully-Digital Computing-in-Memory Macro Supporting High Parallelism and Fine-Grained Simultaneous Read + Write + MAC Operations","authors":"Hao Guo;Jiawei Chen;Hailong Jiao","doi":"10.1109/LSSC.2025.3567840","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3567840","url":null,"abstract":"A 15-transistor (15T) SRAM cell-based fully-digital computing-in-memory (CIM) macro is proposed for artificial intelligence accelerations. The CIM macro not only supports simultaneous read + write + multiply-accumulate (MAC) operations, but also supports ultrawide-range voltage scaling, digital design flow, and cell-wise bit interleaving. A fine-grained weight update scheme is introduced to perform write and MAC operations simultaneously. A specialized two’s complement processing strategy is proposed to enable efficient signed MAC operations without in-array sign extension. Fabricated in a 55-nm CMOS technology, the proposed fully-digital CIM macro enhances the peak energy efficiency by up to <inline-formula> <tex-math>$3.46times $ </tex-math></inline-formula> compared with the state-of-the-art digital CIM schemes.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"153-156"},"PeriodicalIF":2.2,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-06DOI: 10.1109/LSSC.2025.3567309
Yu-Teng Chang;Shau-Chi Ho;Wen-Jie Lin
In this letter, we propose a wideband voltage-controlled oscillator (VCO) that combines a switchable inductor technique and negative transconductance $(G_{m})$ enhancement with the positive feedback loop. To extend the tuning range (TR) and reduce the frequency overlapping region between two modes, a mathematical analysis for the optimization TR is proposed to resist the frequency gap caused by process variations and implement a wider TR by using the switchable inductor. Furthermore, to compensate for the loss of the switchable inductor, the source-coupled pair provides additional wideband –$G_{m}$ characteristics to improve the Q value of the entire LC tank across the TR, thereby cooperating with the switchable inductance technique to implement the better phase noise (PN) across all TR. The measured TR is 39.67%, spanning from 10.77 to 16.1 GHz. At 13.19 GHz, the measured PN is –138 dBc/Hz at a 10-MHz offset frequency. The proposed VCO consumes only 10.7 mW of the total DC power. Comparing the proposed VCO to existing designs, these results demonstrate that it has a wider TR, an improved PN, and a higher figure of merit (FoM).
{"title":"A Wideband VCO Using a Switchable Inductance Technique and Negative Gₘ Enhancement With Positive Feedback","authors":"Yu-Teng Chang;Shau-Chi Ho;Wen-Jie Lin","doi":"10.1109/LSSC.2025.3567309","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3567309","url":null,"abstract":"In this letter, we propose a wideband voltage-controlled oscillator (VCO) that combines a switchable inductor technique and negative transconductance <inline-formula> <tex-math>$(G_{m})$ </tex-math></inline-formula> enhancement with the positive feedback loop. To extend the tuning range (TR) and reduce the frequency overlapping region between two modes, a mathematical analysis for the optimization TR is proposed to resist the frequency gap caused by process variations and implement a wider TR by using the switchable inductor. Furthermore, to compensate for the loss of the switchable inductor, the source-coupled pair provides additional wideband –<inline-formula> <tex-math>$G_{m}$ </tex-math></inline-formula> characteristics to improve the Q value of the entire LC tank across the TR, thereby cooperating with the switchable inductance technique to implement the better phase noise (PN) across all TR. The measured TR is 39.67%, spanning from 10.77 to 16.1 GHz. At 13.19 GHz, the measured PN is –138 dBc/Hz at a 10-MHz offset frequency. The proposed VCO consumes only 10.7 mW of the total DC power. Comparing the proposed VCO to existing designs, these results demonstrate that it has a wider TR, an improved PN, and a higher figure of merit (FoM).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"137-140"},"PeriodicalIF":2.2,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a near-$lambda $ /2-antenna-pitch 2-D phased-array CMOS receiver to address the challenge of implementing sub-THz beamforming with the narrow $lambda $ /$2~(approx ~555~mu $ m at 270 GHz) antenna pitch. A double superheterodyne architecture is adopted to reduce the area occupied by the 2-D RX array circuits by locating the E- and H-plane phase control circuits outside the array. Additionally, interpolated feeding is employed to enlarge the area available for the RX circuits by enabling an n-by-n array of RX elements to feed a near-$lambda $ /2-pitch ($2{n}$ – 1)-by-($2{n}$ – 1) antenna array composed of main and auxiliary antennas. A 40-nm CMOS prototype with $2times 2$ RX elements feeding $3times 3$ antenna elements demonstrate beam scanning ranges of approximately ±20° and ±30°in the E- and H-planes, respectively, and achieves 36-Gb/s QPSK signal transmission over a distance of 5 cm.
{"title":"A 300-GHz-Band 36-Gb/s Scalable 2-D Phased-Array CMOS Double Superheterodyne Receiver","authors":"Satoshi Tanaka;Shinsuke Hara;Kyoya Takano;Akifumi Kasamatsu;Yoshiki Sugimoto;Kunio Sakakibara;Shunichi Kubo;Takeshi Yoshida;Shuhei Amakawa;Minoru Fujishima","doi":"10.1109/LSSC.2025.3566726","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3566726","url":null,"abstract":"This letter presents a near-<inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/2-antenna-pitch 2-D phased-array CMOS receiver to address the challenge of implementing sub-THz beamforming with the narrow <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/<inline-formula> <tex-math>$2~(approx ~555~mu $ </tex-math></inline-formula>m at 270 GHz) antenna pitch. A double superheterodyne architecture is adopted to reduce the area occupied by the 2-D RX array circuits by locating the E- and H-plane phase control circuits outside the array. Additionally, interpolated feeding is employed to enlarge the area available for the RX circuits by enabling an n-by-n array of RX elements to feed a near-<inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/2-pitch (<inline-formula> <tex-math>$2{n}$ </tex-math></inline-formula> – 1)-by-(<inline-formula> <tex-math>$2{n}$ </tex-math></inline-formula> – 1) antenna array composed of main and auxiliary antennas. A 40-nm CMOS prototype with <inline-formula> <tex-math>$2times 2$ </tex-math></inline-formula> RX elements feeding <inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula> antenna elements demonstrate beam scanning ranges of approximately ±20° and ±30°in the E- and H-planes, respectively, and achieves 36-Gb/s QPSK signal transmission over a distance of 5 cm.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"133-136"},"PeriodicalIF":2.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10985811","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents a two-step direct-conversion front-end (Direct-FE) for noninvasive wearable biomedical devices. In the first step, a delta modulator ($Delta $ M) with embedded gain is used to implement coarse quantization, while in the second step, a discrete-time sigma delta modulator (DT-$Sigma Delta $ M) is used to realize fine quantization. DC-coupled differential difference amplifier (DDA) with resistor-based digital-to-analog converter (RDAC) is adopted as the input stage. Mismatch error shaping (MES) with reduced silicon area is utilized to suppress the mismatch error of the RDAC. The prototype has been implemented in 0.18-$mu $ m BCD process and achieves a peak input range of $7.64~{mathrm {V}_{mathrm {pp}}}$ , an input-referred-noise (IRN) of $1.59~mu mathrm {V}_{mathrm {RMS}}$ , a corresponding dynamic range (DR) of 115.2 dB, while consuming 2.4-mW power. The real physiological signals recording demonstrates its potential capability for wearable bio-potential acquisition, boosting the wearable and fitness application areas.
{"title":"A 115.2-dB Dynamic-Range Two-Step Direct-Conversion Front-End With Mismatch Error Shaping for Noninvasive Biomedical Devices","authors":"Yuxuan Chen;Xianzhi Yang;Jiayi Lin;Zilong Liu;Min Zeng;Qi Wu;Mingyi Chen","doi":"10.1109/LSSC.2025.3548453","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3548453","url":null,"abstract":"This article presents a two-step direct-conversion front-end (Direct-FE) for noninvasive wearable biomedical devices. In the first step, a delta modulator (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula> M) with embedded gain is used to implement coarse quantization, while in the second step, a discrete-time sigma delta modulator (DT-<inline-formula> <tex-math>$Sigma Delta $ </tex-math></inline-formula> M) is used to realize fine quantization. DC-coupled differential difference amplifier (DDA) with resistor-based digital-to-analog converter (RDAC) is adopted as the input stage. Mismatch error shaping (MES) with reduced silicon area is utilized to suppress the mismatch error of the RDAC. The prototype has been implemented in 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> m BCD process and achieves a peak input range of <inline-formula> <tex-math>$7.64~{mathrm {V}_{mathrm {pp}}}$ </tex-math></inline-formula>, an input-referred-noise (IRN) of <inline-formula> <tex-math>$1.59~mu mathrm {V}_{mathrm {RMS}}$ </tex-math></inline-formula>, a corresponding dynamic range (DR) of 115.2 dB, while consuming 2.4-mW power. The real physiological signals recording demonstrates its potential capability for wearable bio-potential acquisition, boosting the wearable and fitness application areas.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"69-72"},"PeriodicalIF":2.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143716507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a fully dynamic 4th-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed 4th-order cascaded integrator using dynamic-amplifier-assisted and passive integration. This ADC can achieve sharp NTF with only two dynamic amplifiers and is insensitive to process, voltage, and temperature (PVT) variation. The NS-SAR ADC occupies 0.09 mm2 in a 28-nm CMOS process. With a 1-V supply voltage, it consumes $107.38~mu $ W at 5 MS/s. The measured signal-to-noise and distortion ratio (SNDR) is 94.3 dB over a 100-kHz bandwidth (BW), resulting in a Schreier figure of merit (FoM) of 184 dB and a Walden FoM of 12.6 fJ/conv.-step.
{"title":"A 94.3-dB SNDR 184-dB FoMs 4th-Order Noise-Shaping SAR ADC With Dynamic-Amplifier-Assisted Cascaded Integrator","authors":"Kai-Cheng Cheng;Soon-Jyh Chang;Chung-Chieh Chen;Shuo-Hong Hung","doi":"10.1109/LSSC.2025.3544649","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3544649","url":null,"abstract":"This letter presents a fully dynamic 4th-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed 4th-order cascaded integrator using dynamic-amplifier-assisted and passive integration. This ADC can achieve sharp NTF with only two dynamic amplifiers and is insensitive to process, voltage, and temperature (PVT) variation. The NS-SAR ADC occupies 0.09 mm2 in a 28-nm CMOS process. With a 1-V supply voltage, it consumes <inline-formula> <tex-math>$107.38~mu $ </tex-math></inline-formula>W at 5 MS/s. The measured signal-to-noise and distortion ratio (SNDR) is 94.3 dB over a 100-kHz bandwidth (BW), resulting in a Schreier figure of merit (FoM) of 184 dB and a Walden FoM of 12.6 fJ/conv.-step.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"65-68"},"PeriodicalIF":2.2,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143637956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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