Pub Date : 2023-09-12DOI: 10.1109/LSSC.2023.3314457
Zilong Shen;Xiyuan Tang;Zhongyi Wu;Haoyang Luo;Zongnan Wang;Xiangxing Yang;Xing Zhang;Yuan Wang
This letter presents a capacitance-to-digital converter (CDC) with an incremental zoom current-controlled oscillator (CCO)-based time-domain $Delta Sigma $ modulator (TD- $Delta Sigma text{M}$ ). It supports single-sensor and single-shot measurement, which provides significant power saving. A double-PFD (DPFD) quantizer achieves $2times $ resolution enhancement compared to conventional PFD. A fast start-up scheme for CCO boosts conversion speed and ensures first conversion accuracy. The proposed design achieves 9.7 fJ/conv.-step with a short measurement time of $4.1~mu text{s}$ . To the authors’ best knowledge, it realizes the best energy efficiency and shortest measurement time among all high-resolution CDCs achieving over 12 ENOB.
{"title":"An Energy-Efficient Capacitive Sensor Readout Circuit With Zoomed Time-Domain Quantization","authors":"Zilong Shen;Xiyuan Tang;Zhongyi Wu;Haoyang Luo;Zongnan Wang;Xiangxing Yang;Xing Zhang;Yuan Wang","doi":"10.1109/LSSC.2023.3314457","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3314457","url":null,"abstract":"This letter presents a capacitance-to-digital converter (CDC) with an incremental zoom current-controlled oscillator (CCO)-based time-domain \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 modulator (TD-\u0000<inline-formula> <tex-math>$Delta Sigma text{M}$ </tex-math></inline-formula>\u0000). It supports single-sensor and single-shot measurement, which provides significant power saving. A double-PFD (DPFD) quantizer achieves \u0000<inline-formula> <tex-math>$2times $ </tex-math></inline-formula>\u0000 resolution enhancement compared to conventional PFD. A fast start-up scheme for CCO boosts conversion speed and ensures first conversion accuracy. The proposed design achieves 9.7 fJ/conv.-step with a short measurement time of \u0000<inline-formula> <tex-math>$4.1~mu text{s}$ </tex-math></inline-formula>\u0000. To the authors’ best knowledge, it realizes the best energy efficiency and shortest measurement time among all high-resolution CDCs achieving over 12 ENOB.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68080234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a concept of a circuit harvesting high-energy plasma and operating during its semiconductor fabrication process, namely, fetal-movement circuit (FMC). The plasma current collection antenna is designed to be a comb shape for area saving. This enables the FMC related circuits to be placed within a dicing street for suppressing its area penalty to be almost zero. A self-programming oxide-breakdown physically unclonable function (PUF) has been implemented as one of the FMC applications. The successful PUF programming operation during fabrication has been demonstrated.
{"title":"A Fetal-Movement Circuit Harvesting High-Energy Plasma During Fabrication, Concept, and Its Application to Self-Programming PUF","authors":"Kotaro Naruse;Takayuki Ueda;Jun Shiomi;Yoshihiro Midoh;Noriyuki Miura","doi":"10.1109/LSSC.2023.3313966","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3313966","url":null,"abstract":"This letter presents a concept of a circuit harvesting high-energy plasma and operating during its semiconductor fabrication process, namely, fetal-movement circuit (FMC). The plasma current collection antenna is designed to be a comb shape for area saving. This enables the FMC related circuits to be placed within a dicing street for suppressing its area penalty to be almost zero. A self-programming oxide-breakdown physically unclonable function (PUF) has been implemented as one of the FMC applications. The successful PUF programming operation during fabrication has been demonstrated.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8011414/10016898/10247264.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68079041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-08DOI: 10.1109/LSSC.2023.3311797
E. Ray Hsieh;C. F. Huang;S. Y. Huang;M. L. Miu;S. M. Lu;Y. S. Wu;Y. H. Ye
We introduce one kind of embedded dynamic-random-access-memory (eDRAM) array (16 kilo-bits) with peripheral circuits. Each cell in an array comprises 1-control-Fin-type-field-effect-transistor [FinFET (T)] and 1-storage-npn-diode (D). The latter can be implemented by a nFinFET with the floating gate electrode. This 1T1D eDRAM technology is fully integrated with the 16-nm FinFET process and can be continually shrunk to the 3-nm technology node. The size of the unit-cell is $0.0242~mu text{m}~^{mathrm{ 2}}$ . This 1T1D eDRAM cell can be programmed by the Zener-tunneling mechanism with 0.8 V of a writing voltage in 8 ns; the reading can be accomplished in 7 ns at −0.2 V. $116~mu text{s}$ of data retention at 25°C ( $101~mu text{s}$ at 75°C); $100~mu text{W}$ of the write power; $9.125~mu text{W}$ of the read power have been recorded as well. These experimental pieces of evidence suggest that our 1T1D embedded DRAM technology could replace the conventional 1-transistor-1-capacitance (1T1C) eDRAM one with better cost-efficiency and lower power in the advanced CMOS technology to 3-nm node.
{"title":"A Logic Fully Comparable Single-Supply Capacitor-Less 1-FinFET-1-Source-Channel-Drain-Diode (1T1D) Embedded DRAM MACRO in 16-nm FinFET","authors":"E. Ray Hsieh;C. F. Huang;S. Y. Huang;M. L. Miu;S. M. Lu;Y. S. Wu;Y. H. Ye","doi":"10.1109/LSSC.2023.3311797","DOIUrl":"10.1109/LSSC.2023.3311797","url":null,"abstract":"We introduce one kind of embedded dynamic-random-access-memory (eDRAM) array (16 kilo-bits) with peripheral circuits. Each cell in an array comprises 1-control-Fin-type-field-effect-transistor [FinFET (T)] and 1-storage-npn-diode (D). The latter can be implemented by a nFinFET with the floating gate electrode. This 1T1D eDRAM technology is fully integrated with the 16-nm FinFET process and can be continually shrunk to the 3-nm technology node. The size of the unit-cell is \u0000<inline-formula> <tex-math>$0.0242~mu text{m}~^{mathrm{ 2}}$ </tex-math></inline-formula>\u0000. This 1T1D eDRAM cell can be programmed by the Zener-tunneling mechanism with 0.8 V of a writing voltage in 8 ns; the reading can be accomplished in 7 ns at −0.2 V. \u0000<inline-formula> <tex-math>$116~mu text{s}$ </tex-math></inline-formula>\u0000 of data retention at 25°C (\u0000<inline-formula> <tex-math>$101~mu text{s}$ </tex-math></inline-formula>\u0000 at 75°C); \u0000<inline-formula> <tex-math>$100~mu text{W}$ </tex-math></inline-formula>\u0000 of the write power; \u0000<inline-formula> <tex-math>$9.125~mu text{W}$ </tex-math></inline-formula>\u0000 of the read power have been recorded as well. These experimental pieces of evidence suggest that our 1T1D embedded DRAM technology could replace the conventional 1-transistor-1-capacitance (1T1C) eDRAM one with better cost-efficiency and lower power in the advanced CMOS technology to 3-nm node.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62405091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-30DOI: 10.1109/LSSC.2023.3310266
Mao Li;Yunze Yang;Weifeng He;Sanu K. Mathew;Vivek De;Mingoo Seok
This letter presents the first on-chip detector for monitoring a PCB-level probing attack in 28-nm CMOS based on a time-to-digital converter (TDC). It can detect a probing attempt caused by placing a probe with a loading capacitance as small as 2 pF, encompassing most commercial passive probes. It also does so robustly across 30°C–90°C and 0.8–0.9 V, up to the data rate of 160 Mb/s during runtime. The proposed detector is integrated with a general-purpose digital output cell. It consumes $3910 ~mu text{m} ^{mathrm{ 2}}$ and $36.8 ~mu text{W}$ at 40 Mb/s.
{"title":"A Fully-Digital Variation-Tolerant Runtime Detector for PCB-Level Probing Attack in a 28-nm CMOS","authors":"Mao Li;Yunze Yang;Weifeng He;Sanu K. Mathew;Vivek De;Mingoo Seok","doi":"10.1109/LSSC.2023.3310266","DOIUrl":"10.1109/LSSC.2023.3310266","url":null,"abstract":"This letter presents the first on-chip detector for monitoring a PCB-level probing attack in 28-nm CMOS based on a time-to-digital converter (TDC). It can detect a probing attempt caused by placing a probe with a loading capacitance as small as 2 pF, encompassing most commercial passive probes. It also does so robustly across 30°C–90°C and 0.8–0.9 V, up to the data rate of 160 Mb/s during runtime. The proposed detector is integrated with a general-purpose digital output cell. It consumes <inline-formula> <tex-math notation=\"LaTeX\">$3910 ~mu text{m} ^{mathrm{ 2}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation=\"LaTeX\">$36.8 ~mu text{W}$ </tex-math></inline-formula> at 40 Mb/s.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62405048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-22DOI: 10.1109/LSSC.2023.3307456
Donggyu Minn;Kiseo Kang;Jaeho Lee;Jae-Yoon Sim
This letter presents a homodyne-demodulation readout IC with continuous-time direct analog integration for superconducting qubits. By integration at the analog front end, the effective signal-to-noise ratio is efficiently increased, eliminating the need for a high-performance analog-to-digital converter and costly baseband processing for data recovery. The proposed IC, fabricated in 40-nm CMOS, is verified at 4 K in a dilution refrigerator. The readout fidelity, estimated under real-world conditions, is reported to be 99% within 300 ns.
{"title":"A Cryo-CMOS Homodyne-Demodulation Qubit Readout IC With Continuous-Time Analog Integration for SNR Improvement","authors":"Donggyu Minn;Kiseo Kang;Jaeho Lee;Jae-Yoon Sim","doi":"10.1109/LSSC.2023.3307456","DOIUrl":"10.1109/LSSC.2023.3307456","url":null,"abstract":"This letter presents a homodyne-demodulation readout IC with continuous-time direct analog integration for superconducting qubits. By integration at the analog front end, the effective signal-to-noise ratio is efficiently increased, eliminating the need for a high-performance analog-to-digital converter and costly baseband processing for data recovery. The proposed IC, fabricated in 40-nm CMOS, is verified at 4 K in a dilution refrigerator. The readout fidelity, estimated under real-world conditions, is reported to be 99% within 300 ns.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62405041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-22DOI: 10.1109/LSSC.2023.3307361
Pranav Kumar;Nagendra Krishnapura
Pseudo-logarithmic signal-strength indicators are usually realized using a chain of amplifiers with amplitude detectors at the output of each stage and summing the output of the amplitude detectors. It is shown that the same can be achieved by measuring the total supply current of a pseudo-differential self-biased CMOS inverter chain. CMOS inverters act as amplifiers, and their supply current indicates the input amplitude. Amplification and amplitude detection are combined in the same block. The supply current is measured by mirroring the current in the pass transistor of the regulator that is used to power the inverter chain. The noise floor is set by the initial stages of the chain. A 65-nm prototype has a 70-dB dynamic range with ±1-dB error. It occupies 0.08 $text {mm}^{{2}}$ and consumes 1.2 mW from 1.5V. The input referred noise floor is 0.2-mV rms.
{"title":"Signal-Strength Detector Based on CMOS-Inverter Supply Current","authors":"Pranav Kumar;Nagendra Krishnapura","doi":"10.1109/LSSC.2023.3307361","DOIUrl":"10.1109/LSSC.2023.3307361","url":null,"abstract":"Pseudo-logarithmic signal-strength indicators are usually realized using a chain of amplifiers with amplitude detectors at the output of each stage and summing the output of the amplitude detectors. It is shown that the same can be achieved by measuring the total supply current of a pseudo-differential self-biased CMOS inverter chain. CMOS inverters act as amplifiers, and their supply current indicates the input amplitude. Amplification and amplitude detection are combined in the same block. The supply current is measured by mirroring the current in the pass transistor of the regulator that is used to power the inverter chain. The noise floor is set by the initial stages of the chain. A 65-nm prototype has a 70-dB dynamic range with ±1-dB error. It occupies 0.08\u0000<inline-formula> <tex-math>$text {mm}^{{2}}$ </tex-math></inline-formula>\u0000 and consumes 1.2 mW from 1.5V. The input referred noise floor is 0.2-mV rms.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62404989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a 4-bit switch-type phase shifter (STPS) with low phase error using standard 65-nm bulk CMOS technology. To reduce the phase error of conventional STPS, the proposed design employs a phase compensation network, utilizing opposite phase-shift characteristics of different filters. The measured maximum root-mean-square (RMS) phase and gain errors are 3.9° and 2.2 dB from 19 to 34 GHz, respectively. The measured RMS group delay error is smaller than 3.8 ps within the operating frequencies. The core area of the fabricated phase shifter is ${0.13 mathrm {mm}}^{2}$ excluding pads. The proposed phase shifter performs a low phase error with compact chip size compared with other reported STPSs within a similar bandwidth.
{"title":"A 19–34-GHz Bridged-T Phase Shifter With High-Pass Phase Compensation Achieving 3.9° RMS Phase Error for 5G NR","authors":"Yijing Liao;Minzhe Tang;Jian Pang;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2023.3305832","DOIUrl":"10.1109/LSSC.2023.3305832","url":null,"abstract":"This letter presents a 4-bit switch-type phase shifter (STPS) with low phase error using standard 65-nm bulk CMOS technology. To reduce the phase error of conventional STPS, the proposed design employs a phase compensation network, utilizing opposite phase-shift characteristics of different filters. The measured maximum root-mean-square (RMS) phase and gain errors are 3.9° and 2.2 dB from 19 to 34 GHz, respectively. The measured RMS group delay error is smaller than 3.8 ps within the operating frequencies. The core area of the fabricated phase shifter is \u0000<inline-formula> <tex-math>${0.13 mathrm {mm}}^{2}$ </tex-math></inline-formula>\u0000 excluding pads. The proposed phase shifter performs a low phase error with compact chip size compared with other reported STPSs within a similar bandwidth.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62404800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-11DOI: 10.1109/LSSC.2023.3304305
Shih-Kai Kuo;Manideep Dunna;Hongyu Lu;Akshit Agarwal;Dinesh Bharadia;Patrick P. Mercier
This letter presents a backscattering chip that is powered via LTE signals and reflects an incident reverse-whitened Bluetooth low energy (BLE) tone-like advertisement packet into a reradiated single-side-band (SSB) 802.11 b WiFi packet at a configurable WiFi channel location, all toward enabling an RFID-like single-device interrogation system. The chip includes an RF energy harvester, a WiFi wake-up receiver, an intermediate frequency (IF) ring oscillator whose frequency is calibrated with a successive-approximation-register (SAR) frequency-lock-loop (FLL), and a QPSK SSB backscatter modulator. Implemented in 65-nm CMOS, the chip consumes 4.5- $mu text{W}$ power in wake-up mode and 11 to $45~mu text{W}$ power in backscatter mode, with on-chip ring oscillator frequencies ranging from 33 to 253 MHz in order to support eight different BLE-to-WiFi backscatter schemes. Wireless measurement showed that the chip can be charged to 1 V before backscattering within 1 s on a 1- $mu text{F}$ off-chip storage capacitor up to a 50-cm distance.
{"title":"LTE-Powered BLE-to-WiFi Backscattering Chip Toward Single-Device Interrogation RFID-Like Systems","authors":"Shih-Kai Kuo;Manideep Dunna;Hongyu Lu;Akshit Agarwal;Dinesh Bharadia;Patrick P. Mercier","doi":"10.1109/LSSC.2023.3304305","DOIUrl":"10.1109/LSSC.2023.3304305","url":null,"abstract":"This letter presents a backscattering chip that is powered via LTE signals and reflects an incident reverse-whitened Bluetooth low energy (BLE) tone-like advertisement packet into a reradiated single-side-band (SSB) 802.11 b WiFi packet at a configurable WiFi channel location, all toward enabling an RFID-like single-device interrogation system. The chip includes an RF energy harvester, a WiFi wake-up receiver, an intermediate frequency (IF) ring oscillator whose frequency is calibrated with a successive-approximation-register (SAR) frequency-lock-loop (FLL), and a QPSK SSB backscatter modulator. Implemented in 65-nm CMOS, the chip consumes 4.5-\u0000<inline-formula> <tex-math>$mu text{W}$ </tex-math></inline-formula>\u0000 power in wake-up mode and 11 to \u0000<inline-formula> <tex-math>$45~mu text{W}$ </tex-math></inline-formula>\u0000 power in backscatter mode, with on-chip ring oscillator frequencies ranging from 33 to 253 MHz in order to support eight different BLE-to-WiFi backscatter schemes. Wireless measurement showed that the chip can be charged to 1 V before backscattering within 1 s on a 1-\u0000<inline-formula> <tex-math>$mu text{F}$ </tex-math></inline-formula>\u0000 off-chip storage capacitor up to a 50-cm distance.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62404782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-08DOI: 10.1109/LSSC.2023.3303332
Yuqi Su;Tony Tae-Hyoung Kim;Bongjin Kim
Ising machines have recently emerged as efficient computers for nondeterministic polynomial-time hard (NP-hard) combinatorial optimization problems (COPs). While most prior works have built their Ising machines with spins arranged in a graph with only two-body interactions, many real-world COPs, including a popular Boolean satisfiability (SAT) problem, often involve many-body spin interactions. This letter presents a novel Ising machine that can directly map and solve 3-SAT problems (i.e., SAT problems with at most three literals per clause). The proposed Ising machine eliminates the hardware overhead due to the ancillary spins required for approximate mapping used for the prior Ising machines with two-body interactions only. For evaluation, a prototype chip is fabricated using 65 nm and solved 3-SAT problems and their variants (a weighted max 3-SAT). The 65-nm chip occupies 0.345 mm 2 for 128–1024 embedded spins with 8-bit interaction coefficients and consumes $3.73~mu text{W}$ per spin at 1.2 V and 64 MHz.
伊辛机最近成为解决不确定多项式时间困难（NP-困难）组合优化问题（COP）的有效计算机。虽然大多数先前的工作都构建了Ising机器，其自旋排列在只有两个身体相互作用的图中，但许多现实世界的COP，包括一个流行的布尔可满足性（SAT）问题，通常涉及许多身体-自旋相互作用。这封信提出了一种新颖的Ising机器，它可以直接映射和解决3-SAT问题（即每个子句最多有三个文字的SAT问题）。所提出的Ising机器消除了由于用于仅具有两个身体相互作用的现有Ising机器的近似映射所需的辅助自旋而引起的硬件开销。为了进行评估，使用65nm制造了原型芯片，并解决了3-SAT问题及其变体（加权最大3-SAT）。对于128–1024个具有8位相互作用系数的嵌入自旋，65 nm芯片占用0.345 mm 2，并且在1.2 V和64 MHz下每自旋消耗3.73美元。
{"title":"A Reconfigurable CMOS Ising Machine With Three-Body Spin Interactions for Solving Boolean Satisfiability With Direct Mapping","authors":"Yuqi Su;Tony Tae-Hyoung Kim;Bongjin Kim","doi":"10.1109/LSSC.2023.3303332","DOIUrl":"10.1109/LSSC.2023.3303332","url":null,"abstract":"Ising machines have recently emerged as efficient computers for nondeterministic polynomial-time hard (NP-hard) combinatorial optimization problems (COPs). While most prior works have built their Ising machines with spins arranged in a graph with only two-body interactions, many real-world COPs, including a popular Boolean satisfiability (SAT) problem, often involve many-body spin interactions. This letter presents a novel Ising machine that can directly map and solve 3-SAT problems (i.e., SAT problems with at most three literals per clause). The proposed Ising machine eliminates the hardware overhead due to the ancillary spins required for approximate mapping used for the prior Ising machines with two-body interactions only. For evaluation, a prototype chip is fabricated using 65 nm and solved 3-SAT problems and their variants (a weighted max 3-SAT). The 65-nm chip occupies 0.345 mm 2 for 128–1024 embedded spins with 8-bit interaction coefficients and consumes \u0000<inline-formula> <tex-math>$3.73~mu text{W}$ </tex-math></inline-formula>\u0000 per spin at 1.2 V and 64 MHz.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62404744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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