This letter presents a $4times 56$ -Gbaud linear transimpedance amplifier (TIA) with low noise and high linearity, designed for linear-drive pluggable optics (LPO) and implemented in 0.13-$mu $ m SiGe-BiCMOS technology (fT/f${_{text {MAX}}} {=} 260$ /350 GHz). The TIA features an inductive shunt-feedback (ISFB) transimpedance stage (TIS) with a $pi $ -topology L-C network as the input stage, achieving wide bandwidth (BW) and low noise despite large photodiode (PD) and packaging parasitic capacitances. Two current-splitting variable gain amplifiers (VGAs) with continuous-time linear equalizer (CTLE) functionality are cascaded after the TIS, providing a gain control range of –12 to +18 dB and accommodating input currents up to 2mApp. A 50-ohm output buffer with T-coil further extends the BW. Measurement results demonstrate a maximum optical-to-electrical transimpedance gain (O/E.ZT) of 73.8 dB$Omega $ , an O/E O/E.BW exceeding 40 GHz, an input-referred noise (IRN) current of $1.9~mu $ Arms, and total harmonic distortion (THD) ¡ 4.5% for a 700-mVpp output swing. The TIA supports 56-Gbaud PAM-4 eye diagrams with PRBS31Q and achieves 9.7-dBm optical modulation amplitude (OMA) sensitivity at the pre-FEC BER limit of $2.4times 10^{-4}$ for 56-Gbaud PAM-4 SSPRQ. The design achieves a power efficiency of 1.67 pJ/bit and occupies an area of $3.14times 1.04$ mm2.
本文介绍了一种$4times 56$ - gbaud线性跨阻放大器（TIA），具有低噪声和高线性度，专为线性驱动可插拔光学器件（LPO）设计，采用0.13- $mu $ m SiGe-BiCMOS技术（fT/f ${_{text {MAX}}} {=} 260$ /350 GHz）实现。该TIA具有电感式并联反馈（ISFB）跨阻级（TIS），其输入级为$pi $ -拓扑L-C网络，尽管具有较大的光电二极管（PD）和封装寄生电容，但仍可实现宽带（BW）和低噪声。两个具有连续时间线性均衡器（CTLE）功能的分流可变增益放大器（vga）级联在TIS之后，提供-12至+18 dB的增益控制范围，可容纳高达2mApp的输入电流。50欧姆输出缓冲器与t线圈进一步扩展了BW。测量结果表明，最大光电透阻增益（O/E. zt）为73.8 dB $Omega $, O/E. O/E。BW超过40 GHz，输入参考噪声（IRN）电流为$1.9~mu $ Arms，总谐波失真（THD）为4.5% for a 700-mVpp output swing. The TIA supports 56-Gbaud PAM-4 eye diagrams with PRBS31Q and achieves 9.7-dBm optical modulation amplitude (OMA) sensitivity at the pre-FEC BER limit of $2.4times 10^{-4}$ for 56-Gbaud PAM-4 SSPRQ. The design achieves a power efficiency of 1.67 pJ/bit and occupies an area of $3.14times 1.04$ mm2.
{"title":"A 4×56 -Gbaud PAM-4 Linear and Low-Noise TIA for Linear-Drive Pluggable Optics","authors":"Wei Chen;Minhao Li;Ming Zhong;Yuan Li;Ying Wu;Pisen Zhou;Patrick Yin Chiang","doi":"10.1109/LSSC.2025.3574875","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3574875","url":null,"abstract":"This letter presents a <inline-formula> <tex-math>$4times 56$ </tex-math></inline-formula>-Gbaud linear transimpedance amplifier (TIA) with low noise and high linearity, designed for linear-drive pluggable optics (LPO) and implemented in 0.13-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m SiGe-BiCMOS technology (fT/f<inline-formula> <tex-math>${_{text {MAX}}} {=} 260$ </tex-math></inline-formula>/350 GHz). The TIA features an inductive shunt-feedback (ISFB) transimpedance stage (TIS) with a <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-topology L-C network as the input stage, achieving wide bandwidth (BW) and low noise despite large photodiode (PD) and packaging parasitic capacitances. Two current-splitting variable gain amplifiers (VGAs) with continuous-time linear equalizer (CTLE) functionality are cascaded after the TIS, providing a gain control range of –12 to +18 dB and accommodating input currents up to 2mApp. A 50-ohm output buffer with T-coil further extends the BW. Measurement results demonstrate a maximum optical-to-electrical transimpedance gain (O/E.ZT) of 73.8 dB<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>, an O/E O/E.BW exceeding 40 GHz, an input-referred noise (IRN) current of <inline-formula> <tex-math>$1.9~mu $ </tex-math></inline-formula>Arms, and total harmonic distortion (THD) ¡ 4.5% for a 700-mVpp output swing. The TIA supports 56-Gbaud PAM-4 eye diagrams with PRBS31Q and achieves 9.7-dBm optical modulation amplitude (OMA) sensitivity at the pre-FEC BER limit of <inline-formula> <tex-math>$2.4times 10^{-4}$ </tex-math></inline-formula> for 56-Gbaud PAM-4 SSPRQ. The design achieves a power efficiency of 1.67 pJ/bit and occupies an area of <inline-formula> <tex-math>$3.14times 1.04$ </tex-math></inline-formula> mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"197-200"},"PeriodicalIF":2.2,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144663709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-28DOI: 10.1109/LSSC.2025.3574413
Yu-Kai Chen;Yi-Fan Tseng;Wei-Zhe Su;Chun-Hsing Li
A 302.5-GHz high-gain CMOS THz amplifier is proposed in this work. An electromagnetic (EM) modeling approach, verified by transistor measurements, is employed to optimize transistor layout, effectively reducing gate resistance and drain-to-gate capacitance. This significantly enhances the transistor’s maximum oscillation frequency $f_{mathrm {max }}$ from 239.7 to 367.5 GHz. Furthermore, a $G_{mathrm {max }}$ -peak-offset-matching technique is proposed to simultaneously optimize active transistors and passive matching networks, significantly increasing the gain by 3.5 dB. Implemented in a 65-nm CMOS technology, the proposed THz amplifier achieves a measured gain of 30.9 dB at 302.5 GHz with an output saturation power of –5.3 dBm while only consuming 35.4 mW from a 1.1 V supply. To the best of the authors’ knowledge, this work exhibits the first experimental validation of the EM modeling approach and achieves the highest reported gain above 200 GHz in bulk CMOS technologies.
{"title":"A 302.5-GHz 30.9-dB-Gain THz Amplifier in 65-nm CMOS","authors":"Yu-Kai Chen;Yi-Fan Tseng;Wei-Zhe Su;Chun-Hsing Li","doi":"10.1109/LSSC.2025.3574413","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3574413","url":null,"abstract":"A 302.5-GHz high-gain CMOS THz amplifier is proposed in this work. An electromagnetic (EM) modeling approach, verified by transistor measurements, is employed to optimize transistor layout, effectively reducing gate resistance and drain-to-gate capacitance. This significantly enhances the transistor’s maximum oscillation frequency <inline-formula> <tex-math>$f_{mathrm {max }}$ </tex-math></inline-formula> from 239.7 to 367.5 GHz. Furthermore, a <inline-formula> <tex-math>$G_{mathrm {max }}$ </tex-math></inline-formula>-peak-offset-matching technique is proposed to simultaneously optimize active transistors and passive matching networks, significantly increasing the gain by 3.5 dB. Implemented in a 65-nm CMOS technology, the proposed THz amplifier achieves a measured gain of 30.9 dB at 302.5 GHz with an output saturation power of –5.3 dBm while only consuming 35.4 mW from a 1.1 V supply. To the best of the authors’ knowledge, this work exhibits the first experimental validation of the EM modeling approach and achieves the highest reported gain above 200 GHz in bulk CMOS technologies.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"165-168"},"PeriodicalIF":2.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Frequency-modulated continuous wave (FMCW) LiDAR offers a significant advantage over FMCW RADAR due to its superior lateral resolution, achieving more than a $1000times $ improvement. However, laser nonlinearities require the use of electro-optical phase-locked loops (EO PLLs), and conventional EO PLL-based FMCW LiDAR systems are susceptible to spoofing attacks. To address this vulnerability, this letter introduces an electro-optical (EO) synthesizer designed to generate FMCW signals with randomly varying chirp rates per frame. The synthesizer incorporates an on-chip SRAM-based physically unclonable function (PUF) fabricated in 180-nm RF CMOS, which generates a device-specific random key to enhance the security of FMCW LiDAR against spoofing attacks. The synthesizer supports four programmable chirp rates: from 8.5 to 12 GHz/ms with a chirp period of $600~mu $ s, and from 12.75 to 18 GHz/ms with a chirp period of $200~mu $ s, resulting in a $5times $ increase in generated cloud points compared to existing long-range EO PLL-based FMCW LiDAR systems.
{"title":"Secure FMCW LiDAR Ranging With an Electro-Optical Synthesizer at 5000 Measurements/s","authors":"Marziyeh Rezaei;Liban Hussein;Alana Dee;Shucheng Fang;Qixuan Lin;Mo Li;Sajjad Moazeni","doi":"10.1109/LSSC.2025.3555948","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3555948","url":null,"abstract":"Frequency-modulated continuous wave (FMCW) LiDAR offers a significant advantage over FMCW RADAR due to its superior lateral resolution, achieving more than a <inline-formula> <tex-math>$1000times $ </tex-math></inline-formula> improvement. However, laser nonlinearities require the use of electro-optical phase-locked loops (EO PLLs), and conventional EO PLL-based FMCW LiDAR systems are susceptible to spoofing attacks. To address this vulnerability, this letter introduces an electro-optical (EO) synthesizer designed to generate FMCW signals with randomly varying chirp rates per frame. The synthesizer incorporates an on-chip SRAM-based physically unclonable function (PUF) fabricated in 180-nm RF CMOS, which generates a device-specific random key to enhance the security of FMCW LiDAR against spoofing attacks. The synthesizer supports four programmable chirp rates: from 8.5 to 12 GHz/ms with a chirp period of <inline-formula> <tex-math>$600~mu $ </tex-math></inline-formula>s, and from 12.75 to 18 GHz/ms with a chirp period of <inline-formula> <tex-math>$200~mu $ </tex-math></inline-formula>s, resulting in a <inline-formula> <tex-math>$5times $ </tex-math></inline-formula> increase in generated cloud points compared to existing long-range EO PLL-based FMCW LiDAR systems.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"93-96"},"PeriodicalIF":2.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143830476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-27DOI: 10.1109/LSSC.2025.3573757
Nengxu Zhu;Yiting Zhang;Genyin Ma;Fanyi Meng
This letter presents two 7–13-GHz GaAs-SiGe four-channel beamforming chiplets to minimize the chip area. The chips integrate GaAs-based power amplifiers (PAs) and low-noise amplifiers (LNAs) with silicon-based phase and amplitude control modules using gold bumps. To mitigate coupling between the metal patterns of the heterogeneous chips and avoid interference with beamforming performance, a metallic interlayer shield is introduced at the interface. This shield ensures effective integration and preserves the functionality and performance of both the compound and silicon-based components. The fabricated four-channel 3-D heterogeneous integrated radio-frequency front-end chips, using 0.25-$mu $ m GaAs and 0.13-$mu $ m SiGe BiCMOS processes, achieve 6-bit amplitude/phase control with 0.5 dB/5.625° resolution with power consumption of 3.6 W (TX) and 1.6 W (RX). The RMS amplitude and phase errors are <0.6> $mathrm { OP_{1dB}}$ and −1.5-dBm RX IP1dB, with a compact total area of $4.1times 3.05$ mm2.
这封信提出了两个7 - 13 ghz GaAs-SiGe四通道波束成形小芯片，以最大限度地减少芯片面积。该芯片将基于砷化镓的功率放大器（PAs）和低噪声放大器（LNAs）与使用金凸起的硅基相位和幅度控制模块集成在一起。为了减轻非均质芯片金属图案之间的耦合，避免对波束形成性能的干扰，在接口处引入了金属层间屏蔽。这种屏蔽确保了有效的集成，并保留了化合物和硅基组件的功能和性能。该四通道三维异构集成射频前端芯片采用0.25- $mu $ m GaAs和0.13- $mu $ m SiGe BiCMOS工艺，实现了6位幅度/相位控制，分辨率为0.5 dB/5.625°，功耗为3.6 W （TX）和1.6 W （RX）。RMS幅值和相位误差分别为$ mathm {OP_{1dB}}$和- 1.5 dbm RX IP1dB，总面积为$4.1 × 3.05$ mm2。
{"title":"Two 7–13-GHz GaAs-SiGe Four–Channel Beamforming Chiplets With/Without Metallic Interlayer Shields","authors":"Nengxu Zhu;Yiting Zhang;Genyin Ma;Fanyi Meng","doi":"10.1109/LSSC.2025.3573757","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3573757","url":null,"abstract":"This letter presents two 7–13-GHz GaAs-SiGe four-channel beamforming chiplets to minimize the chip area. The chips integrate GaAs-based power amplifiers (PAs) and low-noise amplifiers (LNAs) with silicon-based phase and amplitude control modules using gold bumps. To mitigate coupling between the metal patterns of the heterogeneous chips and avoid interference with beamforming performance, a metallic interlayer shield is introduced at the interface. This shield ensures effective integration and preserves the functionality and performance of both the compound and silicon-based components. The fabricated four-channel 3-D heterogeneous integrated radio-frequency front-end chips, using 0.25-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m GaAs and 0.13-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m SiGe BiCMOS processes, achieve 6-bit amplitude/phase control with 0.5 dB/5.625° resolution with power consumption of 3.6 W (TX) and 1.6 W (RX). The RMS amplitude and phase errors are <0.6> <tex-math>$mathrm { OP_{1dB}}$ </tex-math></inline-formula> and −1.5-dBm RX IP1dB, with a compact total area of <inline-formula> <tex-math>$4.1times 3.05$ </tex-math></inline-formula> mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"161-164"},"PeriodicalIF":2.2,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The proposed low input current ripple (LICR) switched-capacitor (SC) hybrid converter effectively minimizes input current ripple by incorporating a precompensation active biasing electromagnetic interference (EMI) filter (PABEF), addressing EMI issues in automotive applications without requiring large external components. In addition, the current-modulation gate driver (CMGD) helps suppress conducted EMI noise at high frequencies. As a result, the LICR achieves a 74% reduction in input current ripple, EMI noise attenuation of 32 dB at low frequencies and 5 dB at high frequencies, and a peak efficiency of 93.3% at $V_{mathrm { O}}$ /$V_{mathrm { IN}}{=}1.8$ /24.
{"title":"A 24 V-to-1 V Low Input Current Ripple SC Hybrid Converter With Conducted EMI Noise Precompensation Filter and Current-Modulated Gate-Driver for Automobile Application","authors":"Yu-Tse Shih;Li-Jen Huang;Xiao-Quan Wu;Wei-Chieh Hung;Tz-Han Hsu;Kuo-Lin Zheng;Ke-Horng Chen;Ying-Hsi Lin;Shian-Ru Lin;Tsung-Yen Tsai","doi":"10.1109/LSSC.2025.3554811","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3554811","url":null,"abstract":"The proposed low input current ripple (LICR) switched-capacitor (SC) hybrid converter effectively minimizes input current ripple by incorporating a precompensation active biasing electromagnetic interference (EMI) filter (PABEF), addressing EMI issues in automotive applications without requiring large external components. In addition, the current-modulation gate driver (CMGD) helps suppress conducted EMI noise at high frequencies. As a result, the LICR achieves a 74% reduction in input current ripple, EMI noise attenuation of 32 dB at low frequencies and 5 dB at high frequencies, and a peak efficiency of 93.3% at <inline-formula> <tex-math>$V_{mathrm { O}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$V_{mathrm { IN}}{=}1.8$ </tex-math></inline-formula>/24.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"89-92"},"PeriodicalIF":2.2,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-21DOI: 10.1109/LSSC.2025.3572385
Kedar Bhatt;Stafford Hutchins;Atresh Sanne;Mohammad M. Hasan;Zhanping Chen;Jaydeep P. Kulkarni
A fast, accurate, single-rail voltage detection circuit (VDC) is presented. Low voltage operation is achieved by a variable gain Charge Pump (CP) followed by a Low-Dropout regulator (LDO). An Open-loop band gap reference (BGREF), passed to a dynamic comparator, achieves an undervoltage trip point of 0.62 V with 8.7 mV sigma, and an overvoltage trip point of 1.22 V with 12 mV sigma, demonstrated on Intel 4 silicon prototype. The design operates without any filter cap, allowing a fast, power-on ramp of $2~mu $ s, and brown-out detection of <200 ns. A voltage band detection of 0.48–1.22 V is enabled through a finite-state machine (FSM) to modify CP and LDO gain depending on input voltage.
{"title":"A Bandgap Diode-Based Voltage Band Detection Circuit With Fast Response Time and Low Vmin on Intel 4 Logic Technology","authors":"Kedar Bhatt;Stafford Hutchins;Atresh Sanne;Mohammad M. Hasan;Zhanping Chen;Jaydeep P. Kulkarni","doi":"10.1109/LSSC.2025.3572385","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3572385","url":null,"abstract":"A fast, accurate, single-rail voltage detection circuit (VDC) is presented. Low voltage operation is achieved by a variable gain Charge Pump (CP) followed by a Low-Dropout regulator (LDO). An Open-loop band gap reference (BGREF), passed to a dynamic comparator, achieves an undervoltage trip point of 0.62 V with 8.7 mV sigma, and an overvoltage trip point of 1.22 V with 12 mV sigma, demonstrated on Intel 4 silicon prototype. The design operates without any filter cap, allowing a fast, power-on ramp of <inline-formula> <tex-math>$2~mu $ </tex-math></inline-formula>s, and brown-out detection of <200 ns. A voltage band detection of 0.48–1.22 V is enabled through a finite-state machine (FSM) to modify CP and LDO gain depending on input voltage.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"157-160"},"PeriodicalIF":2.2,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-18DOI: 10.1109/LSSC.2025.3552520
Zehang Wu;Chi-Hang Chan;Yan Zhu;Rui P. Martins;Minglei Zhang
This letter presents a 32-GS/s per-way hierarchical sampling front-end (SFE) for time-interleaved ADCs, featuring both high linearity and energy efficiency with inherent embedded gain from an inverter-based topology. The P/N ratio configuration extends its applicable input common-mode voltage range. Both active and passive extensions improve the bandwidth of the SFE supplied by a core-device voltage. Furthermore, an improved dual-path bootstrapped switch enhances the sampling bandwidth and linearity at 8 GS/s. Fabricated in a 28-nm CMOS process, the inverter-based SFE achieves 30-GHz bandwidth while consuming 49.4 mW from a 0.95-V supply. The measured spurious free dynamic range (SFDR) and signal-to-noise and -distortion ratio (SNDR) at 50-GHz input are 46.9 dB and 36.1 dB, respectively.
{"title":"An Inverter-Based Sampling Front-End Achieving >46-dB SFDR at 50-GHz Input","authors":"Zehang Wu;Chi-Hang Chan;Yan Zhu;Rui P. Martins;Minglei Zhang","doi":"10.1109/LSSC.2025.3552520","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3552520","url":null,"abstract":"This letter presents a 32-GS/s per-way hierarchical sampling front-end (SFE) for time-interleaved ADCs, featuring both high linearity and energy efficiency with inherent embedded gain from an inverter-based topology. The P/N ratio configuration extends its applicable input common-mode voltage range. Both active and passive extensions improve the bandwidth of the SFE supplied by a core-device voltage. Furthermore, an improved dual-path bootstrapped switch enhances the sampling bandwidth and linearity at 8 GS/s. Fabricated in a 28-nm CMOS process, the inverter-based SFE achieves 30-GHz bandwidth while consuming 49.4 mW from a 0.95-V supply. The measured spurious free dynamic range (SFDR) and signal-to-noise and -distortion ratio (SNDR) at 50-GHz input are 46.9 dB and 36.1 dB, respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"81-84"},"PeriodicalIF":2.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-18DOI: 10.1109/LSSC.2025.3551357
Young-Ju Oh;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong
This letter presents a compact single-stage buffer amplifier designed to drive a wide range of capacitive loads (CL). To further reduce power consumption and silicon area compared to previous single-stage rail-to-rail amplifiers, this letter proposes an asymmetric rail-to-rail class AB output structure. To achieve a high slew rate, the proposed amplifier employs positive feedback loops and a dynamic floating node. A prototype chip successfully drove a wide range of CL, from 250 pF to 15 nF, while achieving a fast transient response. The chip was fabricated using a 0.18-$mu $ m CMOS process.
这封信介绍了一个紧凑的单级缓冲放大器，设计用于驱动大范围的容性负载（CL）。与以前的单级轨对轨放大器相比，为了进一步降低功耗和硅面积，本信函提出了不对称轨对轨级AB输出结构。为了实现高摆率，该放大器采用了正反馈回路和动态浮动节点。原型芯片成功地驱动了宽范围的CL，从250 pF到15 nF，同时实现了快速的瞬态响应。该芯片采用0.18- $mu $ m CMOS工艺制备。
{"title":"Compact Single-Stage Input and Output Rail-to-Rail Class AB Buffer Amplifier With an Asymmetric Output Structure","authors":"Young-Ju Oh;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong","doi":"10.1109/LSSC.2025.3551357","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3551357","url":null,"abstract":"This letter presents a compact single-stage buffer amplifier designed to drive a wide range of capacitive loads (CL). To further reduce power consumption and silicon area compared to previous single-stage rail-to-rail amplifiers, this letter proposes an asymmetric rail-to-rail class AB output structure. To achieve a high slew rate, the proposed amplifier employs positive feedback loops and a dynamic floating node. A prototype chip successfully drove a wide range of CL, from 250 pF to 15 nF, while achieving a fast transient response. The chip was fabricated using a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"73-76"},"PeriodicalIF":2.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a global resonant clocking mesh architecture utilizing backside metal layers in an 18A class technology. Rotary traveling wave oscillators are implemented to provide synchronous low-skew, low-jitter, and 50% duty cycle clocks across a graphics core. To provide dynamic frequency and voltage scaling capabilities across a wide range of operating conditions, a high-speed fractional divider is designed. The proposed architecture is implemented on a 1.6 mm $times $ 1.6 mm graphics core achieving FoMJ of 246 dB FoMT 190.3dBc/Hz.
这封信介绍了一个利用18A级技术的背面金属层的全局谐振时钟网格架构。旋转行波振荡器的实现，以提供同步低斜，低抖动，和50%占空比时钟跨图形核心。为了在广泛的工作条件下提供动态频率和电压缩放能力，设计了高速分数分压器。所提出的架构在1.6 mm × 1.6 mm图形内核上实现，实现了246 dB的FoMJ 190.3dBc/Hz。
{"title":"A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology","authors":"Ragh Kuttappa;Vinayak Honkote;Amreesh Rao;Gaurav Kamalkar;Kailash Chandrashekar;Eric Finley;Chaitanya Sankuratri;Faran Rafiq;Robert Orton;Nils Hernandez;Anuradha Srinivasan;Tanay Karnik","doi":"10.1109/LSSC.2025.3552251","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3552251","url":null,"abstract":"This letter presents a global resonant clocking mesh architecture utilizing backside metal layers in an 18A class technology. Rotary traveling wave oscillators are implemented to provide synchronous low-skew, low-jitter, and 50% duty cycle clocks across a graphics core. To provide dynamic frequency and voltage scaling capabilities across a wide range of operating conditions, a high-speed fractional divider is designed. The proposed architecture is implemented on a 1.6 mm <inline-formula> <tex-math>$times $ </tex-math></inline-formula> 1.6 mm graphics core achieving FoMJ of 246 dB FoMT 190.3dBc/Hz.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"85-88"},"PeriodicalIF":2.2,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter introduces an active reflector for D-band communication utilizing 122-GHz wireless power transfer (WPT). The reflector consists of rectifiers with an integrated low-pass filter (LPF), an IF-band power combining network, and an 1-port amplifier composed of a circulator and IF-band amplifiers. The proposed rectifier not only works as an RF-DC converter but also operates as a self-heterodyne mixer by using the 122 GHz WPT signal as a LO. Since the rectifier operates in a fully passive manner, it can simultaneously perform the upconversion and downconversion required for Tx and Rx operations. The IF signal obtained from downconversion is efficiently amplified and then reinput into the IF distributing network and rectifier after 1-port amplifier for upconversion and reflectively transmission in the specular direction. According to probe measurements, the rectifier achieves a power conversion efficiency (PCE) of 12.2% with an input power of 9.3 dBm, and conversion gains of −15.9 and −17.7 dB for Tx and Rx modes, respectively. Additionally, the proposed rectifier supports a data rate of 48 Gb/s with a 64QAM modulation scheme and an 8-GHz bandwidth for both Tx and Rx.
{"title":"A 122 GHz Wirelessly Powered Active Reflector for D-Band Communications","authors":"Michihiro Ide;Keito Yuasa;Sena Kato;Shu Date;Takashi Tomura;Kenichi Okada;Atsushi Shirane","doi":"10.1109/LSSC.2025.3551244","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3551244","url":null,"abstract":"This letter introduces an active reflector for D-band communication utilizing 122-GHz wireless power transfer (WPT). The reflector consists of rectifiers with an integrated low-pass filter (LPF), an IF-band power combining network, and an 1-port amplifier composed of a circulator and IF-band amplifiers. The proposed rectifier not only works as an RF-DC converter but also operates as a self-heterodyne mixer by using the 122 GHz WPT signal as a LO. Since the rectifier operates in a fully passive manner, it can simultaneously perform the upconversion and downconversion required for Tx and Rx operations. The IF signal obtained from downconversion is efficiently amplified and then reinput into the IF distributing network and rectifier after 1-port amplifier for upconversion and reflectively transmission in the specular direction. According to probe measurements, the rectifier achieves a power conversion efficiency (PCE) of 12.2% with an input power of 9.3 dBm, and conversion gains of −15.9 and −17.7 dB for Tx and Rx modes, respectively. Additionally, the proposed rectifier supports a data rate of 48 Gb/s with a 64QAM modulation scheme and an 8-GHz bandwidth for both Tx and Rx.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"97-100"},"PeriodicalIF":2.2,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143835458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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