Pub Date : 2023-11-15DOI: 10.1109/LSSC.2023.3332766
Andrea Bilato;Ibrahim Petricli;Andrea Mazzanti
A D-band power upconverter in a 55-nm SiGe BiCMOS is presented. The low-output resistance of a switching quad is identified as a limiting factor to mixer power generation in D-band, and common-base transistors are stacked for output power enhancement. Moreover, the current clamping mechanism is exploited to scale the average supply current with output power, improving the efficiency in back-off. Experimental results demonstrate $ {P_{mathrm{ sat}}},,{=}$ 6.3 dBm and ${oP_{mathrm{ 1dB}}},,{=}$ 4.5 dBm at 140 GHz, with efficiency of 3.05% and 2.47%, respectively. The power consumption, from a 2-V supply, rises from 70 mW at the quiescent point to 140 mW at $ {P_{mathrm{ sat}}}$ . The measured output power and efficiency compare favorably against previous works.
{"title":"SiGe BiCMOS D-Band Heterodyne Power Mixer With Back-Off Efficiency Enhanced by Current Clamping","authors":"Andrea Bilato;Ibrahim Petricli;Andrea Mazzanti","doi":"10.1109/LSSC.2023.3332766","DOIUrl":"10.1109/LSSC.2023.3332766","url":null,"abstract":"A D-band power upconverter in a 55-nm SiGe BiCMOS is presented. The low-output resistance of a switching quad is identified as a limiting factor to mixer power generation in D-band, and common-base transistors are stacked for output power enhancement. Moreover, the current clamping mechanism is exploited to scale the average supply current with output power, improving the efficiency in back-off. Experimental results demonstrate \u0000<inline-formula> <tex-math>$ {P_{mathrm{ sat}}},,{=}$ </tex-math></inline-formula>\u00006.3 dBm and \u0000<inline-formula> <tex-math>${oP_{mathrm{ 1dB}}},,{=}$ </tex-math></inline-formula>\u00004.5 dBm at 140 GHz, with efficiency of 3.05% and 2.47%, respectively. The power consumption, from a 2-V supply, rises from 70 mW at the quiescent point to 140 mW at \u0000<inline-formula> <tex-math>$ {P_{mathrm{ sat}}}$ </tex-math></inline-formula>\u0000. The measured output power and efficiency compare favorably against previous works.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135759394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents an SRAM-based compute-in-memory (CIM) macro that uses 1-bit $Delta Sigma $ modulators to convert input and output activations to binary pulse waveform. The SRAM macro uses switched-capacitors for vector matrix multiplications and together with binary input activation improves linearity compared to current-domain SRAM CIM macros and allows reconfigurable activation resolution. The proposed macro is fabricated in 65 nm and benchmarked on MNIST and CIFAR-10 datasets with accuracies of 98.67% and 89.85%, respectively, with energy-efficiency in the range of 15.4–138.6 TOPS/W.
{"title":"SRAM In-Memory Computing Macro With Delta-Sigma Modulator-Based Variable-Resolution Activation","authors":"Vasundhara Damodaran;Ziyu Liu;Jian Meng;Jae-Sun Seo;Arindam Sanyal","doi":"10.1109/LSSC.2023.3327213","DOIUrl":"10.1109/LSSC.2023.3327213","url":null,"abstract":"This letter presents an SRAM-based compute-in-memory (CIM) macro that uses 1-bit \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 modulators to convert input and output activations to binary pulse waveform. The SRAM macro uses switched-capacitors for vector matrix multiplications and together with binary input activation improves linearity compared to current-domain SRAM CIM macros and allows reconfigurable activation resolution. The proposed macro is fabricated in 65 nm and benchmarked on MNIST and CIFAR-10 datasets with accuracies of 98.67% and 89.85%, respectively, with energy-efficiency in the range of 15.4–138.6 TOPS/W.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135156836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-19DOI: 10.1109/LSSC.2023.3326087
Sandeep Reddy Kukunuru;Loai G. Salem
This letter introduces a pulser topology that allows switched-capacitor adiabatic drivers (SCADs) to exploit an H-bridge for doubling the output voltage swing across an ultrasonic transducer (UT) from $V_{DD}$ to $2V_{DD}$ . The topology enables a fourfold increase in the output power of an $N$ -step SCAD while reducing the switching loss of the internal capacitance of a UT by $sim 10times $ . A periodically switched flying ladder of capacitors is employed to balance the voltages across the $N -1$ charge-recycling capacitors in an $N$ -step SCAD at integer multiples of $V_{DD}/N$ against the imbalance produced by an H-bridge or a UT of high power factor. In this way, an H-bridge can be combined with an SCAD to flip the polarity of the voltage applied across a UT every half cycle, effectively lowering the number of required charge-recycling capacitors and intermediate switches for a given number of steps by 2. Measurements of a 0.18- $mu text{m}$ CMOS prototype demonstrate a switching loss reduction of up to 87.2% and a peak ultrasonic driving efficiency of 92.9%.
本文介绍了一种脉冲发生器拓扑结构，该拓扑结构允许开关电容绝热驱动器(scad)利用h桥将超声波换能器(UT)从$V_{DD}$到$2V_{DD}$的输出电压摆幅加倍。该拓扑结构使$N$ -step SCAD的输出功率增加四倍，同时将UT内部电容的开关损耗降低$sim 10times $。在$N$级SCAD中，采用周期性切换的电容器飞梯来平衡$N -1$电荷回收电容器之间的电压，其电压为$V_{DD}/N$的整数倍，以对抗h桥或高功率因数UT产生的不平衡。通过这种方式，h桥可以与SCAD相结合，每半个周期翻转施加在UT上的电压的极性，有效地将给定数量的步骤所需的电荷回收电容器和中间开关的数量减少2。测量0.18- $mu text{m}$ CMOS原型表明开关损耗降低高达87.2% and a peak ultrasonic driving efficiency of 92.9%.
{"title":"An 11-Level Adiabatic Ultrasonic Pulser Achieving 87.2% Dynamic Power Reduction","authors":"Sandeep Reddy Kukunuru;Loai G. Salem","doi":"10.1109/LSSC.2023.3326087","DOIUrl":"10.1109/LSSC.2023.3326087","url":null,"abstract":"This letter introduces a pulser topology that allows switched-capacitor adiabatic drivers (SCADs) to exploit an H-bridge for doubling the output voltage swing across an ultrasonic transducer (UT) from \u0000<inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$2V_{DD}$ </tex-math></inline-formula>\u0000. The topology enables a fourfold increase in the output power of an \u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000-step SCAD while reducing the switching loss of the internal capacitance of a UT by \u0000<inline-formula> <tex-math>$sim 10times $ </tex-math></inline-formula>\u0000. A periodically switched flying ladder of capacitors is employed to balance the voltages across the \u0000<inline-formula> <tex-math>$N -1$ </tex-math></inline-formula>\u0000 charge-recycling capacitors in an \u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000-step SCAD at integer multiples of \u0000<inline-formula> <tex-math>$V_{DD}/N$ </tex-math></inline-formula>\u0000 against the imbalance produced by an H-bridge or a UT of high power factor. In this way, an H-bridge can be combined with an SCAD to flip the polarity of the voltage applied across a UT every half cycle, effectively lowering the number of required charge-recycling capacitors and intermediate switches for a given number of steps by 2. Measurements of a 0.18-\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 CMOS prototype demonstrate a switching loss reduction of up to 87.2% and a peak ultrasonic driving efficiency of 92.9%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135058583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-17DOI: 10.1109/LSSC.2023.3325186
Hamid Jafari Sharemi;Mehrdad Sharif Bakhtiar
This letter presents a new approach to low-power, low-latency, and frequency-selective wake-up receivers. A novel architecture is introduced to achieve frequency domain selectivity, including analog techniques, that enable data detection without the need for power-hungry digital processing. A two-mode duty cycling is also utilized, which helps reduce the power consumption of the receiver significantly with negligible latency. A prototype of the proposed receiver is fabricated and verified in a 180-nm CMOS process. The fabricated chipset achieves a sensitivity of −84.9 dBm with 4.32-ms wake-up latency and drains an average current of $12.2 ~mu text{A}$ . Interference tests show an outstanding signal-to-interference ratio (SIR) of −42/−49/−51 dB at 0.11%/0.22%/0.33% frequency offset from the carrier, confirming the interference immunity of the proposed design.
{"title":"A New Scheme for Low-Power, Low-Latency, and Interferer-Tolerant Wake-Up Receivers","authors":"Hamid Jafari Sharemi;Mehrdad Sharif Bakhtiar","doi":"10.1109/LSSC.2023.3325186","DOIUrl":"10.1109/LSSC.2023.3325186","url":null,"abstract":"This letter presents a new approach to low-power, low-latency, and frequency-selective wake-up receivers. A novel architecture is introduced to achieve frequency domain selectivity, including analog techniques, that enable data detection without the need for power-hungry digital processing. A two-mode duty cycling is also utilized, which helps reduce the power consumption of the receiver significantly with negligible latency. A prototype of the proposed receiver is fabricated and verified in a 180-nm CMOS process. The fabricated chipset achieves a sensitivity of −84.9 dBm with 4.32-ms wake-up latency and drains an average current of \u0000<inline-formula> <tex-math>$12.2 ~mu text{A}$ </tex-math></inline-formula>\u0000. Interference tests show an outstanding signal-to-interference ratio (SIR) of −42/−49/−51 dB at 0.11%/0.22%/0.33% frequency offset from the carrier, confirming the interference immunity of the proposed design.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135007444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-13DOI: 10.1109/LSSC.2023.3324589
M. M. Abdevand;D. Livornesi;A. E. Vergani;F. Piscitelli;E. Mammei;E. Bonizzoni;P. Malcovati;P. Pulici
A fully analog interface circuit based on closed-loop biasing and noise canceling techniques, fabricated in a 130-nm BiCMOS technology, is presented in this letter. The proposed interface circuit is able to precisely bias the sensor and read out the resulting signal in two frequency ranges (low-frequency (LF) range from dc to 375 kHz and high-frequency range from 1 kHz to 130 MHz). In the LF range, thanks to a dedicated noise-canceling technique, the achieved integrated input-referred noise is reduced from 7.3 $mu text{V}_{mathrm{ rms}}$ to 2.8 $mu text{V}_{mathrm{ rms}}$ in the 100-Hz to 1-kHz band and from 14.2 $mu text{V}_{mathrm{ rms}}$ to 4.6 $mu text{V}_{mathrm{ rms}}$ in the 1–100-kHz band, respectively. The fabricated chip features an active area of 1.11 mm2 and consumes 172 mW of power, including the 36 mW required to bias the sensor.
{"title":"A 0.13-μm BiCMOS, 130-MHz Bandwidth Interface Circuit With Noise Canceling for HDD Fly-Height Resistive Sensors","authors":"M. M. Abdevand;D. Livornesi;A. E. Vergani;F. Piscitelli;E. Mammei;E. Bonizzoni;P. Malcovati;P. Pulici","doi":"10.1109/LSSC.2023.3324589","DOIUrl":"10.1109/LSSC.2023.3324589","url":null,"abstract":"A fully analog interface circuit based on closed-loop biasing and noise canceling techniques, fabricated in a 130-nm BiCMOS technology, is presented in this letter. The proposed interface circuit is able to precisely bias the sensor and read out the resulting signal in two frequency ranges (low-frequency (LF) range from dc to 375 kHz and high-frequency range from 1 kHz to 130 MHz). In the LF range, thanks to a dedicated noise-canceling technique, the achieved integrated input-referred noise is reduced from 7.3 \u0000<inline-formula> <tex-math>$mu text{V}_{mathrm{ rms}}$ </tex-math></inline-formula>\u0000 to 2.8 \u0000<inline-formula> <tex-math>$mu text{V}_{mathrm{ rms}}$ </tex-math></inline-formula>\u0000 in the 100-Hz to 1-kHz band and from 14.2 \u0000<inline-formula> <tex-math>$mu text{V}_{mathrm{ rms}}$ </tex-math></inline-formula>\u0000 to 4.6 \u0000<inline-formula> <tex-math>$mu text{V}_{mathrm{ rms}}$ </tex-math></inline-formula>\u0000 in the 1–100-kHz band, respectively. The fabricated chip features an active area of 1.11 mm2 and consumes 172 mW of power, including the 36 mW required to bias the sensor.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136302120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-13DOI: 10.1109/LSSC.2023.3323857
Daniel Widmann;Tobias Tannert;Markus Grözing;Manfred Berroth
To enhance the performance of digital-to-analog converters (DACs), time interleaving by an analog multiplexer (AMUX) provides a powerful concept. Next to an increased sampling rate, potential signal quality improvement as well as a sin( ${x}$ )/ ${x}$ roll-off shift due to the nonlinear switching operation enabling a true bandwidth extension can be achieved. In this letter, an integrated AMUX in a 28-nm CMOS technology is presented. The fundamental roll-off shift is deduced from a general mathematical model. In measurements, the roll-off shift as well as improvements of the edge jitter of pulse-amplitude modulated (PAM) signals due to the AMUX are demonstrated at a sampling rate of 100GS/s. Compared to single-DAC operation at 50GS/s, the total edge jitter of a PAM-2 signal can be improved from a standard deviation of about 1.27ps to about 0.56ps at 100GS/s with AMUX operation in the given system. Finally, switching operation of the AMUX at 126GS/s is shown demonstrating the potential of the concept.
{"title":"Analog Multiplexer for Performance Enhancement of Digital-to-Analog Converters and Experimental 2-to-1 Time Interleaving in 28-nm FD-SOI CMOS","authors":"Daniel Widmann;Tobias Tannert;Markus Grözing;Manfred Berroth","doi":"10.1109/LSSC.2023.3323857","DOIUrl":"10.1109/LSSC.2023.3323857","url":null,"abstract":"To enhance the performance of digital-to-analog converters (DACs), time interleaving by an analog multiplexer (AMUX) provides a powerful concept. Next to an increased sampling rate, potential signal quality improvement as well as a sin(\u0000<inline-formula> <tex-math>${x}$ </tex-math></inline-formula>\u0000)/\u0000<inline-formula> <tex-math>${x}$ </tex-math></inline-formula>\u0000 roll-off shift due to the nonlinear switching operation enabling a true bandwidth extension can be achieved. In this letter, an integrated AMUX in a 28-nm CMOS technology is presented. The fundamental roll-off shift is deduced from a general mathematical model. In measurements, the roll-off shift as well as improvements of the edge jitter of pulse-amplitude modulated (PAM) signals due to the AMUX are demonstrated at a sampling rate of 100GS/s. Compared to single-DAC operation at 50GS/s, the total edge jitter of a PAM-2 signal can be improved from a standard deviation of about 1.27ps to about 0.56ps at 100GS/s with AMUX operation in the given system. Finally, switching operation of the AMUX at 126GS/s is shown demonstrating the potential of the concept.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136304261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents a second-order continuous-time delta-sigma (CT- $Delta Sigma $ )-based analog front-end (AFE) for biopotential sensor interfaces. High linearity is achieved by using a current balanced $G_{m,1}$ input stage with gain-boosting and cascode techniques. Low-frequency chopping embedded in gain-boosting OTAs breaks the limitation of chopping frequency in conventional CT- $Delta Sigma $ ADCs and mitigates flicker noise without reducing the input impedance. In the second stage, the closed-loop $G_{m,2}$ -OTA-C proportional integrator (PI) relaxes the linearity requirements of the OTA and eliminates the additional active adder. Fabricated in a standard 0.18- $mu text{m}$ CMOS technology, this direct-digitization AFE achieves 94.9-dB peak SNDR, $335 rm mV_{pp}$ linear input range, and 4.7- $text{G}Omega $ input impedance at 50 Hz with $64times $ reduction in the chopping frequency.
{"title":"A 15.5-ENOB 335 mVPP-Linear-Input-Range 4.7-GΩ-Input-Impedance CT-ΔΣM Analog Front-End With Embedded Low-Frequency Chopping","authors":"Yijie Li;Weiqi Zhi;Yuying Li;Jianhong Zhou;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2023.3318815","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3318815","url":null,"abstract":"This article presents a second-order continuous-time delta-sigma (CT-\u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000)-based analog front-end (AFE) for biopotential sensor interfaces. High linearity is achieved by using a current balanced \u0000<inline-formula> <tex-math>$G_{m,1}$ </tex-math></inline-formula>\u0000 input stage with gain-boosting and cascode techniques. Low-frequency chopping embedded in gain-boosting OTAs breaks the limitation of chopping frequency in conventional CT-\u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 ADCs and mitigates flicker noise without reducing the input impedance. In the second stage, the closed-loop \u0000<inline-formula> <tex-math>$G_{m,2}$ </tex-math></inline-formula>\u0000-OTA-C proportional integrator (PI) relaxes the linearity requirements of the OTA and eliminates the additional active adder. Fabricated in a standard 0.18-\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 CMOS technology, this direct-digitization AFE achieves 94.9-dB peak SNDR, \u0000<inline-formula> <tex-math>$335 rm mV_{pp}$ </tex-math></inline-formula>\u0000 linear input range, and 4.7-\u0000<inline-formula> <tex-math>$text{G}Omega $ </tex-math></inline-formula>\u0000 input impedance at 50 Hz with \u0000<inline-formula> <tex-math>$64times $ </tex-math></inline-formula>\u0000 reduction in the chopping frequency.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68079040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-19DOI: 10.1109/LSSC.2023.3306369
Nicolas Butzen;Harish Krishnamurthy;Zakir Ahmed;Sheldon Weng;Krishnan Ravichandran;Michael Zelikson;James Tschanz;Jonathan Douglas
This letter introduces the phase-merging turbo (PMT) technique, a method which significantly augments the output current capability of a continuous scalable conversion-ratio (CSCR) switched-capacitor voltage regulator (SCVR). The research also proposes a unique method for implementing communication-free ganging with these converters, enhancing their scalability across a wide range of power domain sizes. Fabricated using a 4-nm class CMOS technology, this study achieves a current density of 26 A/mm2 for monolithic capacitive voltage regulators, and a peak efficiency of 88.5%.
{"title":"A Monolithic 26 A/mm2 Continuously Scalable Conversion Ratio Switched-Capacitor Converter With Phase-Merging Turbo and Communication-Less Ganging","authors":"Nicolas Butzen;Harish Krishnamurthy;Zakir Ahmed;Sheldon Weng;Krishnan Ravichandran;Michael Zelikson;James Tschanz;Jonathan Douglas","doi":"10.1109/LSSC.2023.3306369","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3306369","url":null,"abstract":"This letter introduces the phase-merging turbo (PMT) technique, a method which significantly augments the output current capability of a continuous scalable conversion-ratio (CSCR) switched-capacitor voltage regulator (SCVR). The research also proposes a unique method for implementing communication-free ganging with these converters, enhancing their scalability across a wide range of power domain sizes. Fabricated using a 4-nm class CMOS technology, this study achieves a current density of 26 A/mm2 for monolithic capacitive voltage regulators, and a peak efficiency of 88.5%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68079042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-13DOI: 10.1109/LSSC.2023.3314795
Heejun Lee;Hyunki Han;Hyun-Sik Kim
This letter presents a 4-to-42-V input and 3.3-V output dc–dc buck converter for battery-powered automotive uses. Pulse-frequency modulation (PFM) is a common scheme employed to reduce quiescent current $(I_{Q})$ and mitigate battery drain. However, sustaining the bootstrap voltage $(V_{B})$ , essential for activating power switches, becomes arduous at elevated temperatures due to significant leakage currents, particularly when the switching frequency is low in no-load scenarios. To address this issue, this letter proposes a leakage-emulating oscillator-based (LEOB) refresher that stabilizes $V_{B}$ , even at temperatures as high as +125 °C. Additionally, an anti-deadlock self-bias supply is presented to further reduce $I_{Q}$ while ensuring fault tolerance. The chip, fabricated in a 180-nm BCD process, exhibits a low $I_{Q}$ of 3.2 $mu text{A}$ and a peak efficiency of 95.5% (93.3%) at $V_{mathrm{ IN}},,=$ 24 V (42 V), with demonstrated stability of $V_{B}$ from −40 °C to +125 °C.
{"title":"A 4-to-42-V Input 3.3-V Output Self-Biased DC–DC Buck Converter Featuring Leakage-Emulated Bootstrap Voltage Refresher and Anti-Deadlock","authors":"Heejun Lee;Hyunki Han;Hyun-Sik Kim","doi":"10.1109/LSSC.2023.3314795","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3314795","url":null,"abstract":"This letter presents a 4-to-42-V input and 3.3-V output dc–dc buck converter for battery-powered automotive uses. Pulse-frequency modulation (PFM) is a common scheme employed to reduce quiescent current \u0000<inline-formula> <tex-math>$(I_{Q})$ </tex-math></inline-formula>\u0000 and mitigate battery drain. However, sustaining the bootstrap voltage \u0000<inline-formula> <tex-math>$(V_{B})$ </tex-math></inline-formula>\u0000, essential for activating power switches, becomes arduous at elevated temperatures due to significant leakage currents, particularly when the switching frequency is low in no-load scenarios. To address this issue, this letter proposes a leakage-emulating oscillator-based (LEOB) refresher that stabilizes \u0000<inline-formula> <tex-math>$V_{B}$ </tex-math></inline-formula>\u0000, even at temperatures as high as +125 °C. Additionally, an anti-deadlock self-bias supply is presented to further reduce \u0000<inline-formula> <tex-math>$I_{Q}$ </tex-math></inline-formula>\u0000 while ensuring fault tolerance. The chip, fabricated in a 180-nm BCD process, exhibits a low \u0000<inline-formula> <tex-math>$I_{Q}$ </tex-math></inline-formula>\u0000 of 3.2 \u0000<inline-formula> <tex-math>$mu text{A}$ </tex-math></inline-formula>\u0000 and a peak efficiency of 95.5% (93.3%) at \u0000<inline-formula> <tex-math>$V_{mathrm{ IN}},,=$ </tex-math></inline-formula>\u0000 24 V (42 V), with demonstrated stability of \u0000<inline-formula> <tex-math>$V_{B}$ </tex-math></inline-formula>\u0000 from −40 °C to +125 °C.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2023-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68079039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-12DOI: 10.1109/LSSC.2023.3314458
L. Zohar;I. Shternberg;B. Khamaisi;A. Nazimov;A. Ben-Bassat;O. Degani
This letter describes the reliability characterization process of switched capacitor digital power amplifier (SCDPA) manufactured in CMOS acrlong 16FF technology. Power amplifiers (PAs) operate at RF frequencies (2.4 and 5–7 GHz) in which the instantaneous voltage on the transistor terminals might exceed the maximum rated voltage, Vmax allowed by the process technology. Since the available technology models for reliability degradation under RF conditions are limited, a detailed design analysis for possible failure mechanisms was done, followed by product data collection while operating in RF. In this letter, we describe this process, including SCDPA reliability risk assessment and stress experiments. We explain how in SCDPA the VDD voltage is critical for failure acceleration and not the output power (as in analog power amplifier (PA). We also show that the initial design suffered from pMOS negative bias temperature instability (NBTI) which resulted in 2nd harmonics degradation. The NBTI issue was overcome by a novel design in which the bulk voltage is dynamically changed to lower the effective source–gate voltage (Vsg) on the SCDPA pMOS transistors. To stress the SCDPA, we used a setup in which the SCDPA transmits a continuous waveform (CW) along with voltage and temperature acceleration. Finally, we show how the dynamic bulk voltage solution was successful in overcoming the NBTI degradation.
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