Pub Date : 2024-01-24DOI: 10.1109/LSSC.2024.3358083
Netanel Desta;Emanuel Cohen
This work presents a second-order parallel N-path bandpass filter implemented in 250-nm depletion-mode GaN process leveraging an integrated baseband bootstrapping technique for high-in-band linearity performance. The bootstrap circuit improves in-band compression by 20 dB by preventing the opening of the gate parasitic diode of the GaN switch. The filter achieves in-band P1dB of 31 dBm for a 26-MHz bandwidth around 1-GHz center frequency along with 2-dB insertion loss between 0.3-1.8 GHz with an out-of-band rejection of 16 dB. The chip occupies an area of 9.2 mm2 and consumes 4.9 Watt.
{"title":"A Bootstrapped 250-nm GaN MMIC N-Path Filter With a 31 dBm In-Band P1dB","authors":"Netanel Desta;Emanuel Cohen","doi":"10.1109/LSSC.2024.3358083","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3358083","url":null,"abstract":"This work presents a second-order parallel N-path bandpass filter implemented in 250-nm depletion-mode GaN process leveraging an integrated baseband bootstrapping technique for high-in-band linearity performance. The bootstrap circuit improves in-band compression by 20 dB by preventing the opening of the gate parasitic diode of the GaN switch. The filter achieves in-band P1dB of 31 dBm for a 26-MHz bandwidth around 1-GHz center frequency along with 2-dB insertion loss between 0.3-1.8 GHz with an out-of-band rejection of 16 dB. The chip occupies an area of 9.2 mm2 and consumes 4.9 Watt.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"66-69"},"PeriodicalIF":2.7,"publicationDate":"2024-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139727465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-24DOI: 10.1109/LSSC.2024.3357810
Liang Zhang;Fengjun Chen;Xu Cheng;Jiang-An Han;Xianhu Luo;Changxing Lin;Wei Su
In this letter, a compact multifunctional 180° hybrid suitable for subharmonic in-phase/quadrature (I/Q) mixers is proposed. To feed LO and RF signals at different frequencies and distribute dc supply, the hybrid combines an out-of-phase dual balun, two in-phase power dividers based on T-junction and coupled lines, and four zero-ohm transmission lines (ZTLs) into a single passive component. Chip size, insertion loss, and bandwidth can all be improved by reducing the number of passive components cascaded in the circuit. The proposed hybrid’s footprint is further minimized by employing redundant line and compensation capacitor techniques. In a 130-nm SiGe BiCMOS technology, two proof-of-concept subharmonic I/Q downconversion resistive mixers with/without an on-chip LO quadrupler are implemented. Both mixers feature wideband HBT-based IF amplifiers and emitter followers, which eliminate the need for dc-blocking capacitors that constrict the IF bandwidth. The mixer, without an integrated LO multiplier, occupies an area of $0.685times 0.692,,{mathrm{ mm}}^{2}$ and achieves a measured conversion gain of approximately 0 dB from 255 to 310 GHz. The mixer with an on-chip LO quadrupler exhibits a conversion gain of approximately −1 dB from 270 to 300 GHz and a 3-dB IF bandwidth from 0.01 to 7 GHz. Additionally, the measured image rejection ratio (IRR) is greater than 20 dB within the operating frequencies.
本文提出了一种适用于次谐波同相/正交（I/Q）混频器的紧凑型多功能 180° 混合器。为了馈入不同频率的 LO 和 RF 信号并分配直流电源，该混合器将一个相位外双平衡器、两个基于 T 型结和耦合线的同相功率分配器以及四根零欧姆传输线 (ZTL) 组合成一个无源元件。通过减少电路中级联的无源元件数量，芯片尺寸、插入损耗和带宽均可得到改善。通过采用冗余线路和补偿电容器技术，进一步减小了拟议混合电路的占地面积。在 130 纳米 SiGe BiCMOS 技术中，实现了两个具有/不具有片上 LO 四倍频器的亚谐波 I/Q 下变频电阻混频器的概念验证。这两款混频器都采用了基于 HBT 的宽带中频放大器和发射极跟随器，无需使用限制中频带宽的直流阻断电容器。不带集成 LO 倍增器的混频器占地面积为 0.685/times 0.692,,{mathrm{mm}}^{2}$，在 255 至 310 GHz 范围内实现了约 0 dB 的实测转换增益。带有片上 LO 四倍频器的混频器在 270 至 300 GHz 范围内的转换增益约为 -1 dB，在 0.01 至 7 GHz 范围内的中频带宽为 3 dB。此外，所测得的图像抑制比 (IRR) 在工作频率范围内大于 20 dB。
{"title":"Compact Multifunctional 180° Hybrid-Based 300-GHz Subharmonic I/Q Downconversion Resistive Mixers in 130-nm SiGe Process","authors":"Liang Zhang;Fengjun Chen;Xu Cheng;Jiang-An Han;Xianhu Luo;Changxing Lin;Wei Su","doi":"10.1109/LSSC.2024.3357810","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3357810","url":null,"abstract":"In this letter, a compact multifunctional 180° hybrid suitable for subharmonic in-phase/quadrature (I/Q) mixers is proposed. To feed LO and RF signals at different frequencies and distribute dc supply, the hybrid combines an out-of-phase dual balun, two in-phase power dividers based on T-junction and coupled lines, and four zero-ohm transmission lines (ZTLs) into a single passive component. Chip size, insertion loss, and bandwidth can all be improved by reducing the number of passive components cascaded in the circuit. The proposed hybrid’s footprint is further minimized by employing redundant line and compensation capacitor techniques. In a 130-nm SiGe BiCMOS technology, two proof-of-concept subharmonic I/Q downconversion resistive mixers with/without an on-chip LO quadrupler are implemented. Both mixers feature wideband HBT-based IF amplifiers and emitter followers, which eliminate the need for dc-blocking capacitors that constrict the IF bandwidth. The mixer, without an integrated LO multiplier, occupies an area of \u0000<inline-formula> <tex-math>$0.685times 0.692,,{mathrm{ mm}}^{2}$ </tex-math></inline-formula>\u0000 and achieves a measured conversion gain of approximately 0 dB from 255 to 310 GHz. The mixer with an on-chip LO quadrupler exhibits a conversion gain of approximately −1 dB from 270 to 300 GHz and a 3-dB IF bandwidth from 0.01 to 7 GHz. Additionally, the measured image rejection ratio (IRR) is greater than 20 dB within the operating frequencies.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"86-89"},"PeriodicalIF":2.7,"publicationDate":"2024-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139942713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-15DOI: 10.1109/LSSC.2024.3354037
Yu-Teng Chang;Wen-Jie Lin
In this letter, a 28-GHz low-power variable-gain low-noise amplifier (VGLNA) is designed for fifth-generation millimeter-wave applications and implemented using the twice current reuse (CR) technique and a tunable load. This amplifier employing the twice CR technique exhibits low dc power while delivering enhanced gain. The gain control (GC) range of the amplifier is extended using a tunable load, which is composed of a pMOS device and an inductance, and the phase variation is improved by resonating the inductance with the parasitic capacitance of the intrastage CR amplifier. Because the tunable load selectively attenuates only ac signals, ${mathrm{ IP}}_{1 rm dB}$ can be proportionally increased by reducing the gain. At 28 GHz, the measured gain and GC range are 21.2 and 13.8 dB, respectively. In the entire GC range, the measured ${mathrm{ IP}}_{1 rm dB}$ ranges from −20 to −7 dBm, the noise figure (NF) ranges from 3.7 to 6.8 dB, and the RMS phase error is 1.05° at 28 GHz. At a supply voltage of 1.2 V, the dc power of the proposed VGLNA is only 5.0 mW. These results highlight that the proposed VGLNA has the lowest dc power, higher gain, and better figure of merit compared to other works.
{"title":"A 28-GHz Low-Power Variable-Gain Low-Noise Amplifier Using Twice Current Reuse Technique","authors":"Yu-Teng Chang;Wen-Jie Lin","doi":"10.1109/LSSC.2024.3354037","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3354037","url":null,"abstract":"In this letter, a 28-GHz low-power variable-gain low-noise amplifier (VGLNA) is designed for fifth-generation millimeter-wave applications and implemented using the twice current reuse (CR) technique and a tunable load. This amplifier employing the twice CR technique exhibits low dc power while delivering enhanced gain. The gain control (GC) range of the amplifier is extended using a tunable load, which is composed of a pMOS device and an inductance, and the phase variation is improved by resonating the inductance with the parasitic capacitance of the intrastage CR amplifier. Because the tunable load selectively attenuates only ac signals, \u0000<inline-formula> <tex-math>${mathrm{ IP}}_{1 rm dB}$ </tex-math></inline-formula>\u0000 can be proportionally increased by reducing the gain. At 28 GHz, the measured gain and GC range are 21.2 and 13.8 dB, respectively. In the entire GC range, the measured \u0000<inline-formula> <tex-math>${mathrm{ IP}}_{1 rm dB}$ </tex-math></inline-formula>\u0000 ranges from −20 to −7 dBm, the noise figure (NF) ranges from 3.7 to 6.8 dB, and the RMS phase error is 1.05° at 28 GHz. At a supply voltage of 1.2 V, the dc power of the proposed VGLNA is only 5.0 mW. These results highlight that the proposed VGLNA has the lowest dc power, higher gain, and better figure of merit compared to other works.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"58-61"},"PeriodicalIF":2.7,"publicationDate":"2024-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-12DOI: 10.1109/LSSC.2024.3353381
D. Zagouri;A. Rimer;E. Emanovic;Y. Ninio;Y. Slezak;D. Jurisic;A. Fish;J. Shor
Photodiodes can be utilized for both image sensing and energy harvesting, but at opposite polarity. There have been numerous research works which have attempted a self-powered imager, by flipping the diodes and harvesting. However, the integration cycle in the image sensing(IS) process is very long and the chip cannot harvest while in this mode. In this letter, an event detector (ED) function is demonstrated in 180 nm, whereby the voltage across the photodiode is monitored during harvesting. If there is a significant change in this voltage, then an event is detected, and the chip can take a picture. Two types of EDs are proposed, which can function at average power as low as 0.2– $1 ~mu text{W}$ .
{"title":"A Photovoltaic Energy Harvester/Image Sensor Platform With Event Detection Capability in 180 nm","authors":"D. Zagouri;A. Rimer;E. Emanovic;Y. Ninio;Y. Slezak;D. Jurisic;A. Fish;J. Shor","doi":"10.1109/LSSC.2024.3353381","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3353381","url":null,"abstract":"Photodiodes can be utilized for both image sensing and energy harvesting, but at opposite polarity. There have been numerous research works which have attempted a self-powered imager, by flipping the diodes and harvesting. However, the integration cycle in the image sensing(IS) process is very long and the chip cannot harvest while in this mode. In this letter, an event detector (ED) function is demonstrated in 180 nm, whereby the voltage across the photodiode is monitored during harvesting. If there is a significant change in this voltage, then an event is detected, and the chip can take a picture. Two types of EDs are proposed, which can function at average power as low as 0.2–\u0000<inline-formula> <tex-math>$1 ~mu text{W}$ </tex-math></inline-formula>\u0000.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"62-65"},"PeriodicalIF":2.7,"publicationDate":"2024-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139676070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter describes a fully synthesizable fractional- $N$ multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relatively smaller number of delay cells. Since its structure is periodical, the corresponding predistortion look-up table (LUT)’s size could also be reduced. The proposed MDLL is implemented in a 65-nm CMOS process. The measured results show that the RO-DTC’s power normalized by operating frequency and tuning range is the lowest among other state-of-the-art works. The proposed MDLL achieves FoMs of −242.3 and −218.6 dB in integer- $N$ and fractional- $N$ operation modes at RF frequencies 1.04 and 1.0465 GHz. The core area is 0.0892 mm2.
{"title":"A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range","authors":"Hóngyè Huáng;Bangan Liu;Zezheng Liu;Dingxin Xu;Yuncheng Zhang;Waleed Madany;Junjun Qiu;Zheng Sun;Ashbir Aviat Fadila;Jian Pang;Zheng Li;Dongwon You;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2024.3352736","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3352736","url":null,"abstract":"This letter describes a fully synthesizable fractional-\u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000 multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relatively smaller number of delay cells. Since its structure is periodical, the corresponding predistortion look-up table (LUT)’s size could also be reduced. The proposed MDLL is implemented in a 65-nm CMOS process. The measured results show that the RO-DTC’s power normalized by operating frequency and tuning range is the lowest among other state-of-the-art works. The proposed MDLL achieves FoMs of −242.3 and −218.6 dB in integer-\u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000 and fractional-\u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000 operation modes at RF frequencies 1.04 and 1.0465 GHz. The core area is 0.0892 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"54-57"},"PeriodicalIF":2.7,"publicationDate":"2024-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10391060","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-09DOI: 10.1109/LSSC.2024.3351671
Hongyu Lu;Hossein Rahmanian Kooshkaki;Patrick P. Mercier
This letter presents a mixer-first RF receiver that: 1) nominally operates in a low-NF $N$ -path filter mode; 2) features an on-chip harmonic blocker detection circuit running in the background; 3) switches to a harmonic rejection mode upon detection of harmonic content; and 4) passively rejects harmonic blockers through a current-mode circuit that uses resistor sizing to set the amplitude of each path, but with capacitive termination to minimize conversion loss to 1.9 dB while providing a sharp, down-converted filter response. Implemented in 65nm CMOS, the receiver achieves 36/40-dB HR3/5,+21 dBm IIP3, +1 dBm blocker 1-dB compression point (B1dB) and 4/8-dB NF while consuming 10–23 mW.
这封信介绍了一种混频器优先射频接收器，它具有以下特点1) 名义上以低 NF $N$ 路径滤波器模式运行；2) 具有在后台运行的片上谐波阻断器检测电路；3) 在检测到谐波内容时切换到谐波抑制模式；4) 通过电流模式电路被动地抑制谐波阻断器，该电路使用电阻器大小来设置每条路径的振幅，但采用电容终端将转换损耗降至 1.9 dB，同时提供尖锐的下变频滤波器响应。该接收器采用 65nm CMOS 工艺，实现了 36/40 dB HR3/5、+21 dBm IIP3、+1 dBm Blocker 1 dB 压缩点 (B1dB) 和 4/8 dB NF，功耗为 10-23 mW。
{"title":"A Mixer-First Receiver With On-Demand Passive Harmonic Rejection","authors":"Hongyu Lu;Hossein Rahmanian Kooshkaki;Patrick P. Mercier","doi":"10.1109/LSSC.2024.3351671","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3351671","url":null,"abstract":"This letter presents a mixer-first RF receiver that: 1) nominally operates in a low-NF \u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000-path filter mode; 2) features an on-chip harmonic blocker detection circuit running in the background; 3) switches to a harmonic rejection mode upon detection of harmonic content; and 4) passively rejects harmonic blockers through a current-mode circuit that uses resistor sizing to set the amplitude of each path, but with capacitive termination to minimize conversion loss to 1.9 dB while providing a sharp, down-converted filter response. Implemented in 65nm CMOS, the receiver achieves 36/40-dB HR3/5,+21 dBm IIP3, +1 dBm blocker 1-dB compression point (B1dB) and 4/8-dB NF while consuming 10–23 mW.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"46-49"},"PeriodicalIF":2.7,"publicationDate":"2024-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139573142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a 100-Gb/s CMOS PAM-4 transimpedance amplifier (TIA) with multimilliampere maximum linear input current. A low-noise high-linearity TIA architecture is proposed, leveraging the reconfigurable front-end (FE) TIA and the continuous time linear equalizer (CTLE) synced at multiple gain modes. Implemented in a 28-nm CMOS technology, the TIA achieves bandwidth of more than 24 GHz with transimpedance gain of 65 dB $Omega $ , while showing an acrlong IRN current density of 10.4 pA/ $surd $ Hz. The maximum linear input current reaches 2.2 mApp and the total harmonic distortion (THD) is less than 3% for an output swing of 600 mV $_{rm pp, {mathrm{ diff}}}$ . The chip consumes power of 56 mW from 1.4 and 1.1-V supply.
本文介绍了一种具有多毫安最大线性输入电流的 100-Gb/s CMOS PAM-4 互阻抗放大器（TIA）。利用可重构前端 (FE) TIA 和在多种增益模式下同步的连续时间线性均衡器 (CTLE)，提出了一种低噪声高线性度 TIA 架构。该 TIA 采用 28-nm CMOS 技术实现，带宽超过 24 GHz，跨阻增益达到 65 dB，同时显示出 10.4 pA/ $surd $ Hz 的 acrlong IRN 电流密度。最大线性输入电流达到 2.2 mApp，输出摆幅为 600 mV $_{rm pp, {mathrm{ diff}}$ 时，总谐波失真（THD）小于 3%。芯片在 1.4 V 和 1.1 V 电源下的功耗为 56 mW。
{"title":"A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS","authors":"Shuaizhe Ma;Zhenyu Yin;Nianquan Ran;Yifei Xia;Ruixuan Yang;Chuanhao Yu;Songqin Xu;Binhao Wang;Nan Qi;Bing Zhang;Jingbo Shi;Xiaoyan Gui;Li Geng;Dan Li","doi":"10.1109/LSSC.2024.3351683","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3351683","url":null,"abstract":"This letter presents a 100-Gb/s CMOS PAM-4 transimpedance amplifier (TIA) with multimilliampere maximum linear input current. A low-noise high-linearity TIA architecture is proposed, leveraging the reconfigurable front-end (FE) TIA and the continuous time linear equalizer (CTLE) synced at multiple gain modes. Implemented in a 28-nm CMOS technology, the TIA achieves bandwidth of more than 24 GHz with transimpedance gain of 65 dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000, while showing an acrlong IRN current density of 10.4 pA/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz. The maximum linear input current reaches 2.2 mApp and the total harmonic distortion (THD) is less than 3% for an output swing of 600 mV\u0000<inline-formula> <tex-math>$_{rm pp, {mathrm{ diff}}}$ </tex-math></inline-formula>\u0000. The chip consumes power of 56 mW from 1.4 and 1.1-V supply.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"50-53"},"PeriodicalIF":2.7,"publicationDate":"2024-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139573143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a fully integrated recursive successive-approximation switched capacitor (RSC) DC–DC converter implemented using an automatic cell-based layout generation in 12-nm FinFET technology. A novel design methodology is demonstrated based on the theoretical analyses of the optimal energy operation of the switched-capacitor (SC) DC–DC converter and directly finds the optimal design parameters from the given input specifications. The converter maintains >75% efficiency across a vast range of output currents and temperatures. Our design targets voltage scaling for applications, such as cryo-computing, cryo-sensing, and parts of quantum computing, to achieve high-system power efficiency.
{"title":"A Fully Integrated, Automatically Generated DC–DC Converter Maintaining >75% Efficiency From 398 K Down to 23 K Across Wide Load Ranges in 12-nm FinFET","authors":"Anhang Li;Jeongsup Lee;Prashansa Mukim;Brian D. Hoskins;Pragya Shrestha;David Wentzloff;David Blaauw;Dennis Sylvester;Mehdi Saligane","doi":"10.1109/LSSC.2023.3349129","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3349129","url":null,"abstract":"This letter presents a fully integrated recursive successive-approximation switched capacitor (RSC) DC–DC converter implemented using an automatic cell-based layout generation in 12-nm FinFET technology. A novel design methodology is demonstrated based on the theoretical analyses of the optimal energy operation of the switched-capacitor (SC) DC–DC converter and directly finds the optimal design parameters from the given input specifications. The converter maintains >75% efficiency across a vast range of output currents and temperatures. Our design targets voltage scaling for applications, such as cryo-computing, cryo-sensing, and parts of quantum computing, to achieve high-system power efficiency.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"42-45"},"PeriodicalIF":2.7,"publicationDate":"2024-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139573141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-20DOI: 10.1109/LSSC.2023.3345252
Peng Yan;Po-Hsuan Chang;Anirban Samanta;Mingye Fu;Yu Zhang;Mehmet Berkay On;Ankur Kumar;Hyungryul Kang;Il-Min Yi;Dedeepya Annabattuni;David Scott;Robert Patti;Yang-Hang Fan;Yuanming Zhu;S. J. Ben Yoo;Samuel Palermo
This letter presents a 25-Gb/s 3D-integrated optical receiver, which consists of an electronic integrated circuit (EIC) die fabricated in 12-nm FinFET technology and a photonic integrated circuit (PIC) die fabricated in AIM Photonics’ integrated photonic technology. EIC is flip-chip bonded to PIC through direct bond interconnect (DBI), allowing for significantly reduced parasitic. Except for reduced input-referred noise thanks to improvements in PIC and packaging, variable bandwidth transimpedance amplifier (TIA) with multistage feedback amplifier is utilized for further noise reduction and front-end bandwidth compensation for better full-link energy efficiency. This TIA is followed by a broadband amplifier with active inductor loading, dc cancellation loop, RC LPF generating the pseudo-differential signal, 4 quarter-rate slicers, and a 4-to-8 de-serializer. Measurements demonstrate −17.0-dBm optical modulation amplitude (OMA) sensitivity at 25 Gb/s with 2.12-mW receiver power and 2.66-mW receiver clocking power, which translates to 191.2 and 84.8 fJ/bit receiver energy efficiency, with and without per-channel injection-locked oscillator (ILO) power. Each receiver channel occupies $1560 mu {}text{m} ^{mathrm{ 2}}$ . To the author’s best knowledge, it is the best OMA sensitivity, energy efficiency, and silicon area simultaneously achieved among published 25 Gb/s optical receivers.
{"title":"A 25-Gb/s 3-D Direct Bond Silicon Photonic Receiver in 12-nm FinFET","authors":"Peng Yan;Po-Hsuan Chang;Anirban Samanta;Mingye Fu;Yu Zhang;Mehmet Berkay On;Ankur Kumar;Hyungryul Kang;Il-Min Yi;Dedeepya Annabattuni;David Scott;Robert Patti;Yang-Hang Fan;Yuanming Zhu;S. J. Ben Yoo;Samuel Palermo","doi":"10.1109/LSSC.2023.3345252","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3345252","url":null,"abstract":"This letter presents a 25-Gb/s 3D-integrated optical receiver, which consists of an electronic integrated circuit (EIC) die fabricated in 12-nm FinFET technology and a photonic integrated circuit (PIC) die fabricated in AIM Photonics’ integrated photonic technology. EIC is flip-chip bonded to PIC through direct bond interconnect (DBI), allowing for significantly reduced parasitic. Except for reduced input-referred noise thanks to improvements in PIC and packaging, variable bandwidth transimpedance amplifier (TIA) with multistage feedback amplifier is utilized for further noise reduction and front-end bandwidth compensation for better full-link energy efficiency. This TIA is followed by a broadband amplifier with active inductor loading, dc cancellation loop, RC LPF generating the pseudo-differential signal, 4 quarter-rate slicers, and a 4-to-8 de-serializer. Measurements demonstrate −17.0-dBm optical modulation amplitude (OMA) sensitivity at 25 Gb/s with 2.12-mW receiver power and 2.66-mW receiver clocking power, which translates to 191.2 and 84.8 fJ/bit receiver energy efficiency, with and without per-channel injection-locked oscillator (ILO) power. Each receiver channel occupies \u0000<inline-formula> <tex-math>$1560 mu {}text{m} ^{mathrm{ 2}}$ </tex-math></inline-formula>\u0000. To the author’s best knowledge, it is the best OMA sensitivity, energy efficiency, and silicon area simultaneously achieved among published 25 Gb/s optical receivers.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"34-37"},"PeriodicalIF":2.7,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139488218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents an ultralow-power (ULP) H.264/AVC intra-frame image compression accelerator tailored for intelligent event-driven ULP IoT imaging systems. The H.264/AVC intra-frame codec is customized to enable compression of arbitrary nonrectangular change-detected regions. To optimize energy and latency from image memory accesses, novel algorithm-hardware co-designs are proposed for intra-frame predictions, reducing overhead for neighbor macroblock (McB) accesses by $2.6times $ at a negligible quality loss. With split control for major processing phases, latency is optimized by exploiting data dependency and pipelining. Area and leakage of major computation units are reduced through data path micro-architecture reconfiguration. Fabricated in 40 nm, it occupies a mere 0.32 mm2 area with 4-kB SRAM. At 0.6 V and 153 kHz, it consumes only $1.21 {mu }text{W}$ , with 30.9 pJ/pixel compression energy efficiency that rivals state-of-the-art designs. For an event-driven IoT imaging system, the combination of the proposed accelerator and change detection brings $133times $ reduction to the overall energy for regressing an image of change-detected region of interest.
{"title":"An Ultralow-Power H.264/AVC Intra-Frame Image Compression Accelerator for Intelligent Event-Driven IoT Imaging Systems","authors":"Qirui Zhang;Hyochan An;Andrea Bejarano-Carbo;Hun-Seok Kim;David Blaauw;Dennis Sylvester","doi":"10.1109/LSSC.2023.3344699","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3344699","url":null,"abstract":"This letter presents an ultralow-power (ULP) H.264/AVC intra-frame image compression accelerator tailored for intelligent event-driven ULP IoT imaging systems. The H.264/AVC intra-frame codec is customized to enable compression of arbitrary nonrectangular change-detected regions. To optimize energy and latency from image memory accesses, novel algorithm-hardware co-designs are proposed for intra-frame predictions, reducing overhead for neighbor macroblock (McB) accesses by \u0000<inline-formula> <tex-math>$2.6times $ </tex-math></inline-formula>\u0000 at a negligible quality loss. With split control for major processing phases, latency is optimized by exploiting data dependency and pipelining. Area and leakage of major computation units are reduced through data path micro-architecture reconfiguration. Fabricated in 40 nm, it occupies a mere 0.32 mm2 area with 4-kB SRAM. At 0.6 V and 153 kHz, it consumes only \u0000<inline-formula> <tex-math>$1.21 {mu }text{W}$ </tex-math></inline-formula>\u0000, with 30.9 pJ/pixel compression energy efficiency that rivals state-of-the-art designs. For an event-driven IoT imaging system, the combination of the proposed accelerator and change detection brings \u0000<inline-formula> <tex-math>$133times $ </tex-math></inline-formula>\u0000 reduction to the overall energy for regressing an image of change-detected region of interest.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"30-33"},"PeriodicalIF":2.7,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139488220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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