Pub Date : 2025-06-11DOI: 10.1109/LSSC.2025.3578942
Wei-Yu Lin;Jun-Chau Chien
Implementing dual-resonance class-F oscillators with transformer feedback beyond 60 GHz poses significant challenges due to the limited third-harmonic tank impedance when using small coils with low coupling factors. To address these limitations and leverage the phase noise advantages of class-F operation, this letter introduces a standing-wave oscillator (SWO) topology featuring an on-chip multiband transmission-line (t-line) resonator loaded with harmonically tuned open stubs. The proposed design enhances third-harmonic resonance while facilitating precise alignment of the oscillation frequencies. Three voltage-controlled oscillators (VCOs) were implemented using TSMC’s 65-nm LP technology, demonstrating that the proposed class-F half-wavelength SWO achieves phase noise improvements of 3.1 and 6.4 dB at a 1-MHz offset compared to conventional SWO and transformer-based class-F VCO, respectively.
{"title":"A Millimeter-Wave Standing-Wave Oscillator With Frequency-Specific Wave-Velocity Control Demonstrating Class-F Effects","authors":"Wei-Yu Lin;Jun-Chau Chien","doi":"10.1109/LSSC.2025.3578942","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3578942","url":null,"abstract":"Implementing dual-resonance class-F oscillators with transformer feedback beyond 60 GHz poses significant challenges due to the limited third-harmonic tank impedance when using small coils with low coupling factors. To address these limitations and leverage the phase noise advantages of class-F operation, this letter introduces a standing-wave oscillator (SWO) topology featuring an on-chip multiband transmission-line (t-line) resonator loaded with harmonically tuned open stubs. The proposed design enhances third-harmonic resonance while facilitating precise alignment of the oscillation frequencies. Three voltage-controlled oscillators (VCOs) were implemented using TSMC’s 65-nm LP technology, demonstrating that the proposed class-F half-wavelength SWO achieves phase noise improvements of 3.1 and 6.4 dB at a 1-MHz offset compared to conventional SWO and transformer-based class-F VCO, respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"181-184"},"PeriodicalIF":2.2,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144524414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a 45V high-precision current-feedback instrumentation amplifier (CFIA) that combines both chopping and auto-zeroing (AZ) to achieve 1.8-$mu $ V input offset (10 samples) and 33.5-$mu $ V input-referred ripple. The AZ is duty cycled to minimize power and silicon area, with a parallel auxiliary path operating during AZ to keep the amplifier functioning properly. To improve the limited input signal range of conventional CFIA, an input common-mode (CM) voltage tracking circuit improves the input common-mode voltage range (CMVR) up to 42 V and CMRR to 132-dB, respectively. Further combined with source degeneration resistors, the input differential-mode voltage range (DMVR) is also increased to 800mV at 1% THD. The CFIA is implemented in a standard 0.18-$mu $ m BCD process and consumes $294.5~mu $ A. This translates into a competitive efficiency in terms of GBW/supply current of 134 kHz/$mu $ A.
{"title":"A 45-V Auto-Zero-Stabilized Chopper Instrumentation Amplifier With 1.8- μ V Offset, 33.5- μ V Ripple, and 42-V Common-Mode Input Range","authors":"Jiahao Wang;Shen Ye;Shiqi Zhang;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2025.3576393","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3576393","url":null,"abstract":"This letter presents a 45V high-precision current-feedback instrumentation amplifier (CFIA) that combines both chopping and auto-zeroing (AZ) to achieve 1.8-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>V input offset (10 samples) and 33.5-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>V input-referred ripple. The AZ is duty cycled to minimize power and silicon area, with a parallel auxiliary path operating during AZ to keep the amplifier functioning properly. To improve the limited input signal range of conventional CFIA, an input common-mode (CM) voltage tracking circuit improves the input common-mode voltage range (CMVR) up to 42 V and CMRR to 132-dB, respectively. Further combined with source degeneration resistors, the input differential-mode voltage range (DMVR) is also increased to 800mV at 1% THD. The CFIA is implemented in a standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m BCD process and consumes <inline-formula> <tex-math>$294.5~mu $ </tex-math></inline-formula>A. This translates into a competitive efficiency in terms of GBW/supply current of 134 kHz/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"173-176"},"PeriodicalIF":2.2,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144519461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-02DOI: 10.1109/LSSC.2025.3575536
Cody J. Ellington;Sandeep Hari;Brian A. Floyd
A bandpass reflection-mode N-path filter (RMNF) with 2-GHz bandwidth and 10 to 40 GHz center-frequency tuning is presented. The design includes a broadband hybrid coupler, N-path reflectors, comprising four-phase passive mixers terminated with third-order in-phase and quadrature-phase active baseband loads, and a broadband clock-generation network. The reflectors realize an in-band open circuit and an out-of-band matched termination, providing a bandpass response in reflection mode. The filter is fabricated in the GlobalFoundries 45-nm RFSOI process. Across the 10 to 40 GHz tuning range, the bandpass filter has 18 dB/octave roll-off, 3.6–6.3 dB insertion loss, 40–20 dB out-of-band rejection, 6–12 dB noise figure, +22–+12 dBm out-of-band input-referred third-order intercept point, and 130–332 mW of power consumption.
{"title":"A 10 to 40 GHz Reflection-Mode N-Path Filter","authors":"Cody J. Ellington;Sandeep Hari;Brian A. Floyd","doi":"10.1109/LSSC.2025.3575536","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3575536","url":null,"abstract":"A bandpass reflection-mode N-path filter (RMNF) with 2-GHz bandwidth and 10 to 40 GHz center-frequency tuning is presented. The design includes a broadband hybrid coupler, N-path reflectors, comprising four-phase passive mixers terminated with third-order in-phase and quadrature-phase active baseband loads, and a broadband clock-generation network. The reflectors realize an in-band open circuit and an out-of-band matched termination, providing a bandpass response in reflection mode. The filter is fabricated in the GlobalFoundries 45-nm RFSOI process. Across the 10 to 40 GHz tuning range, the bandpass filter has 18 dB/octave roll-off, 3.6–6.3 dB insertion loss, 40–20 dB out-of-band rejection, 6–12 dB noise figure, +22–+12 dBm out-of-band input-referred third-order intercept point, and 130–332 mW of power consumption.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"169-172"},"PeriodicalIF":2.2,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a D-Band fundamental-sampling phase-locked loop (FS-PLL) featuring a complementary power-gating injection locking frequency-multiplier-based phase detector (CPG-ILFM PD). To reduce the level of the reference spur, the proposed CPG-ILFM PD employs two replica voltage-controlled oscillators (RVCOs) that are alternatively switched to detect the phase error of the main VCO. This approach mitigates the binary frequency shift keying (BFSK)-like modulation typically observed in conventional ILFM PDs. Additionally, the loop bandwidth of the PLL was extended, effectively suppressing the poor out-of-band phase noise (PN) of the D-Band main VCO and enhancing jitter performance. Fabricated in a 40-nm CMOS process, the proposed D-Band PLL achieved a reference spur of −51 dBc and an RMS jitter of 65.6 fs while consuming 59.5 mW of power. This results in a jitter FoM of −245.9 dB at 119.5 GHz.
{"title":"A Low-Reference-Spur and Low-Jitter D-Band PLL With Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector","authors":"Jaeho Kim;Jooeun Bang;Seohee Jung;Myeongho Han;Jaehyouk Choi","doi":"10.1109/LSSC.2025.3564893","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3564893","url":null,"abstract":"This letter presents a D-Band fundamental-sampling phase-locked loop (FS-PLL) featuring a complementary power-gating injection locking frequency-multiplier-based phase detector (CPG-ILFM PD). To reduce the level of the reference spur, the proposed CPG-ILFM PD employs two replica voltage-controlled oscillators (RVCOs) that are alternatively switched to detect the phase error of the main VCO. This approach mitigates the binary frequency shift keying (BFSK)-like modulation typically observed in conventional ILFM PDs. Additionally, the loop bandwidth of the PLL was extended, effectively suppressing the poor out-of-band phase noise (PN) of the D-Band main VCO and enhancing jitter performance. Fabricated in a 40-nm CMOS process, the proposed D-Band PLL achieved a reference spur of −51 dBc and an RMS jitter of 65.6 fs while consuming 59.5 mW of power. This results in a jitter FoM of −245.9 dB at 119.5 GHz.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"129-132"},"PeriodicalIF":2.2,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-25DOI: 10.1109/LSSC.2025.3564312
Shiwei Zhang;Wei Deng;Haikun Jia;Hongzhuo Liu;Junlong Gong;Qiuyu Peng;Baoyong Chi
To achieve robust ultra-low phase noise (PN) and a high figure of merit (FoM), this letter proposes a series-parallel-resonance oscillator topology based on the following ideas: 1) a low-impedance resonator that supports high power consumption and effective PN suppression within a compact layout and 2) impedance and gain boosting for PN-power tradeoff, sharper transition, and active noise reduction. Prototyped in 65-nm CMOS technology, the proposed X-band oscillator demonstrates a PN of −131.4 dBc/Hz at 1-MHz offset, a FoM of 191.5 dBc/Hz, and a FoMA (i.e., FoM with area) of 198.5 dBc/Hz at 10 GHz with quadrature output.
{"title":"A Series-Parallel-Resonance Oscillator With a 191.5 dBc/Hz FoM","authors":"Shiwei Zhang;Wei Deng;Haikun Jia;Hongzhuo Liu;Junlong Gong;Qiuyu Peng;Baoyong Chi","doi":"10.1109/LSSC.2025.3564312","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3564312","url":null,"abstract":"To achieve robust ultra-low phase noise (PN) and a high figure of merit (FoM), this letter proposes a series-parallel-resonance oscillator topology based on the following ideas: 1) a low-impedance resonator that supports high power consumption and effective PN suppression within a compact layout and 2) impedance and gain boosting for PN-power tradeoff, sharper transition, and active noise reduction. Prototyped in 65-nm CMOS technology, the proposed X-band oscillator demonstrates a PN of −131.4 dBc/Hz at 1-MHz offset, a FoM of 191.5 dBc/Hz, and a FoMA (i.e., FoM with area) of 198.5 dBc/Hz at 10 GHz with quadrature output.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"141-144"},"PeriodicalIF":2.2,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144090731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a digital-to-analog-converter/analog-to-digital converter (DAC/ADC)-based multicarrier transceiver fabricated in a 22-nm FinFET technology. The multicarrier signaling scheme utilizes orthogonally spaced carriers for spectral efficient band spacing and exhibit jitter robustness compared to conventional baseband pulse amplitude-based signaling. The transmitter has a polar digital signal processor (DSP) to generate the equalized codes driving the 7-b phase DACs, and 7-b amplitude DACs with 2-b predistortion to yield 1.2-Vppd swing. The multicarrier receiver front-end ADC outputs are equalized with a MIMO DSP backend to compensate for the intersymbol interference and interchannel interference. The measured transceiver at 56 Gb/s through a 40.8-dB loss at 14-GHz channel showed a jitter tolerance of up to 1.21 psrms at BER$lt 10{^{-}4 }$ with 7.82-pJ/bit power efficiency.
{"title":"A 56-Gb/s DAC/ADC-Based Multicarrier Transceiver With TX Polar DSP and RX MIMO-DSP for >40-dB Loss Channel","authors":"Srujan Kumar Kaile;Julian Camilo Gomez Diaz;Yuanming Zhu;Il-Min Yi;Tong Liu;Sebastian Hoyos;Samuel Palermo","doi":"10.1109/LSSC.2025.3562615","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3562615","url":null,"abstract":"This letter presents a digital-to-analog-converter/analog-to-digital converter (DAC/ADC)-based multicarrier transceiver fabricated in a 22-nm FinFET technology. The multicarrier signaling scheme utilizes orthogonally spaced carriers for spectral efficient band spacing and exhibit jitter robustness compared to conventional baseband pulse amplitude-based signaling. The transmitter has a polar digital signal processor (DSP) to generate the equalized codes driving the 7-b phase DACs, and 7-b amplitude DACs with 2-b predistortion to yield 1.2-Vppd swing. The multicarrier receiver front-end ADC outputs are equalized with a MIMO DSP backend to compensate for the intersymbol interference and interchannel interference. The measured transceiver at 56 Gb/s through a 40.8-dB loss at 14-GHz channel showed a jitter tolerance of up to 1.21 psrms at BER<inline-formula> <tex-math>$lt 10{^{-}4 }$ </tex-math></inline-formula> with 7.82-pJ/bit power efficiency.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"125-128"},"PeriodicalIF":2.2,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a single-ended offset-compensating (SEOC) with ground precharge bit-line sense amplifier (BLSA). It uses a ground (GND) precharge (PRE) configuration to overcome its limited headroom margin. The single-ended topology that exploits a charge-transfer amplification can eliminate a redundant edge blocks and additional reference circuitry for GND PRE, while maintaining energy efficiency. It is fabricated in a 25-nm DRAM process and compared with offset-compensation sense amplifier (OCSA). The proposed BLSA can achieve 98% decrease in fail bit count (FBC) compared to OCSA at 0.8 V supply voltage and achieve less than 1% performance degradation without redundant edge blocks.
{"title":"A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier With Ground Precharge and Charge Transfer Pre Sensing for Sub-1V DRAM","authors":"Changyoung Lee;Youngseok Park;Hyunchul Yoon;Seryeong Yoon;Donggeon Kim;Bokyeon Won;Junhwa Song;Injae Bae;Jae-Joon Song;Kyuchang Kang;Jaehyuk Kim;Kyungrak Cho;Incheol Nam;Jungdon Ihm;Younghun Seo;Changsik Yoo;Sangjun Hwang","doi":"10.1109/LSSC.2025.3561280","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3561280","url":null,"abstract":"This letter presents a single-ended offset-compensating (SEOC) with ground precharge bit-line sense amplifier (BLSA). It uses a ground (GND) precharge (PRE) configuration to overcome its limited headroom margin. The single-ended topology that exploits a charge-transfer amplification can eliminate a redundant edge blocks and additional reference circuitry for GND PRE, while maintaining energy efficiency. It is fabricated in a 25-nm DRAM process and compared with offset-compensation sense amplifier (OCSA). The proposed BLSA can achieve 98% decrease in fail bit count (FBC) compared to OCSA at 0.8 V supply voltage and achieve less than 1% performance degradation without redundant edge blocks.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"145-148"},"PeriodicalIF":2.2,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144125646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-15DOI: 10.1109/LSSC.2025.3560676
Yong-Jun Jo;Chufeng Yang;Yuanjin Zheng;Tony Tae-Hyoung Kim
Various data-driven computation-in-memory (CIM) architectures have been proposed to reduce inference energy. However, most data-driven CIM architectures require specific conditions to achieve energy savings (e.g., zero skip requires a ReLU activation function). This letter proposes a convolutional window-inspired similarity-aware CIM that saves energy by predicting the current output based on the previous one, which is applicable in most cases where the neural network is based on convolution. In addition, this letter introduces a novel transposable architecture to enhance linearity and an analog-to-digital converter (ADC) for improved area efficiency. The prototype was fabricated with 65 nm process and achieved the highest SWaP FoM as 19.04 TOPS/W$times $ Mb/mm2 among the state-of-the-art transposable CIMs.
{"title":"Convolutional Window-Inspired Similarity-Aware Computation-in-Memory for Energy Saving","authors":"Yong-Jun Jo;Chufeng Yang;Yuanjin Zheng;Tony Tae-Hyoung Kim","doi":"10.1109/LSSC.2025.3560676","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3560676","url":null,"abstract":"Various data-driven computation-in-memory (CIM) architectures have been proposed to reduce inference energy. However, most data-driven CIM architectures require specific conditions to achieve energy savings (e.g., zero skip requires a ReLU activation function). This letter proposes a convolutional window-inspired similarity-aware CIM that saves energy by predicting the current output based on the previous one, which is applicable in most cases where the neural network is based on convolution. In addition, this letter introduces a novel transposable architecture to enhance linearity and an analog-to-digital converter (ADC) for improved area efficiency. The prototype was fabricated with 65 nm process and achieved the highest SWaP FoM as 19.04 TOPS/W<inline-formula> <tex-math>$times $ </tex-math></inline-formula>Mb/mm2 among the state-of-the-art transposable CIMs.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"121-124"},"PeriodicalIF":2.2,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents an energy-efficient MOS-based temperature sensor, enhanced through transducer and readout circuit integrated design, LSB-first SAR, and energy-efficient comparator. The transducer and readout circuit integrated design reduces noise by combining two blocks into one. With temperature-dependent offset voltage, the comparator integrates with the LSB-first SAR and is optimized for energy efficiency. The LSB-first SAR reduces the number of cycles and energy consumption. In addition, an asynchronous clock controls the circuit, eliminating the need for a timing reference and adjusting speed to temperature to increase measurement robustness. The temperature sensor was fabricated with a 65 nm CMOS process, and the sensor has −60 to $145~^{circ }$ C measurement range. After two-point calibration with a second-order polynomial, errors are −1.93/${+} 1.44~^{circ }$ C over the entire range and −0.96/${+} 0.94~^{circ }$ C from −43 to $137~^{circ }$ C. At room temperature, the sensor achieves 71.8 mK resolution and 41.9 pJ per conversion, resulting in the best resolution figure-of-merit of 216 fJ$cdot $ K2 among MOS-based sensors.
{"title":"A MOS-Based Temperature Sensor With Energy-Efficient Techniques","authors":"Jooeun Kim;Jeongmyeong Kim;Minkyu Yang;Kyounghun Kang;Wanyeong Jung","doi":"10.1109/LSSC.2025.3559900","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3559900","url":null,"abstract":"This letter presents an energy-efficient MOS-based temperature sensor, enhanced through transducer and readout circuit integrated design, LSB-first SAR, and energy-efficient comparator. The transducer and readout circuit integrated design reduces noise by combining two blocks into one. With temperature-dependent offset voltage, the comparator integrates with the LSB-first SAR and is optimized for energy efficiency. The LSB-first SAR reduces the number of cycles and energy consumption. In addition, an asynchronous clock controls the circuit, eliminating the need for a timing reference and adjusting speed to temperature to increase measurement robustness. The temperature sensor was fabricated with a 65 nm CMOS process, and the sensor has −60 to <inline-formula> <tex-math>$145~^{circ }$ </tex-math></inline-formula>C measurement range. After two-point calibration with a second-order polynomial, errors are −1.93/<inline-formula> <tex-math>${+} 1.44~^{circ }$ </tex-math></inline-formula>C over the entire range and −0.96/<inline-formula> <tex-math>${+} 0.94~^{circ }$ </tex-math></inline-formula>C from −43 to <inline-formula> <tex-math>$137~^{circ }$ </tex-math></inline-formula>C. At room temperature, the sensor achieves 71.8 mK resolution and 41.9 pJ per conversion, resulting in the best resolution figure-of-merit of 216 fJ<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>K2 among MOS-based sensors.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"109-112"},"PeriodicalIF":2.2,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143870918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-08DOI: 10.1109/LSSC.2025.3558928
Chang Xue;Youming Yang;Siyuan He;Gang Du;Yuan Wang;Yandong He
In computing-in-memory (CIM) architecture, it is necessary to reliably adjust the precision according to the specific demands of the application, enabling a tradeoff between high precision and high energy efficiency. In addition, when performing multibit computations, nonlinearity errors between different bits can adversely affect the network’s accuracy. Therefore, this work proposes an 8Kb dual-edge time-domain CIM macro, which incorporates a segmented precision configuration scheme. By mapping the high and low 4 bits of the 8-bit input to the rising and falling edges of the pulse for independent computation, this design mitigates nonlinearity errors between high and low bits. The precision of multiplication-and-accumulation (MAC) operations for both high and low bits can be independently adjusted, ensuring sufficient accuracy while enhancing energy efficiency. This work attains an energy efficiency ranging from 8.03 to 13.20 TOPS/W in the end. For the CIFAR-10 dataset, when the inputs and weights are of 8-bit precision, this work reaches an inference accuracy of 90.27%–91.92%.
{"title":"A Segmented Precision Configurable Computing-in-Memory Macro With Dual-Edge Time-Domain Structure","authors":"Chang Xue;Youming Yang;Siyuan He;Gang Du;Yuan Wang;Yandong He","doi":"10.1109/LSSC.2025.3558928","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3558928","url":null,"abstract":"In computing-in-memory (CIM) architecture, it is necessary to reliably adjust the precision according to the specific demands of the application, enabling a tradeoff between high precision and high energy efficiency. In addition, when performing multibit computations, nonlinearity errors between different bits can adversely affect the network’s accuracy. Therefore, this work proposes an 8Kb dual-edge time-domain CIM macro, which incorporates a segmented precision configuration scheme. By mapping the high and low 4 bits of the 8-bit input to the rising and falling edges of the pulse for independent computation, this design mitigates nonlinearity errors between high and low bits. The precision of multiplication-and-accumulation (MAC) operations for both high and low bits can be independently adjusted, ensuring sufficient accuracy while enhancing energy efficiency. This work attains an energy efficiency ranging from 8.03 to 13.20 TOPS/W in the end. For the CIFAR-10 dataset, when the inputs and weights are of 8-bit precision, this work reaches an inference accuracy of 90.27%–91.92%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"117-120"},"PeriodicalIF":2.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143871004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：