Pub Date : 2025-09-10DOI: 10.1109/LSSC.2025.3608096
Kai Cui;Honglei Xu;Yingduo Duan;Yan Lu;Xiaoya Fan;Yanzhao Ma
This letter presents a linear dynamic voltage scaling (DVS) technique using a dual-loop multistage charge-pump maintaining the minimum voltage headroom for implantable neurostimulation. By adopting an analog DVS with adaptive feedback divider, the stimulus current source could be always kept operating at the boundary of the saturation region and the linear region under different stimulus currents. Furthermore, a simple mode-switched control is introduced to improve the loop response of charge-pump. The design has been fabricated in a 0.18-$mu $ m BCD process. The DVS technique increases the measured stimulus efficiency up to 52.8% higher than a fixed supply voltage with a peak efficiency of 89.6% in the range of the stimulus current from 0.5 mA to 0.9 mA.
{"title":"A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation","authors":"Kai Cui;Honglei Xu;Yingduo Duan;Yan Lu;Xiaoya Fan;Yanzhao Ma","doi":"10.1109/LSSC.2025.3608096","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608096","url":null,"abstract":"This letter presents a linear dynamic voltage scaling (DVS) technique using a dual-loop multistage charge-pump maintaining the minimum voltage headroom for implantable neurostimulation. By adopting an analog DVS with adaptive feedback divider, the stimulus current source could be always kept operating at the boundary of the saturation region and the linear region under different stimulus currents. Furthermore, a simple mode-switched control is introduced to improve the loop response of charge-pump. The design has been fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m BCD process. The DVS technique increases the measured stimulus efficiency up to 52.8% higher than a fixed supply voltage with a peak efficiency of 89.6% in the range of the stimulus current from 0.5 mA to 0.9 mA.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"261-264"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145110302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a low power DSP-based single-chip 800GbE PAM-4 PHY transceiver in 7 nm process capable of driving eight lanes of up to 112-Gb/s. It supports both electrical and optical links with monolithic integrated laser driver enabling direct-drive PAM-4 output capability for EML and silicon photonics. The transceiver supports 42 dB IL channel at Nyquist with pre-FEC BER<3E-8. The per-lane analog power efficiency is 2.59pJ/b for low-swing drive mode and 4.58 pJ/b for direct-drive mode.
本文提出了一种低功耗、基于dsp的单片800GbE PAM-4 PHY收发器，采用7nm工艺，可驱动8通道，最高速率为112gb /s。它通过单片集成激光驱动器支持电气和光学链路，为EML和硅光子学提供直接驱动PAM-4输出能力。收发器在奈奎斯特支持42 dB IL通道，预fec误码率<3E-8。低摆幅驱动模式下的每车道模拟功率效率为2.59pJ/b，直接驱动模式下为4.58 pJ/b。
{"title":"An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm","authors":"Chang Liu;Burak Catli;Yong Liu;Anand Vasani;Guansheng Li;Kun Chuai;Lakshmi Rao;Yang Liu;Xin Meng;Jiawen Zhang;Tim He;Batu Dayanik;Vadim Milirud;Meisam Honarvar Nazari;Hyo Gyuem Rhew;Derui Kong;Arvindh Iyer;Nan Wang;Alireza Nilchi;Aminghasem Safarian;Ray Wang;Hyung-Joon Jeon;Xiaochen Yang;Boyu Hu;Jerry Han;Adesh Garg;Kumar Thasari;Heng Zhang;Namik Kocaman;Ali Nazemi;Delong Cui;Afshin Momtaz;Jun Cao","doi":"10.1109/LSSC.2025.3608134","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608134","url":null,"abstract":"This work presents a low power DSP-based single-chip 800GbE PAM-4 PHY transceiver in 7 nm process capable of driving eight lanes of up to 112-Gb/s. It supports both electrical and optical links with monolithic integrated laser driver enabling direct-drive PAM-4 output capability for EML and silicon photonics. The transceiver supports 42 dB IL channel at Nyquist with pre-FEC BER<3E-8. The per-lane analog power efficiency is 2.59pJ/b for low-swing drive mode and 4.58 pJ/b for direct-drive mode.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"281-284"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-10DOI: 10.1109/LSSC.2025.3608187
Woojin Lee;Changmin Sim;Changjoo Kim;Jinwoo Jeon;Hyundo Jung;Taihyun Kim;Chulwoo Kim
This work presents a capacitive-latch (C-latch) true random number generator (TRNG) that achieves both inverter mismatch autozeroing and accelerated evaluation by utilizing coupling capacitors. The proposed C-latch TRNG samples the mismatch between inverter equalization voltages through coupling capacitors during the equalization phase, effectively autozeroing inverter mismatch and enabling high-entropy raw bit generation without calibration. In addition, larger coupling capacitors reduce the effective capacitance in the gate-node stochastic differential equation, resulting in faster evaluation and reduced energy consumption. Fabricated in a 28-nm CMOS process, the TRNG achieves a minimum energy consumption of 38.1 fJ/bit at 0.4-V supply voltage and the maximum throughput of 162.48 Mb/s at 0.9 V. A 4-bit von Neumann post processor consistently extract a full entropy, which successfully passes all NIST SP800-22 and NIST SP800-90B randomness tests under wide voltage and temperature variations, implying both robustness and cryptographic suitability.
{"title":"A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation","authors":"Woojin Lee;Changmin Sim;Changjoo Kim;Jinwoo Jeon;Hyundo Jung;Taihyun Kim;Chulwoo Kim","doi":"10.1109/LSSC.2025.3608187","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608187","url":null,"abstract":"This work presents a capacitive-latch (C-latch) true random number generator (TRNG) that achieves both inverter mismatch autozeroing and accelerated evaluation by utilizing coupling capacitors. The proposed C-latch TRNG samples the mismatch between inverter equalization voltages through coupling capacitors during the equalization phase, effectively autozeroing inverter mismatch and enabling high-entropy raw bit generation without calibration. In addition, larger coupling capacitors reduce the effective capacitance in the gate-node stochastic differential equation, resulting in faster evaluation and reduced energy consumption. Fabricated in a 28-nm CMOS process, the TRNG achieves a minimum energy consumption of 38.1 fJ/bit at 0.4-V supply voltage and the maximum throughput of 162.48 Mb/s at 0.9 V. A 4-bit von Neumann post processor consistently extract a full entropy, which successfully passes all NIST SP800-22 and NIST SP800-90B randomness tests under wide voltage and temperature variations, implying both robustness and cryptographic suitability.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"265-268"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a tri-well implementation of MOS capacitors designed to tackle the challenge of high parasitic capacitance. By serially connecting the three parasitic well junction capacitors between the three wells (N-Well, deep P-Well, and deep N-Well) and substrate (PSUB), the parasitic capacitance can be significantly decreased. A higher bias voltage is applied using a sufficiently large resistor to further reduce parasitic capacitance. Furthermore, we also present a simple and effective method for testing very small parasitic capacitance using off-chip inverters. The test chip was fabricated using the 180-nm BCD process. The measurement results indicate that the ratio of parasitic to flying capacitance can be reduced to as low as 0.67% for 1.8-V MOS capacitors through series-connected tri-well junctions with effective biasing while only increasing a 7.7% the chip area overhead compared to the dual-well junctions.
这封信提出了一种三孔实现的MOS电容器，旨在解决高寄生电容的挑战。通过在三个孔（n孔、深p孔和深n孔）和衬底（PSUB）之间串联三个寄生孔结电容器，可以显著降低寄生电容。使用足够大的电阻施加更高的偏置电压以进一步减小寄生电容。此外，我们还提出了一种使用片外逆变器测试极小寄生电容的简单有效方法。测试芯片采用180nm BCD工艺制备。测量结果表明，通过有效偏置串联的三孔结，1.8 v MOS电容的寄生/飞行电容比可降至0.67%，而与双孔结相比，芯片面积开销仅增加7.7%。
{"title":"Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions","authors":"Zhendong Li;Yongjuan Shi;Yifan Jiang;Chen Hu;Junting Chen;Mengyuan Hua;Xun Liu;Junmin Jiang","doi":"10.1109/LSSC.2025.3608282","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608282","url":null,"abstract":"This letter presents a tri-well implementation of MOS capacitors designed to tackle the challenge of high parasitic capacitance. By serially connecting the three parasitic well junction capacitors between the three wells (N-Well, deep P-Well, and deep N-Well) and substrate (PSUB), the parasitic capacitance can be significantly decreased. A higher bias voltage is applied using a sufficiently large resistor to further reduce parasitic capacitance. Furthermore, we also present a simple and effective method for testing very small parasitic capacitance using off-chip inverters. The test chip was fabricated using the 180-nm BCD process. The measurement results indicate that the ratio of parasitic to flying capacitance can be reduced to as low as 0.67% for 1.8-V MOS capacitors through series-connected tri-well junctions with effective biasing while only increasing a 7.7% the chip area overhead compared to the dual-well junctions.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"277-280"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-02DOI: 10.1109/LSSC.2025.3605369
Cheng-Bin Chen;Tsung Chen;Yuan-Hao Huang
This letter presents a fully digital true random number generator (TRNG) and noise generator (NG) based on a chaos system. We design the chaos random number generator (CRNG) using the proposed Euler-based modified Lorenz system with periodic perturbation and modified modulo unit. The chaos NG (CNG) processor integrates the CRNG with Box-Muller modules to produce Gaussian noise signals. This letter also analyzes the impact of step size on the infinite divergence phenomenon and performs the NIST test to ensure CRNG’s mathematical stability and reliability. The chip was designed and fabricated using TSMC 40 nm CMOS technology. The proposed CRNG chip achieves a throughput of 24.86 Gb/s at a maximum clock frequency of 259 MHz, with a core power consumption of 17.82 mW and an energy efficiency of 0.717 pJ/bit. This performance achieves the highest throughput among state-of-the-art ASIC-based true RNGs (TRNGs). Additionally, the proposed processor achieves a throughput of 1.53 Gsamples/s with a clock frequency of 255 MHz, a core power consumption of 62.73 mW, and an energy efficiency of 41 pJ/sample. This performance achieves the highest throughput and the best energy efficiency in state-of-the-art works.
{"title":"24.86 Gb/s Full-Digital Chaos Random Number 1.53 GSamples/s Noise Generator in 40nm CMOS","authors":"Cheng-Bin Chen;Tsung Chen;Yuan-Hao Huang","doi":"10.1109/LSSC.2025.3605369","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3605369","url":null,"abstract":"This letter presents a fully digital true random number generator (TRNG) and noise generator (NG) based on a chaos system. We design the chaos random number generator (CRNG) using the proposed Euler-based modified Lorenz system with periodic perturbation and modified modulo unit. The chaos NG (CNG) processor integrates the CRNG with Box-Muller modules to produce Gaussian noise signals. This letter also analyzes the impact of step size on the infinite divergence phenomenon and performs the NIST test to ensure CRNG’s mathematical stability and reliability. The chip was designed and fabricated using TSMC 40 nm CMOS technology. The proposed CRNG chip achieves a throughput of 24.86 Gb/s at a maximum clock frequency of 259 MHz, with a core power consumption of 17.82 mW and an energy efficiency of 0.717 pJ/bit. This performance achieves the highest throughput among state-of-the-art ASIC-based true RNGs (TRNGs). Additionally, the proposed processor achieves a throughput of 1.53 Gsamples/s with a clock frequency of 255 MHz, a core power consumption of 62.73 mW, and an energy efficiency of 41 pJ/sample. This performance achieves the highest throughput and the best energy efficiency in state-of-the-art works.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"253-256"},"PeriodicalIF":2.0,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145036957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-29DOI: 10.1109/LSSC.2025.3603569
Chongyun Zhang;Li Wang;Fuzhan Chen;C. Patrick Yue
This letter presents a 0.32 pJ/bit 100-Gb/s PAM-4 CMOS transimpedance amplifier (TIA). Several techniques are proposed to alleviate TIA design tradeoffs while pushing energy efficiency to a limit. A multipeaking input network is designed to relieve the bandwidth (BW) degradation from parasitics of input interface and ESD diodes. An inverter-based single-ended continuous-time linear equalizer (CTLE) enhanced with a Q-shaping inductor is used to further extend the BW. Moreover, a current reuse variable gain amplifier (VGA) based on a transadmittance stage (TAS)-transimpedance stage (TAS-TIS) topology is proposed to provide a dynamic range of 9 dB while maintaining the overall BW and linearity. Implemented in 28-nm CMOS, the TIA achieves a 28-GHz BW with a 65 dB$Omega $ dc transimpedance, while showing an input referred noise density of 16 pA/$surd $ Hz and a total harmonic distortion (THD) < 5% up to $640~mu $ App input current. The TIA consumes 32 mW from a 1.2-V supply, achieving superior BW and energy efficiency among 100-Gb/s+ CMOS TIA designs.
这封信提出了一个0.32 pJ/bit 100 gb /s PAM-4 CMOS跨阻放大器（TIA）。提出了几种技术来减轻TIA设计的权衡，同时将能源效率推向极限。设计了一种多峰输入网络，以缓解输入接口和ESD二极管寄生导致的带宽下降。采用基于逆变器的单端连续时间线性均衡器（CTLE），增强了q整形电感，进一步扩展了BW。此外，提出了一种基于跨导纳级(TAS)-跨阻抗级（TAS- tis）拓扑结构的电流复用可变增益放大器（VGA），在保持整体BW和线性度的同时提供9db的动态范围。在28纳米CMOS中实现的TIA实现了28 ghz的BW，具有65 dB $Omega $直流透阻，同时显示出16 pA/ $surd $ Hz的输入参考噪声密度和总谐波失真(THD) < 5% up to $640~mu $ App input current. The TIA consumes 32 mW from a 1.2-V supply, achieving superior BW and energy efficiency among 100-Gb/s+ CMOS TIA designs.
{"title":"A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS","authors":"Chongyun Zhang;Li Wang;Fuzhan Chen;C. Patrick Yue","doi":"10.1109/LSSC.2025.3603569","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3603569","url":null,"abstract":"This letter presents a 0.32 pJ/bit 100-Gb/s PAM-4 CMOS transimpedance amplifier (TIA). Several techniques are proposed to alleviate TIA design tradeoffs while pushing energy efficiency to a limit. A multipeaking input network is designed to relieve the bandwidth (BW) degradation from parasitics of input interface and ESD diodes. An inverter-based single-ended continuous-time linear equalizer (CTLE) enhanced with a Q-shaping inductor is used to further extend the BW. Moreover, a current reuse variable gain amplifier (VGA) based on a transadmittance stage (TAS)-transimpedance stage (TAS-TIS) topology is proposed to provide a dynamic range of 9 dB while maintaining the overall BW and linearity. Implemented in 28-nm CMOS, the TIA achieves a 28-GHz BW with a 65 dB<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> dc transimpedance, while showing an input referred noise density of 16 pA/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz and a total harmonic distortion (THD) < 5% up to <inline-formula> <tex-math>$640~mu $ </tex-math></inline-formula>App input current. The TIA consumes 32 mW from a 1.2-V supply, achieving superior BW and energy efficiency among 100-Gb/s+ CMOS TIA designs.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"273-276"},"PeriodicalIF":2.0,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-27DOI: 10.1109/LSSC.2025.3603335
Javier Granizo;Ruben Garvi;Ricardo Carrero;Luis Hernandez
This letter presents the experimental results of a leaky-integrate-and-fire neuron (LIF) neuron based on time-domain analog circuitry. This kind of neuron is the core of spiking neural network (SNN) used in edge applications. Edge applications require power-efficient neuron designs whose power consumption is extremely low when idle, and low when in dynamic operation. The proposed neuron complies with the aforementioned requisites by transforming the voltage-based threshold of conventional LIF neurons into a time domain threshold on a quadrature oscillator. In conjunction with a charge-sharing integrator, the proposed neuron shows an energy efficiency of 201 fJ/SOP implemented in $0.13mathbf {mu m}$ process.
{"title":"LIF Neuron Based on a Charge-Powered Ring Oscillator in Weak Inversion Achieving 201 fJ/SOP","authors":"Javier Granizo;Ruben Garvi;Ricardo Carrero;Luis Hernandez","doi":"10.1109/LSSC.2025.3603335","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3603335","url":null,"abstract":"This letter presents the experimental results of a leaky-integrate-and-fire neuron (LIF) neuron based on time-domain analog circuitry. This kind of neuron is the core of spiking neural network (SNN) used in edge applications. Edge applications require power-efficient neuron designs whose power consumption is extremely low when idle, and low when in dynamic operation. The proposed neuron complies with the aforementioned requisites by transforming the voltage-based threshold of conventional LIF neurons into a time domain threshold on a quadrature oscillator. In conjunction with a charge-sharing integrator, the proposed neuron shows an energy efficiency of 201 fJ/SOP implemented in <inline-formula> <tex-math>$0.13mathbf {mu m}$ </tex-math></inline-formula> process.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"249-252"},"PeriodicalIF":2.0,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a D-band bi-directional CMOS double-balanced mixer (DBM) supporting data rates over 160 Gb/s with a 58-GHz RF bandwidth (112–170 GHz). The mixer employs four identical NMOS passive switches ($12~mu $ m/60 nm) in a DBM topology, providing the isolation between RF, LO, and IF ports. Both IF and RF are bi-directional, enabling up conversion and down conversion. The proposed mixer is fabricated in a 65-nm CMOS process with an integrated LO-driver amplifier. LO amplifier has a 9.5-dB simulated gain and an 8-dBm saturated output power. The total area, including RF and DC pads is 0.7749 mm2. The measurement result shows a −12.5-dB conversion gain in both directions with differential signals and a 3-dB extra loss in a single-ended configuration. $mathrm { OP_{1dB}}$ is −13.5 dBm for up conversion and −5.5 dBm for down conversion. In modulated signal measurements, the mixer handles a 40-GHz bandwidth OFDM 16-QAM signal centered at 135 GHz, demonstrating a 160-Gb/s data rate in both up conversion and down conversion.
{"title":"A 160-Gb/s D-Band Bi-Directional CMOS Mixer Covering 112–170 GHz for 6G Transceivers","authors":"Chenxin Liu;Yudai Yamazaki;Anyi Tian;Chun Wang;Hans Herdian;Abanob Shehata;Han Nie;Minzhe Tang;Hiroyuki Sakai;Kazuaki Kunihiro;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2025.3597690","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3597690","url":null,"abstract":"This work presents a D-band bi-directional CMOS double-balanced mixer (DBM) supporting data rates over 160 Gb/s with a 58-GHz RF bandwidth (112–170 GHz). The mixer employs four identical NMOS passive switches (<inline-formula> <tex-math>$12~mu $ </tex-math></inline-formula>m/60 nm) in a DBM topology, providing the isolation between RF, LO, and IF ports. Both IF and RF are bi-directional, enabling up conversion and down conversion. The proposed mixer is fabricated in a 65-nm CMOS process with an integrated LO-driver amplifier. LO amplifier has a 9.5-dB simulated gain and an 8-dBm saturated output power. The total area, including RF and DC pads is 0.7749 mm2. The measurement result shows a −12.5-dB conversion gain in both directions with differential signals and a 3-dB extra loss in a single-ended configuration. <inline-formula> <tex-math>$mathrm { OP_{1dB}}$ </tex-math></inline-formula> is −13.5 dBm for up conversion and −5.5 dBm for down conversion. In modulated signal measurements, the mixer handles a 40-GHz bandwidth OFDM 16-QAM signal centered at 135 GHz, demonstrating a 160-Gb/s data rate in both up conversion and down conversion.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"241-244"},"PeriodicalIF":2.0,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/LSSC.2025.3594739
Hyeon-Ji Choi;Joo-Mi Cho;Hyo-Jin Park;Seok-Jun Lee;Sung-Wan Hong
This letter presents an off-chip output capacitor (CO)-scalable (OCS) boost converter. The proposed OCS boost converter is possible to operate both with and without the off-chip CO. In addition, it operates in a whole conversion ratio (CR) range over 1 while maintaining a small current ripple of an inductor, resulting in a high efficiency with an inductor of which inductance is small, irrespective of the $C_{O}$ capacitance. The converter was fabricated in 130-nm BCD process and shows a peak efficiency of 96.68% at $V_{IN}{=}5.5$ V, $V_{O}{=}7$ V, and I${_{text {O}}} {=}200$ mA which has the CR of 1.27.
{"title":"A 0-to- 10μF Off-Chip Output Capacitor-Scalable Boost Converter Achieving 96.68% Peak Efficiency","authors":"Hyeon-Ji Choi;Joo-Mi Cho;Hyo-Jin Park;Seok-Jun Lee;Sung-Wan Hong","doi":"10.1109/LSSC.2025.3594739","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3594739","url":null,"abstract":"This letter presents an off-chip output capacitor (CO)-scalable (OCS) boost converter. The proposed OCS boost converter is possible to operate both with and without the off-chip CO. In addition, it operates in a whole conversion ratio (CR) range over 1 while maintaining a small current ripple of an inductor, resulting in a high efficiency with an inductor of which inductance is small, irrespective of the <inline-formula> <tex-math>$C_{O}$ </tex-math></inline-formula> capacitance. The converter was fabricated in 130-nm BCD process and shows a peak efficiency of 96.68% at <inline-formula> <tex-math>$V_{IN}{=}5.5$ </tex-math></inline-formula> V, <inline-formula> <tex-math>$V_{O}{=}7$ </tex-math></inline-formula> V, and I<inline-formula> <tex-math>${_{text {O}}} {=}200$ </tex-math></inline-formula> mA which has the CR of 1.27.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"233-236"},"PeriodicalIF":2.0,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144880631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-30DOI: 10.1109/LSSC.2025.3593960
Cai Li;Kaize Zhou;Junyi Qian;Haochang Zhi;Weiwei Shan
This work proposes a unified early-warning adaptive voltage-frequency scaling (AVFS) system that offers a practical low-power solution for commercial IoT devices. First, a path activation-aware monitoring point optimization strategy is proposed to mitigate the risk of illegal voltage scaling. The strategy combines the path activation evaluation with the required timing guard band, reducing monitoring costs by 18.7%. Second, a delay-compensated dual-shadow monitor is developed and paired with a scalable monitoring window sizing methodology to monitor the timing of paths with memory-type endpoints, overcoming the limitation of monitoring only DFF-type endpoints. Third, a unified architecture that integrates both frequency and voltage scaling is presented to alleviate the problems of the off-chip voltage regulation. Fabricated in 40 nm CMOS, a Cortex M0+ CPU with AVFS achieves voltage reductions between 15.4% and 29.5% and power savings ranging from 32.3% to 49.3% at 50–100 MHz across SS/TT/FF corners.
{"title":"A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization","authors":"Cai Li;Kaize Zhou;Junyi Qian;Haochang Zhi;Weiwei Shan","doi":"10.1109/LSSC.2025.3593960","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3593960","url":null,"abstract":"This work proposes a unified early-warning adaptive voltage-frequency scaling (AVFS) system that offers a practical low-power solution for commercial IoT devices. First, a path activation-aware monitoring point optimization strategy is proposed to mitigate the risk of illegal voltage scaling. The strategy combines the path activation evaluation with the required timing guard band, reducing monitoring costs by 18.7%. Second, a delay-compensated dual-shadow monitor is developed and paired with a scalable monitoring window sizing methodology to monitor the timing of paths with memory-type endpoints, overcoming the limitation of monitoring only DFF-type endpoints. Third, a unified architecture that integrates both frequency and voltage scaling is presented to alleviate the problems of the off-chip voltage regulation. Fabricated in 40 nm CMOS, a Cortex M0+ CPU with AVFS achieves voltage reductions between 15.4% and 29.5% and power savings ranging from 32.3% to 49.3% at 50–100 MHz across SS/TT/FF corners.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"229-232"},"PeriodicalIF":2.0,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144880468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：