Pub Date : 2024-03-30DOI: 10.1109/LSSC.2024.3407583
I-Fan Lin;Yu-Chu Tsai;Heng-Li Lin;Yu-Te Liao
This letter presents a design for a voltage and current reference (VCR) that utilizes a 0.18- $mu $ m CMOS process. The design employs stacked-diode MOS transistors (SDMTs) to generate a voltage that is complementary to absolute temperature for the current reference (CR). By adjusting the transistor size ratio, this bias voltage exhibits the similar temperature coefficient (TC) as that of the resistor in the CR. To enhance temperature compensation, a reversely biased transistor is employed in the voltage reference (VR). Additionally, the cascode current mirror and SDMTs in the VR mitigate supply sensitivity in both voltage and current outputs. The VCR achieves a TC of 124 ppm/°C in VR and 264 ppm/°C in CR over a temperature range of $- 40~^{circ }$ C to $130~^{circ }$ C. Furthermore, it achieves a line sensitivity of 0.011 %/V in VR and 0.094 %/V in CR while operating at 18.51 nW at room temperature. The active chip area of the VCR is approximately $25~000~mu $ m2.
{"title":"An 18-nW CMOS Current and Voltage Reference Circuit With Low Line Sensitivity and Wide Temperature Range","authors":"I-Fan Lin;Yu-Chu Tsai;Heng-Li Lin;Yu-Te Liao","doi":"10.1109/LSSC.2024.3407583","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3407583","url":null,"abstract":"This letter presents a design for a voltage and current reference (VCR) that utilizes a 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS process. The design employs stacked-diode MOS transistors (SDMTs) to generate a voltage that is complementary to absolute temperature for the current reference (CR). By adjusting the transistor size ratio, this bias voltage exhibits the similar temperature coefficient (TC) as that of the resistor in the CR. To enhance temperature compensation, a reversely biased transistor is employed in the voltage reference (VR). Additionally, the cascode current mirror and SDMTs in the VR mitigate supply sensitivity in both voltage and current outputs. The VCR achieves a TC of 124 ppm/°C in VR and 264 ppm/°C in CR over a temperature range of \u0000<inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>\u0000C to \u0000<inline-formula> <tex-math>$130~^{circ }$ </tex-math></inline-formula>\u0000C. Furthermore, it achieves a line sensitivity of 0.011 %/V in VR and 0.094 %/V in CR while operating at 18.51 nW at room temperature. The active chip area of the VCR is approximately \u0000<inline-formula> <tex-math>$25~000~mu $ </tex-math></inline-formula>\u0000m2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141474867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter proposes a low-power high-precision capacitance-to-digital converter (CDC) utilizing a dynamic current mirror (DCM) to transform a sensor input capacitance $(C_{mathrm{ IN}})$ into an output current. The resulting current is directly proportional to the ratio of $C_{mathrm{ IN}}$ to an internal reference capacitor $(C_{mathrm {REF}})$ and subsequently converted into a period-modulated output, facilitating simple digitization by a digital counter. The CDC achieves an extensive $C_{mathrm{ IN}}$ range of 1 to 68 pF without the need for a power-hungry reference buffer. Fabricated in a 65-nm CMOS process, the prototype IC occupies a small area of 0.05-mm2 and consumes only $23.9~mu text{W}$ even with a $C_{mathrm{ IN}}$ of 47 pF. It achieves a capacitance resolution of 1.65 fF for a $C_{mathrm{ IN}}$ of 1 pF with a conversion time of 4 ms, corresponding to a 13.6-bit effective number of bit.
{"title":"A 23.9-μW 13.6-Bit Period Modulation-Based Capacitance-to-Digital Converter With Dynamic Current Mirror Front-End","authors":"Hyeyeon Lee;Donguk Seo;Young-Jin Woo;Yoonmyung Lee;Inhee Lee;Youngcheol Chae","doi":"10.1109/LSSC.2024.3382813","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3382813","url":null,"abstract":"This letter proposes a low-power high-precision capacitance-to-digital converter (CDC) utilizing a dynamic current mirror (DCM) to transform a sensor input capacitance \u0000<inline-formula> <tex-math>$(C_{mathrm{ IN}})$ </tex-math></inline-formula>\u0000 into an output current. The resulting current is directly proportional to the ratio of \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 to an internal reference capacitor \u0000<inline-formula> <tex-math>$(C_{mathrm {REF}})$ </tex-math></inline-formula>\u0000 and subsequently converted into a period-modulated output, facilitating simple digitization by a digital counter. The CDC achieves an extensive \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 range of 1 to 68 pF without the need for a power-hungry reference buffer. Fabricated in a 65-nm CMOS process, the prototype IC occupies a small area of 0.05-mm2 and consumes only \u0000<inline-formula> <tex-math>$23.9~mu text{W}$ </tex-math></inline-formula>\u0000 even with a \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 of 47 pF. It achieves a capacitance resolution of 1.65 fF for a \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 of 1 pF with a conversion time of 4 ms, corresponding to a 13.6-bit effective number of bit.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140606068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-27DOI: 10.1109/LSSC.2024.3382594
Yoondeok Na;Myung-Jae Lee;Youngcheol Chae
This letter introduces a compact, high-resolution time-to-digital converter (TDC) for lidar applications. In contrast to a conventional histogram-based peak detection method, this letter proposes a mean detection method using a highly digitized phase-domain delta–sigma (PD $Delta Sigma$ ) TDC. The proposed TDC operates in an incremental $Delta Sigma $ manner for a compact implementation and utilizing a digital integrator as a loop filter that facilitates an extended counting, resulting in significantly improved resolution. By utilizing a dual gated-ring oscillator (GRO) structure, time-quantization noise due to a residue phase of GRO is effectively mitigated. To address the issue of single-photon avalanche diode (SPAD) signals due to their stochastic nature, a dual time window is proposed to compensate for counting error when SPAD trigger missing occurs. Fabricated in a 65-nm CMOS process, the prototype TDC occupies only an area of $2000~mu text{m}~^{mathrm{ 2}}$ . It achieves a noise level of 27.6 ps for the number of cycles of 32. When the cycle is 1000, it achieves a maximum integral nonlinearity (INL) of 80 ps (+53 ps/-27 ps) with a resolution of 8.5 ps.
{"title":"A Compact Phase-Domain Delta–Sigma Time-to-Digital Converter With 8.5-ps Resolution for LiDAR Applications","authors":"Yoondeok Na;Myung-Jae Lee;Youngcheol Chae","doi":"10.1109/LSSC.2024.3382594","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3382594","url":null,"abstract":"This letter introduces a compact, high-resolution time-to-digital converter (TDC) for lidar applications. In contrast to a conventional histogram-based peak detection method, this letter proposes a mean detection method using a highly digitized phase-domain delta–sigma (PD\u0000<inline-formula> <tex-math>$Delta Sigma$ </tex-math></inline-formula>\u0000) TDC. The proposed TDC operates in an incremental \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 manner for a compact implementation and utilizing a digital integrator as a loop filter that facilitates an extended counting, resulting in significantly improved resolution. By utilizing a dual gated-ring oscillator (GRO) structure, time-quantization noise due to a residue phase of GRO is effectively mitigated. To address the issue of single-photon avalanche diode (SPAD) signals due to their stochastic nature, a dual time window is proposed to compensate for counting error when SPAD trigger missing occurs. Fabricated in a 65-nm CMOS process, the prototype TDC occupies only an area of \u0000<inline-formula> <tex-math>$2000~mu text{m}~^{mathrm{ 2}}$ </tex-math></inline-formula>\u0000. It achieves a noise level of 27.6 ps for the number of cycles of 32. When the cycle is 1000, it achieves a maximum integral nonlinearity (INL) of 80 ps (+53 ps/-27 ps) with a resolution of 8.5 ps.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-26DOI: 10.1109/LSSC.2024.3381811
Yang Gao;Howard C. Luong
This letter presents the first on-chip transformer-based six-port balanced-to-unbalanced quadrature hybrid coupler (QHBC). The proposed six-port QHBC employs three transformers to replace eight inductors design in conventional LC-based couplers for miniaturization. Fabricated in CMOS 28 nm, the overall size of the proposed coupler is 0.23 mm $times0.17$ mm, which is equivalent to $0.046cdot lambda _{0} times 0.034cdot lambda _{0}$ , around 20 times smaller compared to the state-of-the-art six-port QHBC. Operating from 48 to 67 GHz, the measured differential and common mode return loss are <−8>−2.2 dB, respectively. The measured output phase and magnitude imbalance are within 10° and 2 dB, respectively. The measured voltage gain varies from −5.8 to −2.8 dB.
{"title":"A 50–67-GHz Transformer-Based Six-Port Balanced-to-Unbalanced Quadrature Hybrid Coupler","authors":"Yang Gao;Howard C. Luong","doi":"10.1109/LSSC.2024.3381811","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3381811","url":null,"abstract":"This letter presents the first on-chip transformer-based six-port balanced-to-unbalanced quadrature hybrid coupler (QHBC). The proposed six-port QHBC employs three transformers to replace eight inductors design in conventional LC-based couplers for miniaturization. Fabricated in CMOS 28 nm, the overall size of the proposed coupler is 0.23 mm \u0000<inline-formula> <tex-math>$times0.17$ </tex-math></inline-formula>\u0000 mm, which is equivalent to \u0000<inline-formula> <tex-math>$0.046cdot lambda _{0} times 0.034cdot lambda _{0}$ </tex-math></inline-formula>\u0000, around 20 times smaller compared to the state-of-the-art six-port QHBC. Operating from 48 to 67 GHz, the measured differential and common mode return loss are <−8>−2.2 dB, respectively. The measured output phase and magnitude imbalance are within 10° and 2 dB, respectively. The measured voltage gain varies from −5.8 to −2.8 dB.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140619579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-21DOI: 10.1109/LSSC.2024.3371728
Injune Yeo;Wangxin He;Yuan-Chun Luo;Shimeng Yu;Jae-Sun Seo
In the article [1] , Table 2 was incorrectly copied from Table I. The correct Table 2 in [1] is shown below.
在文章[1]中，表 2 错误地抄袭了表 I。下文是 [1] 中正确的表 2。
{"title":"Corrections to “A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array”","authors":"Injune Yeo;Wangxin He;Yuan-Chun Luo;Shimeng Yu;Jae-Sun Seo","doi":"10.1109/LSSC.2024.3371728","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3371728","url":null,"abstract":"In the article \u0000<xref>[1]</xref>\u0000, \u0000<xref>Table 2</xref>\u0000 was incorrectly copied from Table I. The correct \u0000<xref>Table 2</xref>\u0000 in \u0000<xref>[1]</xref>\u0000 is shown below.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10477667","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140188372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-20DOI: 10.1109/LSSC.2024.3379562
Ziyi Lin;Haikun Jia;Chuanming Zhu;Wei Deng;Huabing Liao;Bao Shi;Lujie Hao;Xiangrong Huang;Baoyong Chi
This letter presents a 4-element phased-array receiver with code-domain hybrid beamforming (CDHBF) in 65-nm CMOS technology. Code-division multiplexing is used to fully preserve the flexibility in the digital domain while using a single RF interface, which reduces the RF chain complexity, reduces the chip area, and improves power efficiency. Phase and amplitude control circuits are also integrated into each path to keep the flexibility to use the receiver as a traditional 4-element phased-array. The phased-array and code modulator can be turned on or off to reconfigure this structure into an analog beamformer, hybrid beamformer, and digital beamformer according to applications. An over-the-air wireless measurement is set up and two streams from different directions are simultaneously received and processed by the proposed receiver. The measured EVMs in CDHBF mode are -22.7 and -20.5 dB for 100 and 200-Ms/s data streams, respectively, without any digital domain equalization.
{"title":"A 4-Element Ka-Band Phased-Array Receiver With Code-Domain Hybrid Beamforming","authors":"Ziyi Lin;Haikun Jia;Chuanming Zhu;Wei Deng;Huabing Liao;Bao Shi;Lujie Hao;Xiangrong Huang;Baoyong Chi","doi":"10.1109/LSSC.2024.3379562","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3379562","url":null,"abstract":"This letter presents a 4-element phased-array receiver with code-domain hybrid beamforming (CDHBF) in 65-nm CMOS technology. Code-division multiplexing is used to fully preserve the flexibility in the digital domain while using a single RF interface, which reduces the RF chain complexity, reduces the chip area, and improves power efficiency. Phase and amplitude control circuits are also integrated into each path to keep the flexibility to use the receiver as a traditional 4-element phased-array. The phased-array and code modulator can be turned on or off to reconfigure this structure into an analog beamformer, hybrid beamformer, and digital beamformer according to applications. An over-the-air wireless measurement is set up and two streams from different directions are simultaneously received and processed by the proposed receiver. The measured EVMs in CDHBF mode are -22.7 and -20.5 dB for 100 and 200-Ms/s data streams, respectively, without any digital domain equalization.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-19DOI: 10.1109/LSSC.2024.3378093
Zhao Zhang;Yidan Zhang;Yiqing Xu;Xinyu Shen;Guike Li;Nan Qi;Jian Liu;Nanjian Wu;Liyuan Liu
This letter presents a low-noise wideband analog front-end (AFE) circuit for long-range linear LiDAR. The nMOS feedforward transimpedance amplifier with inner feedback resistor (NFFR-TIA) is proposed to extend the bandwidth to around 400 MHz and reduce the input referred noise (IRN) concurrently with high-transimpedance gain and improved stability. Two stage continuous-time linear feedback circuits are introduced to further boost the bandwidth to over-1 GHz with flatten in-band AC response and negligible extra noise. Fabricated in a 40-nm CMOS process, our AFE achieves an average IRN of 2.7 pA/Hz $^{mathrm{ 0.5}}$ , 1.6-GHz bandwidth, 103-dB $Omega $ transimpedance gain, and 10-mW power consumption.
{"title":"A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6-GHz Bandwidth, 2.7-pA/Hz0.5 Input-Referred Noise, and 103-dBΩ Transimpedance Gain","authors":"Zhao Zhang;Yidan Zhang;Yiqing Xu;Xinyu Shen;Guike Li;Nan Qi;Jian Liu;Nanjian Wu;Liyuan Liu","doi":"10.1109/LSSC.2024.3378093","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3378093","url":null,"abstract":"This letter presents a low-noise wideband analog front-end (AFE) circuit for long-range linear LiDAR. The nMOS feedforward transimpedance amplifier with inner feedback resistor (NFFR-TIA) is proposed to extend the bandwidth to around 400 MHz and reduce the input referred noise (IRN) concurrently with high-transimpedance gain and improved stability. Two stage continuous-time linear feedback circuits are introduced to further boost the bandwidth to over-1 GHz with flatten in-band AC response and negligible extra noise. Fabricated in a 40-nm CMOS process, our AFE achieves an average IRN of 2.7 pA/Hz \u0000<inline-formula> <tex-math>$^{mathrm{ 0.5}}$ </tex-math></inline-formula>\u0000, 1.6-GHz bandwidth, 103-dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 transimpedance gain, and 10-mW power consumption.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter describes a NAND flash memory multichip package (NAND MCP) incorporating a developed LSI interface (IF) Chip (Bridge Chip) in which the IF to and from the solid-state drive (SSD) controller has twice the speed as that of the IF to and from the NAND dies even with multiple packages on each printed circuit board (PCB) channel. This NAND MCP allows to reduce the number of NAND IF channels on the PCB while retaining the total bandwidth of the SSD and increasing the capacity. The Bridge Chip employs a 2:1 frequency multiplying function to bridge the speed gap, a fast-lock phase-locked loop (PLL) with an extended pull-in range and 16-cycle lock time to enhance the IF performance with its input-jitter filtering effect, and equalizers to compensate for intersymbol interference and reflected noise in up to a 4-drop configuration. The Bridge Chip implemented in a 12-nm CMOS process is demonstrated at 6.4 Gb/s/pin with 2.85-pJ/b I/O energy efficiency in a read operation. The NAND MCP incorporating the Bridge Chip and eight 1-Tb NAND dies achieves data transmission to and from field-programmable gate array (FPGA) at twice the speed of the NAND IF in a 2-drop configuration.
{"title":"A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems","authors":"Shinichi Ikeda;Akira Iwata;Goichi Otomo;Tomoaki Suzuki;Hiroaki Iijima;Mikio Shiraishi;Shinya Kawakami;Masatomo Eimitsu;Yoshiki Matsuoka;Kiyohito Sato;Shigehiro Tsuchiya;Yoshinori Shigeta;Takuma Aoyama","doi":"10.1109/LSSC.2024.3377263","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3377263","url":null,"abstract":"This letter describes a NAND flash memory multichip package (NAND MCP) incorporating a developed LSI interface (IF) Chip (Bridge Chip) in which the IF to and from the solid-state drive (SSD) controller has twice the speed as that of the IF to and from the NAND dies even with multiple packages on each printed circuit board (PCB) channel. This NAND MCP allows to reduce the number of NAND IF channels on the PCB while retaining the total bandwidth of the SSD and increasing the capacity. The Bridge Chip employs a 2:1 frequency multiplying function to bridge the speed gap, a fast-lock phase-locked loop (PLL) with an extended pull-in range and 16-cycle lock time to enhance the IF performance with its input-jitter filtering effect, and equalizers to compensate for intersymbol interference and reflected noise in up to a 4-drop configuration. The Bridge Chip implemented in a 12-nm CMOS process is demonstrated at 6.4 Gb/s/pin with 2.85-pJ/b I/O energy efficiency in a read operation. The NAND MCP incorporating the Bridge Chip and eight 1-Tb NAND dies achieves data transmission to and from field-programmable gate array (FPGA) at twice the speed of the NAND IF in a 2-drop configuration.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140348399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-11DOI: 10.1109/LSSC.2024.3375329
Sheng-Kai Chang;Zhi-Wei Lin;Kuang-Wei Cheng
This letter introduces an ultralow-power ON–OFF keying (OOK) wireless transmitter incorporating innovative multiphase injection locking and frequency multiplication techniques. The transmitter leverages a current mode class-D edge-combining power amplifier, ensuring high-energy efficiency in frequency multiplication to generate the carrier frequency. With a primary focus on facilitating multichannel support for Internet of Things (IoT) applications, the prototype incorporates a low-frequency phase-rotation-based frequency synthesizer. To mitigate the quantization noise in $Delta Sigma $ modulator of the synthesizer, the design combines an N-path filter and injection-locked ring oscillators to effectively filter out the shaped far-out phase noise. The prototype, fabricated in TSMC 90-nm CMOS, achieves an output power of −6.9 dBm with a power consumption of $890~mu text{W}$ at a 0.75-V supply voltage. It supports data rates of up to 40 Mb/s under OOK modulation, resulting in an energy efficiency of 22 pJ/bit and a global efficiency of 23%, showcasing its effectiveness in balancing performance and power consumption.
这封信介绍了一种超低功耗开-关键控（OOK）无线发射机，它采用了创新的多相注入锁定和频率倍增技术。该发射器利用电流模式 D 类边缘合并功率放大器，确保频率倍增产生载波频率的高能效。该原型主要侧重于促进对物联网（IoT）应用的多通道支持，采用了基于相位旋转的低频频率合成器。为了减轻合成器的ΔΣ调制器中的量化噪声，该设计结合了N路径滤波器和注入锁定环形振荡器，以有效滤除形远相位噪声。原型采用台积电90纳米CMOS制造，在0.75伏电源电压下，输出功率为-6.9 dBm，功耗为890~mu text{W}$。在 OOK 调制下，它支持高达 40 Mb/s 的数据传输速率，能效为 22 pJ/bit，总体能效为 23%，在性能和功耗之间实现了有效平衡。
{"title":"A Multichannel Injection-Locked OOK Transmitter With Current Mode Edge-Combining Power Amplifier","authors":"Sheng-Kai Chang;Zhi-Wei Lin;Kuang-Wei Cheng","doi":"10.1109/LSSC.2024.3375329","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3375329","url":null,"abstract":"This letter introduces an ultralow-power ON–OFF keying (OOK) wireless transmitter incorporating innovative multiphase injection locking and frequency multiplication techniques. The transmitter leverages a current mode class-D edge-combining power amplifier, ensuring high-energy efficiency in frequency multiplication to generate the carrier frequency. With a primary focus on facilitating multichannel support for Internet of Things (IoT) applications, the prototype incorporates a low-frequency phase-rotation-based frequency synthesizer. To mitigate the quantization noise in \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 modulator of the synthesizer, the design combines an N-path filter and injection-locked ring oscillators to effectively filter out the shaped far-out phase noise. The prototype, fabricated in TSMC 90-nm CMOS, achieves an output power of −6.9 dBm with a power consumption of \u0000<inline-formula> <tex-math>$890~mu text{W}$ </tex-math></inline-formula>\u0000 at a 0.75-V supply voltage. It supports data rates of up to 40 Mb/s under OOK modulation, resulting in an energy efficiency of 22 pJ/bit and a global efficiency of 23%, showcasing its effectiveness in balancing performance and power consumption.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140310160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter describes a voltage-controlled oscillator (VCO) that can achieve robust flicker noise suppression when the decoupling network is not ideal. Utilizing a multitap transformer, the implicit common-mode (CM) impedance quality factor (Q factor) degradation from the parasitic resistance of the decoupling network can be avoided. Fabricated in 65-nm CMOS, the proposed VCO realizes a flicker corner (1/f3 corner) from 70 to 230 kHz across the tuning range from 4.24 to 4.80 GHz. The proposed VCO achieves a phase noise (PN) of -127.4 dBc/Hz at 1 MHz offset frequency fofst and a Figure of Merit (FoM) of 193.1 dB. The core area of the VCO is 0.29 mm2.
{"title":"A VCO With Robust Implicit Common-Mode Resonance Against Nonideal Decoupling Network","authors":"Dingxin Xu;Zheng Sun;Yuang Xiong;Yuncheng Zhang;Hongye Huang;Zezheng Liu;Ashbir Aviat Fadila;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2024.3399228","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3399228","url":null,"abstract":"This letter describes a voltage-controlled oscillator (VCO) that can achieve robust flicker noise suppression when the decoupling network is not ideal. Utilizing a multitap transformer, the implicit common-mode (CM) impedance quality factor (Q factor) degradation from the parasitic resistance of the decoupling network can be avoided. Fabricated in 65-nm CMOS, the proposed VCO realizes a flicker corner (1/f3 corner) from 70 to 230 kHz across the tuning range from 4.24 to 4.80 GHz. The proposed VCO achieves a phase noise (PN) of -127.4 dBc/Hz at 1 MHz offset frequency fofst and a Figure of Merit (FoM) of 193.1 dB. The core area of the VCO is 0.29 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141181903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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