Pub Date : 2024-06-05DOI: 10.1109/LSSC.2024.3409710
Babita Gyawali;Ramesh K. Pokharel;Samundra K. Thapa;Adel Barakat;Naoki Shinohara
This article presents the design and realization of a compact size high-efficiency complementary metal-oxide- semiconductor rectifier with resonance control technique employing the concept of parallel rectifier. The methodology involves the integration of two rectifiers, where one is main rectifier, specifically designated for rectification purposes and the other is auxiliary, serves for impedance matching, resulting in no matching at input. Furthermore, the auxiliary rectifier offers control over resonance of the proposed rectifier. The proposed design achieves more than 40% conversion efficiency at 22 dBm of input power for the broadband range from 2.4 to 3.5 GHz, with an active circuit size of $0.21~mathrm {mm}^{2}$ .
{"title":"New Rectification Technique Employing Auxiliary Rectifier for Resonance Control Achieving Compact Size and High Efficiency in CMOS","authors":"Babita Gyawali;Ramesh K. Pokharel;Samundra K. Thapa;Adel Barakat;Naoki Shinohara","doi":"10.1109/LSSC.2024.3409710","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3409710","url":null,"abstract":"This article presents the design and realization of a compact size high-efficiency complementary metal-oxide- semiconductor rectifier with resonance control technique employing the concept of parallel rectifier. The methodology involves the integration of two rectifiers, where one is main rectifier, specifically designated for rectification purposes and the other is auxiliary, serves for impedance matching, resulting in no matching at input. Furthermore, the auxiliary rectifier offers control over resonance of the proposed rectifier. The proposed design achieves more than 40% conversion efficiency at 22 dBm of input power for the broadband range from 2.4 to 3.5 GHz, with an active circuit size of \u0000<inline-formula> <tex-math>$0.21~mathrm {mm}^{2}$ </tex-math></inline-formula>\u0000.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"187-190"},"PeriodicalIF":2.2,"publicationDate":"2024-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141474849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-26DOI: 10.1109/LSSC.2024.3393973
Chun Wang;Chenxin Liu;Hans Herdian;Abanob Shehata;Jill Mayeda;Kazuaki Kunihiro;Hiroyuki Sakai;Atsushi Shirane;Kenichi Okada
A D-band wideband passive single-ended upconversion mixer with controlled LO feedthrough in 65-nm CMOS process is presented in this letter. The LO feedthrough was controlled by the varactor and the neutralizing transmission line between the LO and RF ports of the mixer. In measurement, the proposed passive single-ended mixer had a conversion gain of −13.0±1.5 dB with an ultrawide 3-dB bandwidth from 110 to 160 GHz. The LO feedthrough suppression was from −38.9 to −24.4 dB at 135 GHz by changing the varactor bias. The measured OP1dB was −12.5 dBm at center frequency. The chip occupies 0.35 mm2, including pads.
本信介绍了一种采用 65 纳米 CMOS 工艺制造的具有受控 LO 馈通的 D 波段宽带无源单端上转换混频器。LO 馈通由变容二极管和混频器 LO 与 RF 端口之间的中和传输线控制。在测量中，所提出的无源单端混频器的转换增益为 -13.0±1.5 dB，具有 110 至 160 GHz 的超宽 3 dB 带宽。通过改变变容二极管偏置，在 135 GHz 时 LO 馈通抑制从 -38.9 dB 降至 -24.4 dB。在中心频率测量的 OP1dB 为 -12.5 dBm。芯片占地 0.35 平方毫米，包括焊盘。
{"title":"A D-Band Wideband Single-Ended Neutralized Upconversion Mixer With Controlled LO Feedthrough in 65-nm CMOS","authors":"Chun Wang;Chenxin Liu;Hans Herdian;Abanob Shehata;Jill Mayeda;Kazuaki Kunihiro;Hiroyuki Sakai;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2024.3393973","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3393973","url":null,"abstract":"A D-band wideband passive single-ended upconversion mixer with controlled LO feedthrough in 65-nm CMOS process is presented in this letter. The LO feedthrough was controlled by the varactor and the neutralizing transmission line between the LO and RF ports of the mixer. In measurement, the proposed passive single-ended mixer had a conversion gain of −13.0±1.5 dB with an ultrawide 3-dB bandwidth from 110 to 160 GHz. The LO feedthrough suppression was from −38.9 to −24.4 dB at 135 GHz by changing the varactor bias. The measured OP1dB was −12.5 dBm at center frequency. The chip occupies 0.35 mm2, including pads.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"167-170"},"PeriodicalIF":2.7,"publicationDate":"2024-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141078836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-10DOI: 10.1109/LSSC.2024.3386870
Ronald Hassib Galvis Chacón;José Alexandre Diniz;Saulo Finco
The electrical power system (EPS) of satellites requires protection devices to isolate failures in short-circuit conditions that can occur in payloads due to various sources, such as debris, mishandling, or radiation. Latching current limiter (LCL) implemented with a pMOS power transistor is typically used for this task. Radiation can also affect the function of the LCL and compromise the mission of the satellite. Therefore, to improve radiation hardness, LCLs have been developed using different rad-hard techniques, such as the implementation of Wide BandGap (WBG) semiconductors as power switches. Gallium nitride (GaN) transistors are more resistant to radiation due to their intrinsic characteristics. In this letter, an LCL topology with a GaN power switch is presented to improve system reliability for space applications. The LCL has an integrated control circuit in 0.18 $mu text{m}$ CMOS technology powered by an auxiliary source. The proposed LCL was validated by simulation and experimental tests. The LCL limited the current to the set value for a supply voltage of up to 50V and maintained a recovery time of less than 50 $mu text{s}$ , under short-circuit tests.
{"title":"GaN Power Switch for Power Distribution Protection","authors":"Ronald Hassib Galvis Chacón;José Alexandre Diniz;Saulo Finco","doi":"10.1109/LSSC.2024.3386870","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3386870","url":null,"abstract":"The electrical power system (EPS) of satellites requires protection devices to isolate failures in short-circuit conditions that can occur in payloads due to various sources, such as debris, mishandling, or radiation. Latching current limiter (LCL) implemented with a pMOS power transistor is typically used for this task. Radiation can also affect the function of the LCL and compromise the mission of the satellite. Therefore, to improve radiation hardness, LCLs have been developed using different rad-hard techniques, such as the implementation of Wide BandGap (WBG) semiconductors as power switches. Gallium nitride (GaN) transistors are more resistant to radiation due to their intrinsic characteristics. In this letter, an LCL topology with a GaN power switch is presented to improve system reliability for space applications. The LCL has an integrated control circuit in 0.18\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 CMOS technology powered by an auxiliary source. The proposed LCL was validated by simulation and experimental tests. The LCL limited the current to the set value for a supply voltage of up to 50V and maintained a recovery time of less than 50\u0000<inline-formula> <tex-math>$mu text{s}$ </tex-math></inline-formula>\u0000, under short-circuit tests.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"155-158"},"PeriodicalIF":2.7,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140813919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-10DOI: 10.1109/LSSC.2024.3386676
Jian Zhang;Dawei Wang;Wei Zhu;Ming Zhai;Xiangjie Yi;Yan Wang
This letter presents a Ka-band mutual coupling resilient stacked-FET power amplifier (PA) in 45-nm CMOS silicon on insulator. Two sub-PAs with triple-stacked-FET to increase output-power (Pout) are combined through a quadrature hybrid coupler to keep robust and high performance in the scenario of mutual coupling among the phased-array antennas. A shunt inductor is introduced to deal with the performance deterioration caused by the transistors’ parasitic capacitances and the magnetic coupling cancelling topology is adopted for a more compact layout. The measurement results show that the proposed PA achieves 21.2 dBm OP1dB with 27.6% PAE1dB and 22.2 dBm Psat with 28.8% peak PAE. The OP1dB and PAE1dB are beyond 21 dBm and 22% for a frequency range from 25 to 32 GHz, respectively. The maximum small-signal gain is 26.5 dB with <-19/-14 dB S11/S22. The simulated variation of Psat/OP1dB is less than 0.5/1.1 dBm under a strong voltage-standing-wave-ratio condition.
{"title":"A Ka-Band Mutual Coupling Resilient Stacked-FET Power Amplifier With 21.2 dBm OP1dB and 27.6% PAE1dB in 45-nm CMOS SOI","authors":"Jian Zhang;Dawei Wang;Wei Zhu;Ming Zhai;Xiangjie Yi;Yan Wang","doi":"10.1109/LSSC.2024.3386676","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3386676","url":null,"abstract":"This letter presents a Ka-band mutual coupling resilient stacked-FET power amplifier (PA) in 45-nm CMOS silicon on insulator. Two sub-PAs with triple-stacked-FET to increase output-power (Pout) are combined through a quadrature hybrid coupler to keep robust and high performance in the scenario of mutual coupling among the phased-array antennas. A shunt inductor is introduced to deal with the performance deterioration caused by the transistors’ parasitic capacitances and the magnetic coupling cancelling topology is adopted for a more compact layout. The measurement results show that the proposed PA achieves 21.2 dBm OP1dB with 27.6% PAE1dB and 22.2 dBm Psat with 28.8% peak PAE. The OP1dB and PAE1dB are beyond 21 dBm and 22% for a frequency range from 25 to 32 GHz, respectively. The maximum small-signal gain is 26.5 dB with <-19/-14 dB S11/S22. The simulated variation of Psat/OP1dB is less than 0.5/1.1 dBm under a strong voltage-standing-wave-ratio condition.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"147-150"},"PeriodicalIF":2.7,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140647929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-10DOI: 10.1109/LSSC.2024.3387285
Seunghoon Lee;Junhyeong Kim;Kangseop Lee;Ho-Jin Song
This letter presents a 248 GHz compact direct-conversion transmitter with IQ and LO feedthrough (LOFT) calibration capability, which can achieve a data rate of 20-Gb/s with 16-QAM. The transmitter design incorporates a subharmonic double-balanced mixer configuration, simplifying the complexity of the local oscillator (LO) chain. Furthermore, a Wilkinson power divider and a transmission line terminated by variable capacitors are used to generate LO signals with a 45° phase difference. This configuration, combined with variable gain amplifiers, allows for the precise balancing of IQ amplitude and phase. The measured image rejection ratio and LOFT suppression ratio are better than 25 and 28 dB, respectively, in the range of 242–252 GHz. The DC power consumption of the transmitter is 96.3 mW.
这封信介绍了一种 248 GHz 紧凑型直接转换发射机，它具有 IQ 和 LO 馈通（LOFT）校准功能，可通过 16-QAM 实现 20-Gb/s 的数据传输速率。发射机设计采用了亚谐波双平衡混频器配置，简化了本地振荡器（LO）链的复杂性。此外，还使用了一个威尔金森功率分压器和一条由可变电容端接的传输线，以产生具有 45° 相位差的 LO 信号。这种配置与可变增益放大器相结合，实现了 IQ 振幅和相位的精确平衡。在 242-252 GHz 范围内，测量到的图像抑制比和 LOFT 抑制比分别优于 25 和 28 dB。发射机的直流功耗为 96.3 mW。
{"title":"248-GHz Subharmonic Mixer Last Transmitter With I/Q Imbalance and LO Feedthrough Calibration","authors":"Seunghoon Lee;Junhyeong Kim;Kangseop Lee;Ho-Jin Song","doi":"10.1109/LSSC.2024.3387285","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3387285","url":null,"abstract":"This letter presents a 248 GHz compact direct-conversion transmitter with IQ and LO feedthrough (LOFT) calibration capability, which can achieve a data rate of 20-Gb/s with 16-QAM. The transmitter design incorporates a subharmonic double-balanced mixer configuration, simplifying the complexity of the local oscillator (LO) chain. Furthermore, a Wilkinson power divider and a transmission line terminated by variable capacitors are used to generate LO signals with a 45° phase difference. This configuration, combined with variable gain amplifiers, allows for the precise balancing of IQ amplitude and phase. The measured image rejection ratio and LOFT suppression ratio are better than 25 and 28 dB, respectively, in the range of 242–252 GHz. The DC power consumption of the transmitter is 96.3 mW.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"159-162"},"PeriodicalIF":2.7,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140818799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-04DOI: 10.1109/LSSC.2024.3385233
Shun Yamaguchi;Takashi Hisakado;Osami Wada;Mahfuzul Islam
Digital LDOs are gaining attention for their operation with small output capacitance. Adaptive sampling with a large frequency scaling ratio is required for fast transient response with low-power operation. Furthermore, the design of a fluctuation detector to deal with large load steps is important. This letter describes an adaptive-sampling digital LDO with a built-in clock generator and fluctuation detector based on statistical comparator selection. Statistical comparator selection utilizes offset voltage variation to realize stable implicit references. We apply order statistics for run-time calibration. Our proposed LDO fabricated in a commercial 65-nm low-power CMOS process operates from 0.6 to 1.2 V and achieves a maximum current efficiency of 99.99 %. The transient FoM is 0.25 ps.
{"title":"A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection","authors":"Shun Yamaguchi;Takashi Hisakado;Osami Wada;Mahfuzul Islam","doi":"10.1109/LSSC.2024.3385233","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3385233","url":null,"abstract":"Digital LDOs are gaining attention for their operation with small output capacitance. Adaptive sampling with a large frequency scaling ratio is required for fast transient response with low-power operation. Furthermore, the design of a fluctuation detector to deal with large load steps is important. This letter describes an adaptive-sampling digital LDO with a built-in clock generator and fluctuation detector based on statistical comparator selection. Statistical comparator selection utilizes offset voltage variation to realize stable implicit references. We apply order statistics for run-time calibration. Our proposed LDO fabricated in a commercial 65-nm low-power CMOS process operates from 0.6 to 1.2 V and achieves a maximum current efficiency of 99.99 %. The transient FoM is 0.25 ps.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"163-166"},"PeriodicalIF":2.7,"publicationDate":"2024-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140818784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-04DOI: 10.1109/LSSC.2024.3384762
Taylor Barton;Shea Smith;Yu Hao;Ryan Watson;Kyle Rogers;Parker Allred;Bibhu Datta Sahoo;Nancy Fulda;Jordan T. Yorgason;Karl F. Warnick;Mau-Chung Frank Chang;Yen-Cheng Kuan;Shiuh-Hua Wood Chiang
The design and measurement of a time-domain analog spiking neuron is described. The proposed neuron leverages time-domain processing using voltage-controlled oscillators (VCOs) and a time-domain comparator to integrate the input spike and trigger the output spike. A novel leaky circuit uses a phase-locked loop (PLL) to drive the phase difference between the two VCOs toward zero. A weighted capacitive digital-to-analog converter (CDAC) synapse merges the input spikes and phase-frequency detector (PFD) outputs to generate the VCO control voltage. The neuron is implemented in a 28-nm CMOS technology and operates under a subthreshold supply voltage of 0.35 V. Occupying $154~mu {mathrm{ m}}^{2}$ , measurement shows a maximum spike rate of 5.5 MHz and energy consumption of 159 fJ/spike.
{"title":"A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse","authors":"Taylor Barton;Shea Smith;Yu Hao;Ryan Watson;Kyle Rogers;Parker Allred;Bibhu Datta Sahoo;Nancy Fulda;Jordan T. Yorgason;Karl F. Warnick;Mau-Chung Frank Chang;Yen-Cheng Kuan;Shiuh-Hua Wood Chiang","doi":"10.1109/LSSC.2024.3384762","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3384762","url":null,"abstract":"The design and measurement of a time-domain analog spiking neuron is described. The proposed neuron leverages time-domain processing using voltage-controlled oscillators (VCOs) and a time-domain comparator to integrate the input spike and trigger the output spike. A novel leaky circuit uses a phase-locked loop (PLL) to drive the phase difference between the two VCOs toward zero. A weighted capacitive digital-to-analog converter (CDAC) synapse merges the input spikes and phase-frequency detector (PFD) outputs to generate the VCO control voltage. The neuron is implemented in a 28-nm CMOS technology and operates under a subthreshold supply voltage of 0.35 V. Occupying \u0000<inline-formula> <tex-math>$154~mu {mathrm{ m}}^{2}$ </tex-math></inline-formula>\u0000, measurement shows a maximum spike rate of 5.5 MHz and energy consumption of 159 fJ/spike.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"143-146"},"PeriodicalIF":2.7,"publicationDate":"2024-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140639424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-02DOI: 10.1109/LSSC.2024.3384345
Peng Xu;Tao Wang;Xueli Zhang;Peng Cao;Jiawei Xu;Zhiliang Hong
This letter analyzes the proposed variable-sawtooth-based PWM controller for the ac-coupled envelope tracking (ET) supply modulator (SM). The ET SM includes a linear amplifier and a switching power modulator (SPM). The SPM maintains the voltage across the ac-coupling capacitor and provides an output current in a power-efficient manner. A 10-MHz constant frequency is employed in the proposed SPM to reduce the interference to the communication system. It utilizes a pulse-width-modulation controller but contains a voltage main loop and a current auxiliary loop, improving the transient response performance at the expense of complicated control loops. This letter analyzes the stability condition and design methodology to determine key parameters. The simulation and measurement have verified these theoretical analyses.
{"title":"Design and Stability Analysis of the Variable-Sawtooth-Based PWM Controller for the AC-Coupled Envelope Tracking Supply Modulator","authors":"Peng Xu;Tao Wang;Xueli Zhang;Peng Cao;Jiawei Xu;Zhiliang Hong","doi":"10.1109/LSSC.2024.3384345","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3384345","url":null,"abstract":"This letter analyzes the proposed variable-sawtooth-based PWM controller for the ac-coupled envelope tracking (ET) supply modulator (SM). The ET SM includes a linear amplifier and a switching power modulator (SPM). The SPM maintains the voltage across the ac-coupling capacitor and provides an output current in a power-efficient manner. A 10-MHz constant frequency is employed in the proposed SPM to reduce the interference to the communication system. It utilizes a pulse-width-modulation controller but contains a voltage main loop and a current auxiliary loop, improving the transient response performance at the expense of complicated control loops. This letter analyzes the stability condition and design methodology to determine key parameters. The simulation and measurement have verified these theoretical analyses.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"151-154"},"PeriodicalIF":2.7,"publicationDate":"2024-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140813914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-30DOI: 10.1109/LSSC.2024.3407583
I-Fan Lin;Yu-Chu Tsai;Heng-Li Lin;Yu-Te Liao
This letter presents a design for a voltage and current reference (VCR) that utilizes a 0.18- $mu $ m CMOS process. The design employs stacked-diode MOS transistors (SDMTs) to generate a voltage that is complementary to absolute temperature for the current reference (CR). By adjusting the transistor size ratio, this bias voltage exhibits the similar temperature coefficient (TC) as that of the resistor in the CR. To enhance temperature compensation, a reversely biased transistor is employed in the voltage reference (VR). Additionally, the cascode current mirror and SDMTs in the VR mitigate supply sensitivity in both voltage and current outputs. The VCR achieves a TC of 124 ppm/°C in VR and 264 ppm/°C in CR over a temperature range of $- 40~^{circ }$ C to $130~^{circ }$ C. Furthermore, it achieves a line sensitivity of 0.011 %/V in VR and 0.094 %/V in CR while operating at 18.51 nW at room temperature. The active chip area of the VCR is approximately $25~000~mu $ m2.
{"title":"An 18-nW CMOS Current and Voltage Reference Circuit With Low Line Sensitivity and Wide Temperature Range","authors":"I-Fan Lin;Yu-Chu Tsai;Heng-Li Lin;Yu-Te Liao","doi":"10.1109/LSSC.2024.3407583","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3407583","url":null,"abstract":"This letter presents a design for a voltage and current reference (VCR) that utilizes a 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS process. The design employs stacked-diode MOS transistors (SDMTs) to generate a voltage that is complementary to absolute temperature for the current reference (CR). By adjusting the transistor size ratio, this bias voltage exhibits the similar temperature coefficient (TC) as that of the resistor in the CR. To enhance temperature compensation, a reversely biased transistor is employed in the voltage reference (VR). Additionally, the cascode current mirror and SDMTs in the VR mitigate supply sensitivity in both voltage and current outputs. The VCR achieves a TC of 124 ppm/°C in VR and 264 ppm/°C in CR over a temperature range of \u0000<inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>\u0000C to \u0000<inline-formula> <tex-math>$130~^{circ }$ </tex-math></inline-formula>\u0000C. Furthermore, it achieves a line sensitivity of 0.011 %/V in VR and 0.094 %/V in CR while operating at 18.51 nW at room temperature. The active chip area of the VCR is approximately \u0000<inline-formula> <tex-math>$25~000~mu $ </tex-math></inline-formula>\u0000m2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"179-182"},"PeriodicalIF":2.2,"publicationDate":"2024-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141474867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter proposes a low-power high-precision capacitance-to-digital converter (CDC) utilizing a dynamic current mirror (DCM) to transform a sensor input capacitance $(C_{mathrm{ IN}})$ into an output current. The resulting current is directly proportional to the ratio of $C_{mathrm{ IN}}$ to an internal reference capacitor $(C_{mathrm {REF}})$ and subsequently converted into a period-modulated output, facilitating simple digitization by a digital counter. The CDC achieves an extensive $C_{mathrm{ IN}}$ range of 1 to 68 pF without the need for a power-hungry reference buffer. Fabricated in a 65-nm CMOS process, the prototype IC occupies a small area of 0.05-mm2 and consumes only $23.9~mu text{W}$ even with a $C_{mathrm{ IN}}$ of 47 pF. It achieves a capacitance resolution of 1.65 fF for a $C_{mathrm{ IN}}$ of 1 pF with a conversion time of 4 ms, corresponding to a 13.6-bit effective number of bit.
{"title":"A 23.9-μW 13.6-Bit Period Modulation-Based Capacitance-to-Digital Converter With Dynamic Current Mirror Front-End","authors":"Hyeyeon Lee;Donguk Seo;Young-Jin Woo;Yoonmyung Lee;Inhee Lee;Youngcheol Chae","doi":"10.1109/LSSC.2024.3382813","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3382813","url":null,"abstract":"This letter proposes a low-power high-precision capacitance-to-digital converter (CDC) utilizing a dynamic current mirror (DCM) to transform a sensor input capacitance \u0000<inline-formula> <tex-math>$(C_{mathrm{ IN}})$ </tex-math></inline-formula>\u0000 into an output current. The resulting current is directly proportional to the ratio of \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 to an internal reference capacitor \u0000<inline-formula> <tex-math>$(C_{mathrm {REF}})$ </tex-math></inline-formula>\u0000 and subsequently converted into a period-modulated output, facilitating simple digitization by a digital counter. The CDC achieves an extensive \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 range of 1 to 68 pF without the need for a power-hungry reference buffer. Fabricated in a 65-nm CMOS process, the prototype IC occupies a small area of 0.05-mm2 and consumes only \u0000<inline-formula> <tex-math>$23.9~mu text{W}$ </tex-math></inline-formula>\u0000 even with a \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 of 47 pF. It achieves a capacitance resolution of 1.65 fF for a \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 of 1 pF with a conversion time of 4 ms, corresponding to a 13.6-bit effective number of bit.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"135-138"},"PeriodicalIF":2.7,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140606068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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