Pub Date : 2025-08-01DOI: 10.1109/LSSC.2025.3594739
Hyeon-Ji Choi;Joo-Mi Cho;Hyo-Jin Park;Seok-Jun Lee;Sung-Wan Hong
This letter presents an off-chip output capacitor (CO)-scalable (OCS) boost converter. The proposed OCS boost converter is possible to operate both with and without the off-chip CO. In addition, it operates in a whole conversion ratio (CR) range over 1 while maintaining a small current ripple of an inductor, resulting in a high efficiency with an inductor of which inductance is small, irrespective of the $C_{O}$ capacitance. The converter was fabricated in 130-nm BCD process and shows a peak efficiency of 96.68% at $V_{IN}{=}5.5$ V, $V_{O}{=}7$ V, and I${_{text {O}}} {=}200$ mA which has the CR of 1.27.
{"title":"A 0-to- 10μF Off-Chip Output Capacitor-Scalable Boost Converter Achieving 96.68% Peak Efficiency","authors":"Hyeon-Ji Choi;Joo-Mi Cho;Hyo-Jin Park;Seok-Jun Lee;Sung-Wan Hong","doi":"10.1109/LSSC.2025.3594739","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3594739","url":null,"abstract":"This letter presents an off-chip output capacitor (CO)-scalable (OCS) boost converter. The proposed OCS boost converter is possible to operate both with and without the off-chip CO. In addition, it operates in a whole conversion ratio (CR) range over 1 while maintaining a small current ripple of an inductor, resulting in a high efficiency with an inductor of which inductance is small, irrespective of the <inline-formula> <tex-math>$C_{O}$ </tex-math></inline-formula> capacitance. The converter was fabricated in 130-nm BCD process and shows a peak efficiency of 96.68% at <inline-formula> <tex-math>$V_{IN}{=}5.5$ </tex-math></inline-formula> V, <inline-formula> <tex-math>$V_{O}{=}7$ </tex-math></inline-formula> V, and I<inline-formula> <tex-math>${_{text {O}}} {=}200$ </tex-math></inline-formula> mA which has the CR of 1.27.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"233-236"},"PeriodicalIF":2.0,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144880631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-30DOI: 10.1109/LSSC.2025.3593960
Cai Li;Kaize Zhou;Junyi Qian;Haochang Zhi;Weiwei Shan
This work proposes a unified early-warning adaptive voltage-frequency scaling (AVFS) system that offers a practical low-power solution for commercial IoT devices. First, a path activation-aware monitoring point optimization strategy is proposed to mitigate the risk of illegal voltage scaling. The strategy combines the path activation evaluation with the required timing guard band, reducing monitoring costs by 18.7%. Second, a delay-compensated dual-shadow monitor is developed and paired with a scalable monitoring window sizing methodology to monitor the timing of paths with memory-type endpoints, overcoming the limitation of monitoring only DFF-type endpoints. Third, a unified architecture that integrates both frequency and voltage scaling is presented to alleviate the problems of the off-chip voltage regulation. Fabricated in 40 nm CMOS, a Cortex M0+ CPU with AVFS achieves voltage reductions between 15.4% and 29.5% and power savings ranging from 32.3% to 49.3% at 50–100 MHz across SS/TT/FF corners.
{"title":"A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization","authors":"Cai Li;Kaize Zhou;Junyi Qian;Haochang Zhi;Weiwei Shan","doi":"10.1109/LSSC.2025.3593960","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3593960","url":null,"abstract":"This work proposes a unified early-warning adaptive voltage-frequency scaling (AVFS) system that offers a practical low-power solution for commercial IoT devices. First, a path activation-aware monitoring point optimization strategy is proposed to mitigate the risk of illegal voltage scaling. The strategy combines the path activation evaluation with the required timing guard band, reducing monitoring costs by 18.7%. Second, a delay-compensated dual-shadow monitor is developed and paired with a scalable monitoring window sizing methodology to monitor the timing of paths with memory-type endpoints, overcoming the limitation of monitoring only DFF-type endpoints. Third, a unified architecture that integrates both frequency and voltage scaling is presented to alleviate the problems of the off-chip voltage regulation. Fabricated in 40 nm CMOS, a Cortex M0+ CPU with AVFS achieves voltage reductions between 15.4% and 29.5% and power savings ranging from 32.3% to 49.3% at 50–100 MHz across SS/TT/FF corners.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"229-232"},"PeriodicalIF":2.0,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144880468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-24DOI: 10.1109/LSSC.2025.3592246
Chun-Sheng Lin;Chih-Hsueh Lin;Chun-Hsing Li
A 240-GHz direct-conversion transmitter (TX), consisting of an LO chain and fundamental I/Q mixers, is proposed for sub-THz communication applications. The LO chain integrates phase-shifter-embedded impedance matching networks (IMNs) and frequency tripler with an optimized harmonic IMN, delivering I/Q LO signals at 240 GHz with high output power, 360° phase shifting range, and I/Q phase calibration capability. The I/Q mixer incorporates two transformer baluns for I/Q signal combining and ground-shielding structures, ensuring layout symmetry and reducing coupling. This can significantly enhance the image rejection ratio (IMRR) and suppress LO feedthrough (LOFT). Fabricated in a 40-nm CMOS process, the proposed TX provides an output power of -11.7 dBm at 240 GHz with a 3-dB bandwidth (BW) from 224 to 244 GHz. It achieves LOFT suppression and IMRR better than -17.7 and -16.3 dBc, respectively, within the 3-dB BW.
{"title":"A 240-GHz Sub-THz Direct-Conversion Transmitter With I/Q Phase Calibration in 40-nm CMOS","authors":"Chun-Sheng Lin;Chih-Hsueh Lin;Chun-Hsing Li","doi":"10.1109/LSSC.2025.3592246","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3592246","url":null,"abstract":"A 240-GHz direct-conversion transmitter (TX), consisting of an LO chain and fundamental I/Q mixers, is proposed for sub-THz communication applications. The LO chain integrates phase-shifter-embedded impedance matching networks (IMNs) and frequency tripler with an optimized harmonic IMN, delivering I/Q LO signals at 240 GHz with high output power, 360° phase shifting range, and I/Q phase calibration capability. The I/Q mixer incorporates two transformer baluns for I/Q signal combining and ground-shielding structures, ensuring layout symmetry and reducing coupling. This can significantly enhance the image rejection ratio (IMRR) and suppress LO feedthrough (LOFT). Fabricated in a 40-nm CMOS process, the proposed TX provides an output power of -11.7 dBm at 240 GHz with a 3-dB bandwidth (BW) from 224 to 244 GHz. It achieves LOFT suppression and IMRR better than -17.7 and -16.3 dBc, respectively, within the 3-dB BW.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"225-228"},"PeriodicalIF":2.0,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144858650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a multiclass, asymmetric digital Doherty power amplifier (DDPA) for Bluetooth low energy (BLE) applications, that achieves high efficiency at full-scale as well as at 8.6-dB back-off using a single 0.7-V supply voltage. The proposed DDPA is made of two power-combined switched-capacitor power amplifiers (SCPAs) and uses an on-chip, compact matching network. The DDPA is implemented in a 22-nm bulk CMOS technology, with the main goal of supporting BLE power classes 1.5, 2, and 3 efficiently. The proposed DDPA shows a peak drain efficiency (DE) of 41% at 10.5-dBm full-scale output power, and features an output spectrum compliant with the BLE spectrum emission mask.
{"title":"A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS","authors":"Edoardo Baiesi Fietta;David Seebacher;Davide Ponton;Andrea Bevilacqua","doi":"10.1109/LSSC.2025.3591570","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3591570","url":null,"abstract":"This letter presents a multiclass, asymmetric digital Doherty power amplifier (DDPA) for Bluetooth low energy (BLE) applications, that achieves high efficiency at full-scale as well as at 8.6-dB back-off using a single 0.7-V supply voltage. The proposed DDPA is made of two power-combined switched-capacitor power amplifiers (SCPAs) and uses an on-chip, compact matching network. The DDPA is implemented in a 22-nm bulk CMOS technology, with the main goal of supporting BLE power classes 1.5, 2, and 3 efficiently. The proposed DDPA shows a peak drain efficiency (DE) of 41% at 10.5-dBm full-scale output power, and features an output spectrum compliant with the BLE spectrum emission mask.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"217-220"},"PeriodicalIF":2.0,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144858639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A mixed-precision analog compute-in-memory (Mix-ACIM) is presented for mixed-precision vector-matrix multiplication (VMM). The design features an all-analog current-domain fixed-point (FxP) VMM with floating-point conversion and feature restoration. A 28 nm CMOS test chip shows 41 TOPS/W and 24 TOPS/mm2 for FxP (8-bit input/weight and 12-bit output) and 24.18 TFLOPS/W and 3.3 TFLOPS/mm2 for 16-bit floating-point equivalent operation.
{"title":"MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication","authors":"Wei-Chun Wang;Shida Zhang;Laith Shamieh;Narasimha Vasishta Kidambi;Isha Chakraborty;Saibal Mukhopadhyay","doi":"10.1109/LSSC.2025.3590757","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3590757","url":null,"abstract":"A mixed-precision analog compute-in-memory (Mix-ACIM) is presented for mixed-precision vector-matrix multiplication (VMM). The design features an all-analog current-domain fixed-point (FxP) VMM with floating-point conversion and feature restoration. A 28 nm CMOS test chip shows 41 TOPS/W and 24 TOPS/mm2 for FxP (8-bit input/weight and 12-bit output) and 24.18 TFLOPS/W and 3.3 TFLOPS/mm2 for 16-bit floating-point equivalent operation.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"213-216"},"PeriodicalIF":2.0,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144831853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-22DOI: 10.1109/LSSC.2025.3591584
Alican Caglar;Imri Fattal;Clement Godfrin;Roy Li;Steven Van Winckel;Kristiaan De Greve;Piet Wambacq;Jan Craninckx
This letter demonstrates a DC demultiplexer using CMOS switches with extremely low OFF-state current at mK temperatures. The DC demultiplexer is designed to reduce the number of interconnections needed for voltage biasing of large-scale spin qubit arrays. The demultiplexer utilizes a T-switch structure and thick-oxide devices in a 65 nm bulk CMOS technology to avoid current leakage in the OFF-state of switches at mK temperatures, which enables preservation of a voltage stored on a capacitor without the need for resampling thereby reducing dynamic power consumption. The demultiplexer has a static power consumption of 33 nW with 4 inputs and 16 outputs, which can be scaled up using the SPI interface of the demultiplexer in a daisy-chain configuration. With its scalability, ultralow static power dissipation, and extremely low OFF-leakage current, the DC demultiplexer can help mitigate the wiring bottleneck of spin-based quantum computers at the base stage of dilution refrigerators.
{"title":"A Scalable mK DC Demultiplexer With Extremely Low OFF-Leakage CMOS Switches for Biasing of Spin Qubits","authors":"Alican Caglar;Imri Fattal;Clement Godfrin;Roy Li;Steven Van Winckel;Kristiaan De Greve;Piet Wambacq;Jan Craninckx","doi":"10.1109/LSSC.2025.3591584","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3591584","url":null,"abstract":"This letter demonstrates a DC demultiplexer using CMOS switches with extremely low OFF-state current at mK temperatures. The DC demultiplexer is designed to reduce the number of interconnections needed for voltage biasing of large-scale spin qubit arrays. The demultiplexer utilizes a T-switch structure and thick-oxide devices in a 65 nm bulk CMOS technology to avoid current leakage in the OFF-state of switches at mK temperatures, which enables preservation of a voltage stored on a capacitor without the need for resampling thereby reducing dynamic power consumption. The demultiplexer has a static power consumption of 33 nW with 4 inputs and 16 outputs, which can be scaled up using the SPI interface of the demultiplexer in a daisy-chain configuration. With its scalability, ultralow static power dissipation, and extremely low OFF-leakage current, the DC demultiplexer can help mitigate the wiring bottleneck of spin-based quantum computers at the base stage of dilution refrigerators.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"221-224"},"PeriodicalIF":2.0,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144858649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-16DOI: 10.1109/LSSC.2025.3589568
Yan Chen;Gaofeng Jin;Haojie Xu;Yu Cui;Lei Zeng;Xiang Gao
This work presents an 8.5–14 GHz dual-path sampling phase detection (SPD)/phase frequency detection (PFD) phase-locked loop (PLL) (DP-SPFDPLL), with extended frequency/phase detection ranges, built-in frequency-locked loop (FLL) function, and stable loop bandwidth across PVT corners. An SPD and a PFD are placed on the dual paths, responsible for phase/frequency locking and temperature drift tracking. An SPD replica is introduced to align the locking points of the integral and proportional paths. A Slew Rate Calibration technique using a Ring Oscillator is proposed to make the slew rate of sampling ramps stable. Implemented in 7 nm FinFET, the 8.5–14 GHz DP-SPFDPLL achieves $75~fs_{rms}$ integrated jitter and −252 dB PLL Figure-of-Merit (FoM)J.
{"title":"A Dual-Path SPD/PFD PLL With PVT-Insensitive Loop Bandwidth","authors":"Yan Chen;Gaofeng Jin;Haojie Xu;Yu Cui;Lei Zeng;Xiang Gao","doi":"10.1109/LSSC.2025.3589568","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3589568","url":null,"abstract":"This work presents an 8.5–14 GHz dual-path sampling phase detection (SPD)/phase frequency detection (PFD) phase-locked loop (PLL) (DP-SPFDPLL), with extended frequency/phase detection ranges, built-in frequency-locked loop (FLL) function, and stable loop bandwidth across PVT corners. An SPD and a PFD are placed on the dual paths, responsible for phase/frequency locking and temperature drift tracking. An SPD replica is introduced to align the locking points of the integral and proportional paths. A Slew Rate Calibration technique using a Ring Oscillator is proposed to make the slew rate of sampling ramps stable. Implemented in 7 nm FinFET, the 8.5–14 GHz DP-SPFDPLL achieves <inline-formula> <tex-math>$75~fs_{rms}$ </tex-math></inline-formula> integrated jitter and −252 dB PLL Figure-of-Merit (FoM)J.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"237-240"},"PeriodicalIF":2.0,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Edge computing devices demand efficient transposable computing architectures to enable on-chip learning, necessitating novel hardware designs that balance performance and flexibility. We present an RRAM-based compute-in-memory macro capable of supporting both in-situ forward and backward propagation operations. The design incorporates an orthogonal-WL array structure with weight-level parallelism adjustment and a precision-driven input mechanism to enable flexible transposable computing. Additionally, optimized ADCs provide high throughput while maintaining area efficiency. The work exhibits a SOTA normalized area efficiency of 126.7 TOPS/mm2/bit, an energy efficiency of 2348.96 TOPS/W/bit, and a storage density of 4.84 Mb/mm2.
{"title":"A RRAM-Based CIM Design With in-Situ Transposable Computing and Hybrid-Precision Scheme for Edge Learning","authors":"Qiumeng Wei;Peng Yao;Dong Wu;Qi Qin;Bin Gao;Qingtian Zhang;Sining Pan;Jianshi Tang;He Qian;Lu Jie;Huaqiang Wu","doi":"10.1109/LSSC.2025.3589580","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3589580","url":null,"abstract":"Edge computing devices demand efficient transposable computing architectures to enable on-chip learning, necessitating novel hardware designs that balance performance and flexibility. We present an RRAM-based compute-in-memory macro capable of supporting both in-situ forward and backward propagation operations. The design incorporates an orthogonal-WL array structure with weight-level parallelism adjustment and a precision-driven input mechanism to enable flexible transposable computing. Additionally, optimized ADCs provide high throughput while maintaining area efficiency. The work exhibits a SOTA normalized area efficiency of 126.7 TOPS/mm2/bit, an energy efficiency of 2348.96 TOPS/W/bit, and a storage density of 4.84 Mb/mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"205-208"},"PeriodicalIF":2.0,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144773316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We developed a 55 nm CMOS static random access memory (SRAM) chip that scans all data every 125 ns and outputs timestamped soft error data via an SPI interface through a FIFO. The proposed system, consisting of the developed chip and particle detectors, enables event-wise soft error measurement and precise identification of single bit upset and multiple-cell upsets (MCUs), thus resolving misclassifications such as Pseudo- and Distant MCUs that conventional methods cannot distinguish. An 80-MeV proton irradiation experiment at RARiS, Tohoku University verified the system operation. Timestamps between the SRAM chip and the particle detectors were successfully synchronized, accounting for PLL disturbances caused by radiation. Event building was achieved by determining a reset offset with sub-ns resolution, and spatial synchronization was maintained within several tens of micrometers.
{"title":"A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement","authors":"Yuibi Gomi;Akira Sato;Waleed Madany;Kenichi Okada;Satoshi Adachi;Masatoshi Itoh;Masanori Hashimoto","doi":"10.1109/LSSC.2025.3589611","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3589611","url":null,"abstract":"We developed a 55 nm CMOS static random access memory (SRAM) chip that scans all data every 125 ns and outputs timestamped soft error data via an SPI interface through a FIFO. The proposed system, consisting of the developed chip and particle detectors, enables event-wise soft error measurement and precise identification of single bit upset and multiple-cell upsets (MCUs), thus resolving misclassifications such as Pseudo- and Distant MCUs that conventional methods cannot distinguish. An 80-MeV proton irradiation experiment at RARiS, Tohoku University verified the system operation. Timestamps between the SRAM chip and the particle detectors were successfully synchronized, accounting for PLL disturbances caused by radiation. Event building was achieved by determining a reset offset with sub-ns resolution, and spatial synchronization was maintained within several tens of micrometers.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"245-248"},"PeriodicalIF":2.0,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144916321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-10DOI: 10.1109/LSSC.2025.3587763
Suyash Shrivastava;Vaishali Choudhary;Pydi Ganga Bahubalindruni
This letter presents a novel voltage-controlled LC oscillators (LCO) designed for energy-efficient wearable applications. The circuit employs a compact AIND topology paired with cross-coupled transistors to generate sustained oscillations. The active inductor (AIND) has been implemented with four transistors. Cross-coupled transistors provide negative resistance to circumvent losses due to parasitic resistance, enabling robust oscillation while minimizing area. This LCO is fabricated on a $27~ mu $ m thick flexible polyimide substrate using all enhancement n-type amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) technology. From measurements, the LCO has shown a wide tuning range (power consumption) of 152 kHz ($10.4~ mu $ W)–1.9 MHz ($450~ mu $ W), when the supply voltage (VDD) is swept from 0.8 to 2.5 V, respectively. Moreover, the LCO exhibits a phase noise of –94.26 and –90 dBc/Hz at a offset frequency of 10 kHz at a VDD of 2 and 0.8 V, respectively. The average tuning sensitivity $(K_{text {LCO}})$ is around 985 kHz/V. Reproducibility and stress dependent stability of the LCO has been validated from multiple sample’s experimental characterization. This circuit occupies a total active area of 0.03 mm2. These parameters indicate that the proposed LCO can find potential applications in on-chip clock generation to implement compact wearable devices.
这封信提出了一种新型的电压控制LC振荡器（LCO），专为节能可穿戴应用而设计。该电路采用紧凑的AIND拓扑与交叉耦合晶体管配对以产生持续振荡。有源电感（AIND）由四个晶体管实现。交叉耦合晶体管提供负电阻以避免由于寄生电阻造成的损耗，在使面积最小化的同时实现鲁棒振荡。该LCO采用全增强n型非晶铟镓氧化锌（a- igzo）薄膜晶体管（TFT）技术，在27~ mu $ m厚的柔性聚酰亚胺衬底上制备。从测量结果来看，当电源电压（VDD）分别从0.8到2.5 V扫频时，LCO的调谐范围（功耗）为152 kHz ($10.4~ mu $ W) -1.9 MHz （$450~ mu $ W）。此外，在VDD为2和0.8 V时，LCO在失调频率为10 kHz时的相位噪声分别为-94.26和-90 dBc/Hz。平均调谐灵敏度$(K_{text {LCO}})$约为985 kHz/V。通过多个样品的实验表征，验证了LCO的重复性和应力依赖性稳定性。该电路的总有效面积为0.03 mm2。这些参数表明，所提出的LCO可以在片上时钟生成中找到潜在的应用，以实现紧凑的可穿戴设备。
{"title":"A Compact Low Power Active Oscillator Using Oxide TFTs on a Flexible Foil","authors":"Suyash Shrivastava;Vaishali Choudhary;Pydi Ganga Bahubalindruni","doi":"10.1109/LSSC.2025.3587763","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3587763","url":null,"abstract":"This letter presents a novel voltage-controlled LC oscillators (LCO) designed for energy-efficient wearable applications. The circuit employs a compact AIND topology paired with cross-coupled transistors to generate sustained oscillations. The active inductor (AIND) has been implemented with four transistors. Cross-coupled transistors provide negative resistance to circumvent losses due to parasitic resistance, enabling robust oscillation while minimizing area. This LCO is fabricated on a <inline-formula> <tex-math>$27~ mu $ </tex-math></inline-formula>m thick flexible polyimide substrate using all enhancement n-type amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) technology. From measurements, the LCO has shown a wide tuning range (power consumption) of 152 kHz (<inline-formula> <tex-math>$10.4~ mu $ </tex-math></inline-formula>W)–1.9 MHz (<inline-formula> <tex-math>$450~ mu $ </tex-math></inline-formula>W), when the supply voltage (VDD) is swept from 0.8 to 2.5 V, respectively. Moreover, the LCO exhibits a phase noise of –94.26 and –90 dBc/Hz at a offset frequency of 10 kHz at a VDD of 2 and 0.8 V, respectively. The average tuning sensitivity <inline-formula> <tex-math>$(K_{text {LCO}})$ </tex-math></inline-formula> is around 985 kHz/V. Reproducibility and stress dependent stability of the LCO has been validated from multiple sample’s experimental characterization. This circuit occupies a total active area of 0.03 mm2. These parameters indicate that the proposed LCO can find potential applications in on-chip clock generation to implement compact wearable devices.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"209-212"},"PeriodicalIF":2.0,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144773263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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