This letter presents a digital-to-analog-converter/analog-to-digital converter (DAC/ADC)-based multicarrier transceiver fabricated in a 22-nm FinFET technology. The multicarrier signaling scheme utilizes orthogonally spaced carriers for spectral efficient band spacing and exhibit jitter robustness compared to conventional baseband pulse amplitude-based signaling. The transmitter has a polar digital signal processor (DSP) to generate the equalized codes driving the 7-b phase DACs, and 7-b amplitude DACs with 2-b predistortion to yield 1.2-Vppd swing. The multicarrier receiver front-end ADC outputs are equalized with a MIMO DSP backend to compensate for the intersymbol interference and interchannel interference. The measured transceiver at 56 Gb/s through a 40.8-dB loss at 14-GHz channel showed a jitter tolerance of up to 1.21 psrms at BER$lt 10{^{-}4 }$ with 7.82-pJ/bit power efficiency.
{"title":"A 56-Gb/s DAC/ADC-Based Multicarrier Transceiver With TX Polar DSP and RX MIMO-DSP for >40-dB Loss Channel","authors":"Srujan Kumar Kaile;Julian Camilo Gomez Diaz;Yuanming Zhu;Il-Min Yi;Tong Liu;Sebastian Hoyos;Samuel Palermo","doi":"10.1109/LSSC.2025.3562615","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3562615","url":null,"abstract":"This letter presents a digital-to-analog-converter/analog-to-digital converter (DAC/ADC)-based multicarrier transceiver fabricated in a 22-nm FinFET technology. The multicarrier signaling scheme utilizes orthogonally spaced carriers for spectral efficient band spacing and exhibit jitter robustness compared to conventional baseband pulse amplitude-based signaling. The transmitter has a polar digital signal processor (DSP) to generate the equalized codes driving the 7-b phase DACs, and 7-b amplitude DACs with 2-b predistortion to yield 1.2-Vppd swing. The multicarrier receiver front-end ADC outputs are equalized with a MIMO DSP backend to compensate for the intersymbol interference and interchannel interference. The measured transceiver at 56 Gb/s through a 40.8-dB loss at 14-GHz channel showed a jitter tolerance of up to 1.21 psrms at BER<inline-formula> <tex-math>$lt 10{^{-}4 }$ </tex-math></inline-formula> with 7.82-pJ/bit power efficiency.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"125-128"},"PeriodicalIF":2.2,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a single-ended offset-compensating (SEOC) with ground precharge bit-line sense amplifier (BLSA). It uses a ground (GND) precharge (PRE) configuration to overcome its limited headroom margin. The single-ended topology that exploits a charge-transfer amplification can eliminate a redundant edge blocks and additional reference circuitry for GND PRE, while maintaining energy efficiency. It is fabricated in a 25-nm DRAM process and compared with offset-compensation sense amplifier (OCSA). The proposed BLSA can achieve 98% decrease in fail bit count (FBC) compared to OCSA at 0.8 V supply voltage and achieve less than 1% performance degradation without redundant edge blocks.
{"title":"A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier With Ground Precharge and Charge Transfer Pre Sensing for Sub-1V DRAM","authors":"Changyoung Lee;Youngseok Park;Hyunchul Yoon;Seryeong Yoon;Donggeon Kim;Bokyeon Won;Junhwa Song;Injae Bae;Jae-Joon Song;Kyuchang Kang;Jaehyuk Kim;Kyungrak Cho;Incheol Nam;Jungdon Ihm;Younghun Seo;Changsik Yoo;Sangjun Hwang","doi":"10.1109/LSSC.2025.3561280","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3561280","url":null,"abstract":"This letter presents a single-ended offset-compensating (SEOC) with ground precharge bit-line sense amplifier (BLSA). It uses a ground (GND) precharge (PRE) configuration to overcome its limited headroom margin. The single-ended topology that exploits a charge-transfer amplification can eliminate a redundant edge blocks and additional reference circuitry for GND PRE, while maintaining energy efficiency. It is fabricated in a 25-nm DRAM process and compared with offset-compensation sense amplifier (OCSA). The proposed BLSA can achieve 98% decrease in fail bit count (FBC) compared to OCSA at 0.8 V supply voltage and achieve less than 1% performance degradation without redundant edge blocks.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"145-148"},"PeriodicalIF":2.2,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144125646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-15DOI: 10.1109/LSSC.2025.3560676
Yong-Jun Jo;Chufeng Yang;Yuanjin Zheng;Tony Tae-Hyoung Kim
Various data-driven computation-in-memory (CIM) architectures have been proposed to reduce inference energy. However, most data-driven CIM architectures require specific conditions to achieve energy savings (e.g., zero skip requires a ReLU activation function). This letter proposes a convolutional window-inspired similarity-aware CIM that saves energy by predicting the current output based on the previous one, which is applicable in most cases where the neural network is based on convolution. In addition, this letter introduces a novel transposable architecture to enhance linearity and an analog-to-digital converter (ADC) for improved area efficiency. The prototype was fabricated with 65 nm process and achieved the highest SWaP FoM as 19.04 TOPS/W$times $ Mb/mm2 among the state-of-the-art transposable CIMs.
{"title":"Convolutional Window-Inspired Similarity-Aware Computation-in-Memory for Energy Saving","authors":"Yong-Jun Jo;Chufeng Yang;Yuanjin Zheng;Tony Tae-Hyoung Kim","doi":"10.1109/LSSC.2025.3560676","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3560676","url":null,"abstract":"Various data-driven computation-in-memory (CIM) architectures have been proposed to reduce inference energy. However, most data-driven CIM architectures require specific conditions to achieve energy savings (e.g., zero skip requires a ReLU activation function). This letter proposes a convolutional window-inspired similarity-aware CIM that saves energy by predicting the current output based on the previous one, which is applicable in most cases where the neural network is based on convolution. In addition, this letter introduces a novel transposable architecture to enhance linearity and an analog-to-digital converter (ADC) for improved area efficiency. The prototype was fabricated with 65 nm process and achieved the highest SWaP FoM as 19.04 TOPS/W<inline-formula> <tex-math>$times $ </tex-math></inline-formula>Mb/mm2 among the state-of-the-art transposable CIMs.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"121-124"},"PeriodicalIF":2.2,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents an energy-efficient MOS-based temperature sensor, enhanced through transducer and readout circuit integrated design, LSB-first SAR, and energy-efficient comparator. The transducer and readout circuit integrated design reduces noise by combining two blocks into one. With temperature-dependent offset voltage, the comparator integrates with the LSB-first SAR and is optimized for energy efficiency. The LSB-first SAR reduces the number of cycles and energy consumption. In addition, an asynchronous clock controls the circuit, eliminating the need for a timing reference and adjusting speed to temperature to increase measurement robustness. The temperature sensor was fabricated with a 65 nm CMOS process, and the sensor has −60 to $145~^{circ }$ C measurement range. After two-point calibration with a second-order polynomial, errors are −1.93/${+} 1.44~^{circ }$ C over the entire range and −0.96/${+} 0.94~^{circ }$ C from −43 to $137~^{circ }$ C. At room temperature, the sensor achieves 71.8 mK resolution and 41.9 pJ per conversion, resulting in the best resolution figure-of-merit of 216 fJ$cdot $ K2 among MOS-based sensors.
{"title":"A MOS-Based Temperature Sensor With Energy-Efficient Techniques","authors":"Jooeun Kim;Jeongmyeong Kim;Minkyu Yang;Kyounghun Kang;Wanyeong Jung","doi":"10.1109/LSSC.2025.3559900","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3559900","url":null,"abstract":"This letter presents an energy-efficient MOS-based temperature sensor, enhanced through transducer and readout circuit integrated design, LSB-first SAR, and energy-efficient comparator. The transducer and readout circuit integrated design reduces noise by combining two blocks into one. With temperature-dependent offset voltage, the comparator integrates with the LSB-first SAR and is optimized for energy efficiency. The LSB-first SAR reduces the number of cycles and energy consumption. In addition, an asynchronous clock controls the circuit, eliminating the need for a timing reference and adjusting speed to temperature to increase measurement robustness. The temperature sensor was fabricated with a 65 nm CMOS process, and the sensor has −60 to <inline-formula> <tex-math>$145~^{circ }$ </tex-math></inline-formula>C measurement range. After two-point calibration with a second-order polynomial, errors are −1.93/<inline-formula> <tex-math>${+} 1.44~^{circ }$ </tex-math></inline-formula>C over the entire range and −0.96/<inline-formula> <tex-math>${+} 0.94~^{circ }$ </tex-math></inline-formula>C from −43 to <inline-formula> <tex-math>$137~^{circ }$ </tex-math></inline-formula>C. At room temperature, the sensor achieves 71.8 mK resolution and 41.9 pJ per conversion, resulting in the best resolution figure-of-merit of 216 fJ<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>K2 among MOS-based sensors.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"109-112"},"PeriodicalIF":2.2,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143870918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-08DOI: 10.1109/LSSC.2025.3558928
Chang Xue;Youming Yang;Siyuan He;Gang Du;Yuan Wang;Yandong He
In computing-in-memory (CIM) architecture, it is necessary to reliably adjust the precision according to the specific demands of the application, enabling a tradeoff between high precision and high energy efficiency. In addition, when performing multibit computations, nonlinearity errors between different bits can adversely affect the network’s accuracy. Therefore, this work proposes an 8Kb dual-edge time-domain CIM macro, which incorporates a segmented precision configuration scheme. By mapping the high and low 4 bits of the 8-bit input to the rising and falling edges of the pulse for independent computation, this design mitigates nonlinearity errors between high and low bits. The precision of multiplication-and-accumulation (MAC) operations for both high and low bits can be independently adjusted, ensuring sufficient accuracy while enhancing energy efficiency. This work attains an energy efficiency ranging from 8.03 to 13.20 TOPS/W in the end. For the CIFAR-10 dataset, when the inputs and weights are of 8-bit precision, this work reaches an inference accuracy of 90.27%–91.92%.
{"title":"A Segmented Precision Configurable Computing-in-Memory Macro With Dual-Edge Time-Domain Structure","authors":"Chang Xue;Youming Yang;Siyuan He;Gang Du;Yuan Wang;Yandong He","doi":"10.1109/LSSC.2025.3558928","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3558928","url":null,"abstract":"In computing-in-memory (CIM) architecture, it is necessary to reliably adjust the precision according to the specific demands of the application, enabling a tradeoff between high precision and high energy efficiency. In addition, when performing multibit computations, nonlinearity errors between different bits can adversely affect the network’s accuracy. Therefore, this work proposes an 8Kb dual-edge time-domain CIM macro, which incorporates a segmented precision configuration scheme. By mapping the high and low 4 bits of the 8-bit input to the rising and falling edges of the pulse for independent computation, this design mitigates nonlinearity errors between high and low bits. The precision of multiplication-and-accumulation (MAC) operations for both high and low bits can be independently adjusted, ensuring sufficient accuracy while enhancing energy efficiency. This work attains an energy efficiency ranging from 8.03 to 13.20 TOPS/W in the end. For the CIFAR-10 dataset, when the inputs and weights are of 8-bit precision, this work reaches an inference accuracy of 90.27%–91.92%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"117-120"},"PeriodicalIF":2.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143871004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-04DOI: 10.1109/LSSC.2025.3557862
Vaishali Choudhary;Pydi Ganga Bahubalindruni
This letter presents a novel low-power, fully dynamic, latched comparator using only n-type, single-gate amorphous-indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) on a $27~mu $ m thick polyimide substrate. This circuit demonstrates a stable performance up to an input signal frequency of 15 kHz with 1-MHz clock. By employing a pseudo-CMOS bootstrapped load, it achieved an output voltage swing of around 90%, an input-referred offset and noise voltages of 28 mV and 14 mV, respectively from measurements. In addition, it can reliably detect a minimum differential input voltage of 50 mV at a $V_{mathrm { DD}}$ of 4 V, while consuming only $8~mu $ W power. Therefore, this design is well-suited in biomedical wearable devices which typically needs low-power.
{"title":"A Low-Power Fully Dynamic Latched Comparator Using Flexible Oxide TFT Technology","authors":"Vaishali Choudhary;Pydi Ganga Bahubalindruni","doi":"10.1109/LSSC.2025.3557862","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3557862","url":null,"abstract":"This letter presents a novel low-power, fully dynamic, latched comparator using only n-type, single-gate amorphous-indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) on a <inline-formula> <tex-math>$27~mu $ </tex-math></inline-formula>m thick polyimide substrate. This circuit demonstrates a stable performance up to an input signal frequency of 15 kHz with 1-MHz clock. By employing a pseudo-CMOS bootstrapped load, it achieved an output voltage swing of around 90%, an input-referred offset and noise voltages of 28 mV and 14 mV, respectively from measurements. In addition, it can reliably detect a minimum differential input voltage of 50 mV at a <inline-formula> <tex-math>$V_{mathrm { DD}}$ </tex-math></inline-formula> of 4 V, while consuming only <inline-formula> <tex-math>$8~mu $ </tex-math></inline-formula>W power. Therefore, this design is well-suited in biomedical wearable devices which typically needs low-power.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"101-104"},"PeriodicalIF":2.2,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143850040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1109/LSSC.2025.3557524
Mehdi Saberi;Alexandre Schmid
The analysis of the operation of nonlinear circuits, such as voltage level shifters and latched comparators, and therefore the prediction of their propagation delay and power consumption, is challenging. This is because the operating points of the employed nonlinear devices are time-varying. Hence, in this letter, a new approach which uses the trajectory of the operating points of the employed devices is proposed to analyze nonlinear circuits. The proposed method is used to provide a comprehensive study about the operation of the cross-coupled voltage level shifters. The proposed analysis not only formulates the existing contention between the pull-up and pull-down devices but also presents closed-form formulas for the delay as well as the power consumption. Measurement results of a prototype implemented in a standard 0.18-$mu $ m CMOS technology verify the effectiveness of the proposed method.
对电压电平转换器和锁存式比较器等非线性电路的运行进行分析，从而预测其传播延迟和功耗，是一项具有挑战性的工作。这是因为所采用的非线性器件的工作点是时变的。因此，在这封信中，我们提出了一种利用所采用器件的工作点轨迹来分析非线性电路的新方法。所提出的方法用于全面研究交叉耦合电压电平转换器的运行。所提出的分析不仅阐述了上拉和下拉器件之间的现有争论，还提出了延迟和功耗的闭式公式。在标准 0.18 $mu $ m CMOS 技术中实现的原型的测量结果验证了所提方法的有效性。
{"title":"Analysis of Power Consumption and Propagation Delay in Voltage Level Shifters","authors":"Mehdi Saberi;Alexandre Schmid","doi":"10.1109/LSSC.2025.3557524","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3557524","url":null,"abstract":"The analysis of the operation of nonlinear circuits, such as voltage level shifters and latched comparators, and therefore the prediction of their propagation delay and power consumption, is challenging. This is because the operating points of the employed nonlinear devices are time-varying. Hence, in this letter, a new approach which uses the trajectory of the operating points of the employed devices is proposed to analyze nonlinear circuits. The proposed method is used to provide a comprehensive study about the operation of the cross-coupled voltage level shifters. The proposed analysis not only formulates the existing contention between the pull-up and pull-down devices but also presents closed-form formulas for the delay as well as the power consumption. Measurement results of a prototype implemented in a standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS technology verify the effectiveness of the proposed method.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"113-116"},"PeriodicalIF":2.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143871027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1109/LSSC.2025.3557531
Guangxu Shen;Haitao Ma;Chenyang Zhang;Dingyuan Zeng Member;Haoshen Zhu;Wenquan Che
A series of switchable resonators are proposed by incorporating the parasitic effects of two gallium nitride (GaN) high electron mobility transistor (HEMT) devices in this letter, based on which a broadband single-pole double-throw (SPDT) switch is presented with a bandpass response. As for on-chip switches, the ideal transistor is desired to act as a capacitor in its off-state but a resistor in its on-state. In conventional switch designs, the inductive effects of transistors are typically suppressed due to their detrimental impact on impedance matching and isolation. In contrast to this conventional approach, this study proposes a resonator-based design strategy that intentionally exploits and amplifies these inductive characteristics to construct two distinct GaN HEMT-integrated resonators. The first resonator employs the enhanced on-state inductance of a switching transistor combined with an MIM capacitor to form a series resonant network, enabling broadband impedance matching. The second resonator utilizes the large off-state capacitance of a power transistor and a short-circuited transmission line to establish a parallel resonant network. Leveraging the unique properties of these resonators, a broadband switch topology is accordingly proposed and experimentally validated. For demonstration, a SPDT switch is designed and fabricated in a 100 nm GaN-on-Si process. The proposed switch operates from 16 to 33 GHz based on experimental measurements. Two transmission poles are observed in the passband. This result experimentally validates the GaN HEMT-based resonator design.
{"title":"GaN HEMT-Based Resonators Using Parasitic Effects and Its Application to A Ka-band Coupled-Resonator SPDT Switch","authors":"Guangxu Shen;Haitao Ma;Chenyang Zhang;Dingyuan Zeng Member;Haoshen Zhu;Wenquan Che","doi":"10.1109/LSSC.2025.3557531","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3557531","url":null,"abstract":"A series of switchable resonators are proposed by incorporating the parasitic effects of two gallium nitride (GaN) high electron mobility transistor (HEMT) devices in this letter, based on which a broadband single-pole double-throw (SPDT) switch is presented with a bandpass response. As for on-chip switches, the ideal transistor is desired to act as a capacitor in its off-state but a resistor in its on-state. In conventional switch designs, the inductive effects of transistors are typically suppressed due to their detrimental impact on impedance matching and isolation. In contrast to this conventional approach, this study proposes a resonator-based design strategy that intentionally exploits and amplifies these inductive characteristics to construct two distinct GaN HEMT-integrated resonators. The first resonator employs the enhanced on-state inductance of a switching transistor combined with an MIM capacitor to form a series resonant network, enabling broadband impedance matching. The second resonator utilizes the large off-state capacitance of a power transistor and a short-circuited transmission line to establish a parallel resonant network. Leveraging the unique properties of these resonators, a broadband switch topology is accordingly proposed and experimentally validated. For demonstration, a SPDT switch is designed and fabricated in a 100 nm GaN-on-Si process. The proposed switch operates from 16 to 33 GHz based on experimental measurements. Two transmission poles are observed in the passband. This result experimentally validates the GaN HEMT-based resonator design.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"105-108"},"PeriodicalIF":2.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143850828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a $4times 56$ -Gbaud linear transimpedance amplifier (TIA) with low noise and high linearity, designed for linear-drive pluggable optics (LPO) and implemented in 0.13-$mu $ m SiGe-BiCMOS technology (fT/f${_{text {MAX}}} {=} 260$ /350 GHz). The TIA features an inductive shunt-feedback (ISFB) transimpedance stage (TIS) with a $pi $ -topology L-C network as the input stage, achieving wide bandwidth (BW) and low noise despite large photodiode (PD) and packaging parasitic capacitances. Two current-splitting variable gain amplifiers (VGAs) with continuous-time linear equalizer (CTLE) functionality are cascaded after the TIS, providing a gain control range of –12 to +18 dB and accommodating input currents up to 2mApp. A 50-ohm output buffer with T-coil further extends the BW. Measurement results demonstrate a maximum optical-to-electrical transimpedance gain (O/E.ZT) of 73.8 dB$Omega $ , an O/E O/E.BW exceeding 40 GHz, an input-referred noise (IRN) current of $1.9~mu $ Arms, and total harmonic distortion (THD) ¡ 4.5% for a 700-mVpp output swing. The TIA supports 56-Gbaud PAM-4 eye diagrams with PRBS31Q and achieves 9.7-dBm optical modulation amplitude (OMA) sensitivity at the pre-FEC BER limit of $2.4times 10^{-4}$ for 56-Gbaud PAM-4 SSPRQ. The design achieves a power efficiency of 1.67 pJ/bit and occupies an area of $3.14times 1.04$ mm2.
本文介绍了一种$4times 56$ - gbaud线性跨阻放大器（TIA），具有低噪声和高线性度，专为线性驱动可插拔光学器件（LPO）设计，采用0.13- $mu $ m SiGe-BiCMOS技术（fT/f ${_{text {MAX}}} {=} 260$ /350 GHz）实现。该TIA具有电感式并联反馈（ISFB）跨阻级（TIS），其输入级为$pi $ -拓扑L-C网络，尽管具有较大的光电二极管（PD）和封装寄生电容，但仍可实现宽带（BW）和低噪声。两个具有连续时间线性均衡器（CTLE）功能的分流可变增益放大器（vga）级联在TIS之后，提供-12至+18 dB的增益控制范围，可容纳高达2mApp的输入电流。50欧姆输出缓冲器与t线圈进一步扩展了BW。测量结果表明，最大光电透阻增益（O/E. zt）为73.8 dB $Omega $, O/E. O/E。BW超过40 GHz，输入参考噪声（IRN）电流为$1.9~mu $ Arms，总谐波失真（THD）为4.5% for a 700-mVpp output swing. The TIA supports 56-Gbaud PAM-4 eye diagrams with PRBS31Q and achieves 9.7-dBm optical modulation amplitude (OMA) sensitivity at the pre-FEC BER limit of $2.4times 10^{-4}$ for 56-Gbaud PAM-4 SSPRQ. The design achieves a power efficiency of 1.67 pJ/bit and occupies an area of $3.14times 1.04$ mm2.
{"title":"A 4×56 -Gbaud PAM-4 Linear and Low-Noise TIA for Linear-Drive Pluggable Optics","authors":"Wei Chen;Minhao Li;Ming Zhong;Yuan Li;Ying Wu;Pisen Zhou;Patrick Yin Chiang","doi":"10.1109/LSSC.2025.3574875","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3574875","url":null,"abstract":"This letter presents a <inline-formula> <tex-math>$4times 56$ </tex-math></inline-formula>-Gbaud linear transimpedance amplifier (TIA) with low noise and high linearity, designed for linear-drive pluggable optics (LPO) and implemented in 0.13-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m SiGe-BiCMOS technology (fT/f<inline-formula> <tex-math>${_{text {MAX}}} {=} 260$ </tex-math></inline-formula>/350 GHz). The TIA features an inductive shunt-feedback (ISFB) transimpedance stage (TIS) with a <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-topology L-C network as the input stage, achieving wide bandwidth (BW) and low noise despite large photodiode (PD) and packaging parasitic capacitances. Two current-splitting variable gain amplifiers (VGAs) with continuous-time linear equalizer (CTLE) functionality are cascaded after the TIS, providing a gain control range of –12 to +18 dB and accommodating input currents up to 2mApp. A 50-ohm output buffer with T-coil further extends the BW. Measurement results demonstrate a maximum optical-to-electrical transimpedance gain (O/E.ZT) of 73.8 dB<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>, an O/E O/E.BW exceeding 40 GHz, an input-referred noise (IRN) current of <inline-formula> <tex-math>$1.9~mu $ </tex-math></inline-formula>Arms, and total harmonic distortion (THD) ¡ 4.5% for a 700-mVpp output swing. The TIA supports 56-Gbaud PAM-4 eye diagrams with PRBS31Q and achieves 9.7-dBm optical modulation amplitude (OMA) sensitivity at the pre-FEC BER limit of <inline-formula> <tex-math>$2.4times 10^{-4}$ </tex-math></inline-formula> for 56-Gbaud PAM-4 SSPRQ. The design achieves a power efficiency of 1.67 pJ/bit and occupies an area of <inline-formula> <tex-math>$3.14times 1.04$ </tex-math></inline-formula> mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"197-200"},"PeriodicalIF":2.2,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144663709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-28DOI: 10.1109/LSSC.2025.3574413
Yu-Kai Chen;Yi-Fan Tseng;Wei-Zhe Su;Chun-Hsing Li
A 302.5-GHz high-gain CMOS THz amplifier is proposed in this work. An electromagnetic (EM) modeling approach, verified by transistor measurements, is employed to optimize transistor layout, effectively reducing gate resistance and drain-to-gate capacitance. This significantly enhances the transistor’s maximum oscillation frequency $f_{mathrm {max }}$ from 239.7 to 367.5 GHz. Furthermore, a $G_{mathrm {max }}$ -peak-offset-matching technique is proposed to simultaneously optimize active transistors and passive matching networks, significantly increasing the gain by 3.5 dB. Implemented in a 65-nm CMOS technology, the proposed THz amplifier achieves a measured gain of 30.9 dB at 302.5 GHz with an output saturation power of –5.3 dBm while only consuming 35.4 mW from a 1.1 V supply. To the best of the authors’ knowledge, this work exhibits the first experimental validation of the EM modeling approach and achieves the highest reported gain above 200 GHz in bulk CMOS technologies.
{"title":"A 302.5-GHz 30.9-dB-Gain THz Amplifier in 65-nm CMOS","authors":"Yu-Kai Chen;Yi-Fan Tseng;Wei-Zhe Su;Chun-Hsing Li","doi":"10.1109/LSSC.2025.3574413","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3574413","url":null,"abstract":"A 302.5-GHz high-gain CMOS THz amplifier is proposed in this work. An electromagnetic (EM) modeling approach, verified by transistor measurements, is employed to optimize transistor layout, effectively reducing gate resistance and drain-to-gate capacitance. This significantly enhances the transistor’s maximum oscillation frequency <inline-formula> <tex-math>$f_{mathrm {max }}$ </tex-math></inline-formula> from 239.7 to 367.5 GHz. Furthermore, a <inline-formula> <tex-math>$G_{mathrm {max }}$ </tex-math></inline-formula>-peak-offset-matching technique is proposed to simultaneously optimize active transistors and passive matching networks, significantly increasing the gain by 3.5 dB. Implemented in a 65-nm CMOS technology, the proposed THz amplifier achieves a measured gain of 30.9 dB at 302.5 GHz with an output saturation power of –5.3 dBm while only consuming 35.4 mW from a 1.1 V supply. To the best of the authors’ knowledge, this work exhibits the first experimental validation of the EM modeling approach and achieves the highest reported gain above 200 GHz in bulk CMOS technologies.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"165-168"},"PeriodicalIF":2.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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