This letter focuses on improving power added efficiency (PAE) of high-power nonuniform distributed power amplifier (NDPA). A double feeding line matching (DFLM) structure is proposed, where a double-T-type and a $pi $ -type DFLM networks are inserted into drain transmission-line (TL) and gate TL of classical designs, respectively. These optimize load/source impedance for each transistor, improving the output power and PAE. The NPDA monolithic microwave integrated circuit (MMIC) is fabricated with a commercial 0.25-$mu $ m gallium nitride (GaN) process. The measurement results show that the proposed NDPA achieves output power of 37.6-to-40.2 dBm, and PAE of 37.6%-to-50.3% at 8-to-16 GHz, with the chip area of merely 3.5 mm2. The proposed NPDA outperforms the state-of-the-art broadband power amplifier (PA) in PAE with a much smaller chip area.
本文的重点是提高大功率非均匀分布式功率放大器（NDPA）的功率附加效率（PAE）。提出了一种双馈线匹配（DFLM）结构，将双t型和$pi $型DFLM网络分别插入经典设计的漏极输导在线（TL）和栅极输导在线（TL）中。这些优化负载/源阻抗为每个晶体管，提高输出功率和PAE。NPDA单片微波集成电路（MMIC）采用商用0.25- $mu $ m氮化镓（GaN）工艺制备。测量结果表明，该NDPA的输出功率为37.6 ～ 40.2 dBm， PAE为37.6%-to-50.3% at 8-to-16 GHz, with the chip area of merely 3.5 mm2. The proposed NPDA outperforms the state-of-the-art broadband power amplifier (PA) in PAE with a much smaller chip area.
{"title":"A Compact 8-to-16 GHz GaN Nonuniform Distributed PA With Double Feeding Line Matching Structure Presenting 43.2% Average PAE","authors":"Zhaowu Wang;Dexin Shi;Xinyan Li;Shu Ma;Ronglin Chen;Ze Yu;Ziao Wang;Shijie Chen;Xiaochen Tang;Yong Wang","doi":"10.1109/LSSC.2025.3587242","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3587242","url":null,"abstract":"This letter focuses on improving power added efficiency (PAE) of high-power nonuniform distributed power amplifier (NDPA). A double feeding line matching (DFLM) structure is proposed, where a double-T-type and a <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-type DFLM networks are inserted into drain transmission-line (TL) and gate TL of classical designs, respectively. These optimize load/source impedance for each transistor, improving the output power and PAE. The NPDA monolithic microwave integrated circuit (MMIC) is fabricated with a commercial 0.25-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m gallium nitride (GaN) process. The measurement results show that the proposed NDPA achieves output power of 37.6-to-40.2 dBm, and PAE of 37.6%-to-50.3% at 8-to-16 GHz, with the chip area of merely 3.5 mm2. The proposed NPDA outperforms the state-of-the-art broadband power amplifier (PA) in PAE with a much smaller chip area.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"201-204"},"PeriodicalIF":2.0,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-30DOI: 10.1109/LSSC.2025.3584266
Yihao Yang;Dan Li;Nan Qi;Binhao Wang
This letter describes an ultralow-noise, high-speed transimpedance amplifier (TIA) applied to the analog front-end (AFE) circuit of the high-sensitivity optical receiver. A combination of a three-stage amplifier and two positive feedback Miller capacitors is introduced to comprehensively reduce the input-referred noise current (IRNC) of a shunt-feedback TIA (SFTIA) and to extend its bandwidth (BW). The proposed SFTIA utilizes an 80 K$Omega $ resistor as the feedback resistor (RF) and achieves a BW of 2.5 GHz and an average IRNC of only 2 pA/$surd $ Hz in 180 nm CMOS technology, which is the lowest TIA noise reported to date above the GHz BW. Although the fabrication process is not as advanced as the state-of-the-art process, we believe it remains valuable and instructive for a wide variety of applications requiring low noise and high sensitivity.
{"title":"A 2 pA/√Hz Input-Referred Noise TIA in 180-nm CMOS With 2.5 GHz Bandwidth for Optical Receiver","authors":"Yihao Yang;Dan Li;Nan Qi;Binhao Wang","doi":"10.1109/LSSC.2025.3584266","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3584266","url":null,"abstract":"This letter describes an ultralow-noise, high-speed transimpedance amplifier (TIA) applied to the analog front-end (AFE) circuit of the high-sensitivity optical receiver. A combination of a three-stage amplifier and two positive feedback Miller capacitors is introduced to comprehensively reduce the input-referred noise current (IRNC) of a shunt-feedback TIA (SFTIA) and to extend its bandwidth (BW). The proposed SFTIA utilizes an 80 K<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> resistor as the feedback resistor (RF) and achieves a BW of 2.5 GHz and an average IRNC of only 2 pA/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz in 180 nm CMOS technology, which is the lowest TIA noise reported to date above the GHz BW. Although the fabrication process is not as advanced as the state-of-the-art process, we believe it remains valuable and instructive for a wide variety of applications requiring low noise and high sensitivity.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"189-192"},"PeriodicalIF":2.2,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144662025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter proposes a digital low-dropout regulator (DLDO)-assisted buck converter featuring one-step computational droop compensation and DLDO feedback-controlled current handover. The 28-nm test chip achieves a 68-mV droop voltage and a 112-ns settling time for a 1A/0.8ns load step while maintaining a high-peak efficiency of 95.5%.
{"title":"Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency","authors":"Yichen Xu;Zhaoqing Wang;Rentao Wan;Suhwan Kim;Minxiang Gong;Ram Krishnamurthy;Xin Zhang;Mingoo Seok","doi":"10.1109/LSSC.2025.3581844","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3581844","url":null,"abstract":"This letter proposes a digital low-dropout regulator (DLDO)-assisted buck converter featuring one-step computational droop compensation and DLDO feedback-controlled current handover. The 28-nm test chip achieves a 68-mV droop voltage and a 112-ns settling time for a 1A/0.8ns load step while maintaining a high-peak efficiency of 95.5%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"193-196"},"PeriodicalIF":2.0,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144751050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a compact and energy-efficient analog front-end (AFE) circuit for fully digital beamforming in endoscopic and catheter-based 3-D ultrasound imaging. The AFE converts single-ended analog input from each transducer element into a 10-bit digital output through a low-noise amplifier (LNA) and a 20-MS/s SAR ADC. To minimize chip area and power consumption, the LNA employs a capacitor-splitting inverter-based amplifier with dynamic power control, while the ADC utilizes unit-length capacitors and digital error correction. A modified monotonic switching improves the conversion rate, and the kickback noise is reduced by an enhanced Elzakker comparator. Fabricated in a 0.18-$mu $ m CMOS process, the ultrasound AFE occupies a low silicon area of 0.052 mm2/channel, achieves 74.93-dB dynamic range (DR), 10.9-nV/$surd $ Hz input referred noise, and −58.33-dB total harmonic distortion (THD). The average power consumption is 1.34 mW/channel.
这封信提出了一个紧凑和节能的模拟前端（AFE）电路，用于内窥镜和基于导管的三维超声成像的全数字波束形成。AFE通过低噪声放大器（LNA）和20 ms /s SAR ADC将来自每个传感器元件的单端模拟输入转换为10位数字输出。为了最大限度地减少芯片面积和功耗，LNA采用基于电容分裂逆变器的放大器和动态功率控制，而ADC采用单位长度电容器和数字纠错。改进的单调开关提高了转换率，并且通过增强的Elzakker比较器降低了反踢噪声。超声AFE采用0.18- $ $ μ $ m CMOS工艺制造，低硅面积为0.052 mm2/通道，动态范围为74.93 db，输入参考噪声为10.9 nv / $ $ surd $ Hz，总谐波失真（THD）为- 58.33 db。平均功耗为1.34 mW/通道。
{"title":"A 10.9-nV/√Hz, 74.9-dB DR, 20-MS/s Ultrasound Analog Front End for Fully Digital Beamforming","authors":"Changde Ding;Yan Zhu;Pengjie Wang;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2025.3581584","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3581584","url":null,"abstract":"This letter presents a compact and energy-efficient analog front-end (AFE) circuit for fully digital beamforming in endoscopic and catheter-based 3-D ultrasound imaging. The AFE converts single-ended analog input from each transducer element into a 10-bit digital output through a low-noise amplifier (LNA) and a 20-MS/s SAR ADC. To minimize chip area and power consumption, the LNA employs a capacitor-splitting inverter-based amplifier with dynamic power control, while the ADC utilizes unit-length capacitors and digital error correction. A modified monotonic switching improves the conversion rate, and the kickback noise is reduced by an enhanced Elzakker comparator. Fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process, the ultrasound AFE occupies a low silicon area of 0.052 mm2/channel, achieves 74.93-dB dynamic range (DR), 10.9-nV/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz input referred noise, and −58.33-dB total harmonic distortion (THD). The average power consumption is 1.34 mW/channel.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"185-188"},"PeriodicalIF":2.2,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144597896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a 7-bit pipelined subranging ADC that integrates a 3-bit flash ADC with a ring VCO-based quantizer. A resistor-ladder-based residue shifter (RLRS) replaces traditional residue amplifiers, efficiently shifting the residue voltage into the most linear region of the $K_{textrm {VCO}}$ , thereby eliminating the need for post-linearity calibration. Fabricated in a 28-nm FDSOI process, the ADC occupies an area of 0.009 mm2 and achieves an SNDR of 39.26 dB and an SFDR of 48.01 dB at 2.5 GS/s, while consuming 6.5 mW of power. This results in a Walden FOM of 34.6 fJ/conversion step.
{"title":"A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique","authors":"Sungjin Kim;Jeonghyun Lee;Yoonse Cho;Jintae Kim;Jaehyouk Choi;Heein Yoon","doi":"10.1109/LSSC.2025.3578546","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3578546","url":null,"abstract":"This letter presents a 7-bit pipelined subranging ADC that integrates a 3-bit flash ADC with a ring VCO-based quantizer. A resistor-ladder-based residue shifter (RLRS) replaces traditional residue amplifiers, efficiently shifting the residue voltage into the most linear region of the <inline-formula> <tex-math>$K_{textrm {VCO}}$ </tex-math></inline-formula>, thereby eliminating the need for post-linearity calibration. Fabricated in a 28-nm FDSOI process, the ADC occupies an area of 0.009 mm2 and achieves an SNDR of 39.26 dB and an SFDR of 48.01 dB at 2.5 GS/s, while consuming 6.5 mW of power. This results in a Walden FOM of 34.6 fJ/conversion step.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"177-180"},"PeriodicalIF":2.2,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144524330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-11DOI: 10.1109/LSSC.2025.3578942
Wei-Yu Lin;Jun-Chau Chien
Implementing dual-resonance class-F oscillators with transformer feedback beyond 60 GHz poses significant challenges due to the limited third-harmonic tank impedance when using small coils with low coupling factors. To address these limitations and leverage the phase noise advantages of class-F operation, this letter introduces a standing-wave oscillator (SWO) topology featuring an on-chip multiband transmission-line (t-line) resonator loaded with harmonically tuned open stubs. The proposed design enhances third-harmonic resonance while facilitating precise alignment of the oscillation frequencies. Three voltage-controlled oscillators (VCOs) were implemented using TSMC’s 65-nm LP technology, demonstrating that the proposed class-F half-wavelength SWO achieves phase noise improvements of 3.1 and 6.4 dB at a 1-MHz offset compared to conventional SWO and transformer-based class-F VCO, respectively.
{"title":"A Millimeter-Wave Standing-Wave Oscillator With Frequency-Specific Wave-Velocity Control Demonstrating Class-F Effects","authors":"Wei-Yu Lin;Jun-Chau Chien","doi":"10.1109/LSSC.2025.3578942","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3578942","url":null,"abstract":"Implementing dual-resonance class-F oscillators with transformer feedback beyond 60 GHz poses significant challenges due to the limited third-harmonic tank impedance when using small coils with low coupling factors. To address these limitations and leverage the phase noise advantages of class-F operation, this letter introduces a standing-wave oscillator (SWO) topology featuring an on-chip multiband transmission-line (t-line) resonator loaded with harmonically tuned open stubs. The proposed design enhances third-harmonic resonance while facilitating precise alignment of the oscillation frequencies. Three voltage-controlled oscillators (VCOs) were implemented using TSMC’s 65-nm LP technology, demonstrating that the proposed class-F half-wavelength SWO achieves phase noise improvements of 3.1 and 6.4 dB at a 1-MHz offset compared to conventional SWO and transformer-based class-F VCO, respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"181-184"},"PeriodicalIF":2.2,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144524414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a 45V high-precision current-feedback instrumentation amplifier (CFIA) that combines both chopping and auto-zeroing (AZ) to achieve 1.8-$mu $ V input offset (10 samples) and 33.5-$mu $ V input-referred ripple. The AZ is duty cycled to minimize power and silicon area, with a parallel auxiliary path operating during AZ to keep the amplifier functioning properly. To improve the limited input signal range of conventional CFIA, an input common-mode (CM) voltage tracking circuit improves the input common-mode voltage range (CMVR) up to 42 V and CMRR to 132-dB, respectively. Further combined with source degeneration resistors, the input differential-mode voltage range (DMVR) is also increased to 800mV at 1% THD. The CFIA is implemented in a standard 0.18-$mu $ m BCD process and consumes $294.5~mu $ A. This translates into a competitive efficiency in terms of GBW/supply current of 134 kHz/$mu $ A.
{"title":"A 45-V Auto-Zero-Stabilized Chopper Instrumentation Amplifier With 1.8- μ V Offset, 33.5- μ V Ripple, and 42-V Common-Mode Input Range","authors":"Jiahao Wang;Shen Ye;Shiqi Zhang;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2025.3576393","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3576393","url":null,"abstract":"This letter presents a 45V high-precision current-feedback instrumentation amplifier (CFIA) that combines both chopping and auto-zeroing (AZ) to achieve 1.8-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>V input offset (10 samples) and 33.5-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>V input-referred ripple. The AZ is duty cycled to minimize power and silicon area, with a parallel auxiliary path operating during AZ to keep the amplifier functioning properly. To improve the limited input signal range of conventional CFIA, an input common-mode (CM) voltage tracking circuit improves the input common-mode voltage range (CMVR) up to 42 V and CMRR to 132-dB, respectively. Further combined with source degeneration resistors, the input differential-mode voltage range (DMVR) is also increased to 800mV at 1% THD. The CFIA is implemented in a standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m BCD process and consumes <inline-formula> <tex-math>$294.5~mu $ </tex-math></inline-formula>A. This translates into a competitive efficiency in terms of GBW/supply current of 134 kHz/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"173-176"},"PeriodicalIF":2.2,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144519461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-02DOI: 10.1109/LSSC.2025.3575536
Cody J. Ellington;Sandeep Hari;Brian A. Floyd
A bandpass reflection-mode N-path filter (RMNF) with 2-GHz bandwidth and 10 to 40 GHz center-frequency tuning is presented. The design includes a broadband hybrid coupler, N-path reflectors, comprising four-phase passive mixers terminated with third-order in-phase and quadrature-phase active baseband loads, and a broadband clock-generation network. The reflectors realize an in-band open circuit and an out-of-band matched termination, providing a bandpass response in reflection mode. The filter is fabricated in the GlobalFoundries 45-nm RFSOI process. Across the 10 to 40 GHz tuning range, the bandpass filter has 18 dB/octave roll-off, 3.6–6.3 dB insertion loss, 40–20 dB out-of-band rejection, 6–12 dB noise figure, +22–+12 dBm out-of-band input-referred third-order intercept point, and 130–332 mW of power consumption.
{"title":"A 10 to 40 GHz Reflection-Mode N-Path Filter","authors":"Cody J. Ellington;Sandeep Hari;Brian A. Floyd","doi":"10.1109/LSSC.2025.3575536","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3575536","url":null,"abstract":"A bandpass reflection-mode N-path filter (RMNF) with 2-GHz bandwidth and 10 to 40 GHz center-frequency tuning is presented. The design includes a broadband hybrid coupler, N-path reflectors, comprising four-phase passive mixers terminated with third-order in-phase and quadrature-phase active baseband loads, and a broadband clock-generation network. The reflectors realize an in-band open circuit and an out-of-band matched termination, providing a bandpass response in reflection mode. The filter is fabricated in the GlobalFoundries 45-nm RFSOI process. Across the 10 to 40 GHz tuning range, the bandpass filter has 18 dB/octave roll-off, 3.6–6.3 dB insertion loss, 40–20 dB out-of-band rejection, 6–12 dB noise figure, +22–+12 dBm out-of-band input-referred third-order intercept point, and 130–332 mW of power consumption.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"169-172"},"PeriodicalIF":2.2,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a D-Band fundamental-sampling phase-locked loop (FS-PLL) featuring a complementary power-gating injection locking frequency-multiplier-based phase detector (CPG-ILFM PD). To reduce the level of the reference spur, the proposed CPG-ILFM PD employs two replica voltage-controlled oscillators (RVCOs) that are alternatively switched to detect the phase error of the main VCO. This approach mitigates the binary frequency shift keying (BFSK)-like modulation typically observed in conventional ILFM PDs. Additionally, the loop bandwidth of the PLL was extended, effectively suppressing the poor out-of-band phase noise (PN) of the D-Band main VCO and enhancing jitter performance. Fabricated in a 40-nm CMOS process, the proposed D-Band PLL achieved a reference spur of −51 dBc and an RMS jitter of 65.6 fs while consuming 59.5 mW of power. This results in a jitter FoM of −245.9 dB at 119.5 GHz.
{"title":"A Low-Reference-Spur and Low-Jitter D-Band PLL With Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector","authors":"Jaeho Kim;Jooeun Bang;Seohee Jung;Myeongho Han;Jaehyouk Choi","doi":"10.1109/LSSC.2025.3564893","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3564893","url":null,"abstract":"This letter presents a D-Band fundamental-sampling phase-locked loop (FS-PLL) featuring a complementary power-gating injection locking frequency-multiplier-based phase detector (CPG-ILFM PD). To reduce the level of the reference spur, the proposed CPG-ILFM PD employs two replica voltage-controlled oscillators (RVCOs) that are alternatively switched to detect the phase error of the main VCO. This approach mitigates the binary frequency shift keying (BFSK)-like modulation typically observed in conventional ILFM PDs. Additionally, the loop bandwidth of the PLL was extended, effectively suppressing the poor out-of-band phase noise (PN) of the D-Band main VCO and enhancing jitter performance. Fabricated in a 40-nm CMOS process, the proposed D-Band PLL achieved a reference spur of −51 dBc and an RMS jitter of 65.6 fs while consuming 59.5 mW of power. This results in a jitter FoM of −245.9 dB at 119.5 GHz.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"129-132"},"PeriodicalIF":2.2,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-25DOI: 10.1109/LSSC.2025.3564312
Shiwei Zhang;Wei Deng;Haikun Jia;Hongzhuo Liu;Junlong Gong;Qiuyu Peng;Baoyong Chi
To achieve robust ultra-low phase noise (PN) and a high figure of merit (FoM), this letter proposes a series-parallel-resonance oscillator topology based on the following ideas: 1) a low-impedance resonator that supports high power consumption and effective PN suppression within a compact layout and 2) impedance and gain boosting for PN-power tradeoff, sharper transition, and active noise reduction. Prototyped in 65-nm CMOS technology, the proposed X-band oscillator demonstrates a PN of −131.4 dBc/Hz at 1-MHz offset, a FoM of 191.5 dBc/Hz, and a FoMA (i.e., FoM with area) of 198.5 dBc/Hz at 10 GHz with quadrature output.
{"title":"A Series-Parallel-Resonance Oscillator With a 191.5 dBc/Hz FoM","authors":"Shiwei Zhang;Wei Deng;Haikun Jia;Hongzhuo Liu;Junlong Gong;Qiuyu Peng;Baoyong Chi","doi":"10.1109/LSSC.2025.3564312","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3564312","url":null,"abstract":"To achieve robust ultra-low phase noise (PN) and a high figure of merit (FoM), this letter proposes a series-parallel-resonance oscillator topology based on the following ideas: 1) a low-impedance resonator that supports high power consumption and effective PN suppression within a compact layout and 2) impedance and gain boosting for PN-power tradeoff, sharper transition, and active noise reduction. Prototyped in 65-nm CMOS technology, the proposed X-band oscillator demonstrates a PN of −131.4 dBc/Hz at 1-MHz offset, a FoM of 191.5 dBc/Hz, and a FoMA (i.e., FoM with area) of 198.5 dBc/Hz at 10 GHz with quadrature output.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"141-144"},"PeriodicalIF":2.2,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144090731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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