Pub Date : 2024-03-09DOI: 10.1109/LSSC.2024.3398779
Kateryna Smirnova;Mark van der Heijden;Domine Leenaerts;Ahmet Çağrı Ulusoy
In this letter, a novel W-band switchless bidirectional active phase shifter with 6-bit resolution is proposed. The circuit is implemented in the SiGe:C BiCMOS technology using a Gilbert-cell core configured in a way to combine the reciprocity of passive phase shifters with the compactness of active topologies. The circuit exhibits a maximum average gain of –7.4 and –8.2 dB in two directions while maintaining the RMS amplitude and phase error lower than 0.84 dB and 3.4° within 85– 100 GHz, respectively. The phase shifter uses 0.04 mm2 of the IC area and the DC power of 38 mW in each direction from a 2.4-V supply voltage, excluding the phase control circuitry.
本文提出了一种分辨率为 6 位的新型 W 波段无开关双向有源移相器。该电路采用 SiGe:C BiCMOS 技术实现，使用 Gilbert-cell 内核，其配置方式结合了无源移相器的互易性和有源拓扑结构的紧凑性。该电路在两个方向上的最大平均增益分别为 -7.4 和 -8.2 dB，同时在 85-100 GHz 范围内保持有效值振幅和相位误差分别低于 0.84 dB 和 3.4°。该移相器的集成电路面积为 0.04 mm2，在 2.4 V 电源电压下，每个方向的直流功率为 38 mW（不包括相位控制电路）。
{"title":"Bidirectional 6-Bit Active Phase Shifter in W-Band","authors":"Kateryna Smirnova;Mark van der Heijden;Domine Leenaerts;Ahmet Çağrı Ulusoy","doi":"10.1109/LSSC.2024.3398779","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3398779","url":null,"abstract":"In this letter, a novel W-band switchless bidirectional active phase shifter with 6-bit resolution is proposed. The circuit is implemented in the SiGe:C BiCMOS technology using a Gilbert-cell core configured in a way to combine the reciprocity of passive phase shifters with the compactness of active topologies. The circuit exhibits a maximum average gain of –7.4 and –8.2 dB in two directions while maintaining the RMS amplitude and phase error lower than 0.84 dB and 3.4° within 85– 100 GHz, respectively. The phase shifter uses 0.04 mm2 of the IC area and the DC power of 38 mW in each direction from a 2.4-V supply voltage, excluding the phase control circuitry.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141187374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-08DOI: 10.1109/LSSC.2024.3375110
Gopikrishnan R. Nair;Pragnya S. Nalla;Gokul Krishnan;Anupreetham;Jonghyun Oh;Ahmed Hassan;Injune Yeo;Kishore Kasichainula;Mingoo Seok;Jae-Sun Seo;Yu Cao
Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this design, we adopt a 4-bit autoencoder algorithm and implement it on an AI computing layer with in-memory computing (IMC) to enable real-time compression of DVS data. To support 3-D integration, this architecture is optimized to handle the unique constraints, including footprint to match the size of the sensor array, low latency to manage the continuous data stream, and low-power consumption to avoid thermal issues. Our prototype chip in 65-nm CMOS demonstrates the new concept of 3-D in-sensor computing, achieving < 6 mW power consumption at 1–10 MHz operating frequency, and $10times $ compression ratio on $256times 256$ DVS pixels.
{"title":"3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design","authors":"Gopikrishnan R. Nair;Pragnya S. Nalla;Gokul Krishnan;Anupreetham;Jonghyun Oh;Ahmed Hassan;Injune Yeo;Kishore Kasichainula;Mingoo Seok;Jae-Sun Seo;Yu Cao","doi":"10.1109/LSSC.2024.3375110","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3375110","url":null,"abstract":"Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this design, we adopt a 4-bit autoencoder algorithm and implement it on an AI computing layer with in-memory computing (IMC) to enable real-time compression of DVS data. To support 3-D integration, this architecture is optimized to handle the unique constraints, including footprint to match the size of the sensor array, low latency to manage the continuous data stream, and low-power consumption to avoid thermal issues. Our prototype chip in 65-nm CMOS demonstrates the new concept of 3-D in-sensor computing, achieving < 6 mW power consumption at 1–10 MHz operating frequency, and\u0000<inline-formula> <tex-math>$10times $ </tex-math></inline-formula>\u0000 compression ratio on \u0000<inline-formula> <tex-math>$256times 256$ </tex-math></inline-formula>\u0000 DVS pixels.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140544255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present an ultralow-power high dynamic range (DR) image sensor dedicated to autonomous vision systems, produced in a back illuminated 65 nm/40 nm stacked process and based on a time-to-digital pixel with in-pixel A/D conversion and data memory. Key to the low-power consumption is a new in-pixel comparator without dc current consumption. The 120-dB intrascene DR of the sensor, encoded on 10 bits, makes use of a logarithmic data representation. Thanks to the high intrascene DR, no adaptation to the local illumination is necessary. The sensor has a sensitivity of 6.4 V/lux/s, an FPN of 0.6%, and a temporal noise of 11 e−, with a pixel pitch of $6.3 , mu text{m}$ and a fill factor of 86%.
我们介绍了一种专用于自主视觉系统的超低功耗高动态范围（DR）图像传感器，该传感器采用背照式 65 纳米/40 纳米叠层工艺制造，基于具有像素内 A/D 转换和数据存储器的时间数字像素。低功耗的关键在于一个无直流电流消耗的新型像素内比较器。传感器的级内 DR 为 120 分贝，以 10 位编码，采用对数数据表示。由于级内 DR 高，因此无需适应局部光照。该传感器的灵敏度为 6.4 V/lux/s，FPN 为 0.6%，时间噪声为 11 e-，像素间距为 6.3 mu text{m}$，填充因子为 86%。
{"title":"A 90 µW at 1 fps and 1.33 mW at 30 fps 120-dB Intrascene Dynamic Range 640 × 480 Stacked Image Sensor for Autonomous Vision Systems","authors":"Pierre-François Rüedi;Riccardo Quaglia;Hans-Rudolf Graf","doi":"10.1109/LSSC.2024.3370797","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3370797","url":null,"abstract":"We present an ultralow-power high dynamic range (DR) image sensor dedicated to autonomous vision systems, produced in a back illuminated 65 nm/40 nm stacked process and based on a time-to-digital pixel with in-pixel A/D conversion and data memory. Key to the low-power consumption is a new in-pixel comparator without dc current consumption. The 120-dB intrascene DR of the sensor, encoded on 10 bits, makes use of a logarithmic data representation. Thanks to the high intrascene DR, no adaptation to the local illumination is necessary. The sensor has a sensitivity of 6.4 V/lux/s, an FPN of 0.6%, and a temporal noise of 11 e−, with a pixel pitch of \u0000<inline-formula> <tex-math>$6.3 , mu text{m}$ </tex-math></inline-formula>\u0000 and a fill factor of 86%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140161094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-23DOI: 10.1109/LSSC.2024.3369605
Gichan Yun;Kyeongwon Jeong;Haidam Choi;Seunghyun Nam;Chaerin Oh;Hyunjoo Jenny Lee;Sohmyung Ha;Minkyu Je
In this letter, we present an ultrasound (US) imaging system with a low-noise US receiver (RX) and an element-level US transmitter (TX) for a capacitive micromachined ultrasonic transducer (CMUT). The proposed US RX isolates the input parasitic capacitance $(C_{P})$ from the front-end transimpedance stage by using a bandwidth-enhanced current conveyor. By reducing the effects of the $C_{P}$ , the noise and power efficiency are improved compared to the conventional current readout circuits. Also, a US TX having a class-D output stage is implemented to excite the CMUT with 30-V unipolar pulses. Fabricated in a 180-nm BCD process, the proposed US RX achieves input-referred noise of 2.0 pA/ $sqrt {textit {Hz}}$ at 7.5 MHz and a bandwidth of 18 MHz with 25-pF CMUT capacitance while consuming 3.62 mW.
在这封信中，我们介绍了一种超声波（US）成像系统，该系统带有低噪声 US 接收器（RX）和元件级 US 发射器（TX），适用于电容式微机械超声波换能器（CMUT）。拟议的 US RX 通过使用带宽增强电流传送器，将输入寄生电容 $(C_{P})$ 与前端跨阻抗级隔离开来。与传统的电流读出电路相比，通过减少 $C_{P}$ 的影响，噪声和能效都得到了改善。此外，还采用了具有 D 类输出级的 US TX，以 30 V 单极性脉冲激励 CMUT。所提出的 US RX 采用 180 纳米 BCD 工艺制造，在 7.5 MHz 频率和 18 MHz 带宽条件下，输入参考噪声为 2.0 pA/ $sqrt {textit {Hz}}$，CMUT 电容为 25 pF，功耗为 3.62 mW。
{"title":"An Ultrasound Receiver With Bandwidth-Enhanced Current Conveyor and Element-Level Ultrasound Transmitter for Ultrasound Imaging Systems","authors":"Gichan Yun;Kyeongwon Jeong;Haidam Choi;Seunghyun Nam;Chaerin Oh;Hyunjoo Jenny Lee;Sohmyung Ha;Minkyu Je","doi":"10.1109/LSSC.2024.3369605","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3369605","url":null,"abstract":"In this letter, we present an ultrasound (US) imaging system with a low-noise US receiver (RX) and an element-level US transmitter (TX) for a capacitive micromachined ultrasonic transducer (CMUT). The proposed US RX isolates the input parasitic capacitance \u0000<inline-formula> <tex-math>$(C_{P})$ </tex-math></inline-formula>\u0000 from the front-end transimpedance stage by using a bandwidth-enhanced current conveyor. By reducing the effects of the \u0000<inline-formula> <tex-math>$C_{P}$ </tex-math></inline-formula>\u0000, the noise and power efficiency are improved compared to the conventional current readout circuits. Also, a US TX having a class-D output stage is implemented to excite the CMUT with 30-V unipolar pulses. Fabricated in a 180-nm BCD process, the proposed US RX achieves input-referred noise of 2.0 pA/\u0000<inline-formula> <tex-math>$sqrt {textit {Hz}}$ </tex-math></inline-formula>\u0000 at 7.5 MHz and a bandwidth of 18 MHz with 25-pF CMUT capacitance while consuming 3.62 mW.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140104292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-23DOI: 10.1109/LSSC.2024.3369058
Amitesh Sridharan;Jyotishman Saikia;Anupreetham;Fan Zhang;Jae-Sun Seo;Deliang Fan
We present a fully digital multiply and accumulate (MAC) in-memory computing (IMC) macro demonstrating one of the fastest flexible precision integer-based MACs to date. The design boasts a new bit-parallel architecture enabled by a 10T bit-cell capable of four AND operations and a decomposed precision data flow that decreases the number of shift–accumulate operations, bringing down the overall adder hardware cost by $1.57times $ while maintaining 100% utilization for all supported precision. It also employs a carry save adder tree that saves 21% of adder hardware. The 28-nm prototype chip achieves a speed-up of $2.6times $ , $10.8times $ , $2.42times $ , and $3.22times $ over prior SoTA in 1bW:1bI, 1bW:4bI, 4bW:4bI, and 8bW:8bI MACs, respectively.
我们展示了一个全数字乘法累加（MAC）内存计算（IMC）宏，它是迄今为止速度最快的灵活精度整数 MAC 之一。该设计采用了全新的位并行架构，该架构由一个能够进行四次 AND 运算的 10T 位元组和一个分解精度数据流实现，该数据流减少了移位累加运算的次数，从而将总体加法器硬件成本降低了 1.57 美元/次，同时保持了所有支持精度的 100% 利用率。它还采用了节省进位的加法器树，节省了 21% 的加法器硬件。在1bW:1bI、1bW:4bI、4bW:4bI和8bW:8bI MAC中，28纳米原型芯片的速度比先前的SoTA分别提高了2.6美元、10.8美元、2.42美元和3.22美元。
{"title":"PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs","authors":"Amitesh Sridharan;Jyotishman Saikia;Anupreetham;Fan Zhang;Jae-Sun Seo;Deliang Fan","doi":"10.1109/LSSC.2024.3369058","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3369058","url":null,"abstract":"We present a fully digital multiply and accumulate (MAC) in-memory computing (IMC) macro demonstrating one of the fastest flexible precision integer-based MACs to date. The design boasts a new bit-parallel architecture enabled by a 10T bit-cell capable of four AND operations and a decomposed precision data flow that decreases the number of shift–accumulate operations, bringing down the overall adder hardware cost by \u0000<inline-formula> <tex-math>$1.57times $ </tex-math></inline-formula>\u0000 while maintaining 100% utilization for all supported precision. It also employs a carry save adder tree that saves 21% of adder hardware. The 28-nm prototype chip achieves a speed-up of \u0000<inline-formula> <tex-math>$2.6times $ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$10.8times $ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$2.42times $ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$3.22times $ </tex-math></inline-formula>\u0000 over prior SoTA in 1bW:1bI, 1bW:4bI, 4bW:4bI, and 8bW:8bI MACs, respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140123545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-22DOI: 10.1109/LSSC.2024.3368634
Jian-Hua Li;Xiaoping Liao
In this letter, a sustainable status monitoring of MOSFETs in a fully integrated two stage RF amplifier by thermal voltage sensing of on-chip thermopile is implemented in 0.18- $mu text{m}$ CMOS technology. The designed micro-thermopile consists of many thermocouples electrically connected in series by Al and P-type polysilicon, which are carefully arranged around the metal-oxide-semiconductor field-effect transistors (MOSFETs). A noteworthy attribute of variations-aware thermopiles, which exhibits an exceptionally close physical proximity to the MOSFETs, is their nonintrusive nature, indicating that they lack electrical connectivity to transistors. During normal operation of the RF amplifier, the dynamic range of its input power spans from −20 to 0 dBm. Experimental measurements on the MOSFETs employed in the first and second power amplification stages are observed to lie within the range of 0.226 to 0.264 and 0.275 to 0.3 mV at 5.4 GHz, respectively. This result demonstrates the capability of integrated on-chip micro-thermopiles to enable continuous monitoring of the operational status of MOSFETs. In comparison to conventional status monitoring approaches, the advantage of this integrated design lies in its elimination of the requirement for supplementary sensors or devices, thereby presenting a significant economic benefit as a low-cost, sustainable monitoring solution in a fully integrated CMOS RF amplifier.
{"title":"Sustainable Status Monitoring of MOSFETs in a Fully Integrated RF Amplifier by Thermal Voltage Sensing of On-Chip Thermopile","authors":"Jian-Hua Li;Xiaoping Liao","doi":"10.1109/LSSC.2024.3368634","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3368634","url":null,"abstract":"In this letter, a sustainable status monitoring of MOSFETs in a fully integrated two stage RF amplifier by thermal voltage sensing of on-chip thermopile is implemented in 0.18-\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 CMOS technology. The designed micro-thermopile consists of many thermocouples electrically connected in series by Al and P-type polysilicon, which are carefully arranged around the metal-oxide-semiconductor field-effect transistors (MOSFETs). A noteworthy attribute of variations-aware thermopiles, which exhibits an exceptionally close physical proximity to the MOSFETs, is their nonintrusive nature, indicating that they lack electrical connectivity to transistors. During normal operation of the RF amplifier, the dynamic range of its input power spans from −20 to 0 dBm. Experimental measurements on the MOSFETs employed in the first and second power amplification stages are observed to lie within the range of 0.226 to 0.264 and 0.275 to 0.3 mV at 5.4 GHz, respectively. This result demonstrates the capability of integrated on-chip micro-thermopiles to enable continuous monitoring of the operational status of MOSFETs. In comparison to conventional status monitoring approaches, the advantage of this integrated design lies in its elimination of the requirement for supplementary sensors or devices, thereby presenting a significant economic benefit as a low-cost, sustainable monitoring solution in a fully integrated CMOS RF amplifier.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140063492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Content addressable memories (CAMs) are widely used in many applications in general purpose computer microarchitecture, networking and domain-specific hardware accelerators. In addition to storing and reading data, CAMs enable simultaneous compare of query datawords with the entire memory content. Similar to SRAM and DRAM, CAMs are prone to errors and faults. While error correcting codes (ECCs) are widely used in DRAM and SRAM, they are not directly applicable in CAM: if a dataword that is supposed to match a query altered due to an error, it will falsely mismatch even if it is ECC-encoded. We propose OCCAM, an error oblivious CAM, which combines ECC and approximate search (matching) to allow tolerating a large and dynamically configurable number of errors. We manufactured the OCCAM silicon prototype using 65-nm commercial process and verified its error tolerance capabilities through silicon measurements. OCCAM tolerates 11% error rate (7 bit errors in each 64-bit memory row) with 100% sensitivity and specificity.
{"title":"OCCAM: An Error Oblivious CAM","authors":"Yuval Harary;Paz Snapir;Eyal Reshef;Esteban Garzón;Leonid Yavits","doi":"10.1109/LSSC.2024.3362891","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3362891","url":null,"abstract":"Content addressable memories (CAMs) are widely used in many applications in general purpose computer microarchitecture, networking and domain-specific hardware accelerators. In addition to storing and reading data, CAMs enable simultaneous compare of query datawords with the entire memory content. Similar to SRAM and DRAM, CAMs are prone to errors and faults. While error correcting codes (ECCs) are widely used in DRAM and SRAM, they are not directly applicable in CAM: if a dataword that is supposed to match a query altered due to an error, it will falsely mismatch even if it is ECC-encoded. We propose OCCAM, an error oblivious CAM, which combines ECC and approximate search (matching) to allow tolerating a large and dynamically configurable number of errors. We manufactured the OCCAM silicon prototype using 65-nm commercial process and verified its error tolerance capabilities through silicon measurements. OCCAM tolerates 11% error rate (7 bit errors in each 64-bit memory row) with 100% sensitivity and specificity.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10423391","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139941573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An innovative, highly reconfigurable charge-domain analog finite-impulse-response (AFIR) filter for high-channel selectivity receivers is presented. This filter demonstrates excellent reconfigurability to different bandwidths and desired stopband rejection and realizes the coefficients in the charge-domain with time-varying pulse widths controlling the on-time of the transconductor. The charge-domain finite impulse response (FIR) principle is derived step by step in this letter. The proposed filter, manufactured in 28-nm CMOS process, occupies a compact area of 0.05 mm 2, and its bandwidth can be reconfigured from 0.37 to 4.6 MHz. The filter can achieve −70-dB stopband rejection with a sharp transition ( $-f_{-60 {mathrm {dB}}}^{/f}-3~ {mathrm {dB}},,=$ 4.5) and low-power consumption of 0.356 mW.
{"title":"A Low-Power Highly Reconfigurable Analog FIR Filter With 11-Bit Charge-Domain DAC for Narrowband Receivers","authors":"Chien-Wei Tseng;Zhen Feng;Zichen Fan;Hyochan An;Yunfan Wang;Hun-Seok Kim;David Blaauw","doi":"10.1109/LSSC.2024.3361380","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3361380","url":null,"abstract":"An innovative, highly reconfigurable charge-domain analog finite-impulse-response (AFIR) filter for high-channel selectivity receivers is presented. This filter demonstrates excellent reconfigurability to different bandwidths and desired stopband rejection and realizes the coefficients in the charge-domain with time-varying pulse widths controlling the on-time of the transconductor. The charge-domain finite impulse response (FIR) principle is derived step by step in this letter. The proposed filter, manufactured in 28-nm CMOS process, occupies a compact area of 0.05 mm 2, and its bandwidth can be reconfigured from 0.37 to 4.6 MHz. The filter can achieve −70-dB stopband rejection with a sharp transition (\u0000<inline-formula> <tex-math>$-f_{-60 {mathrm {dB}}}^{/f}-3~ {mathrm {dB}},,=$ </tex-math></inline-formula>\u0000 4.5) and low-power consumption of 0.356 mW.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139916583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-01DOI: 10.1109/LSSC.2024.3361011
Injune Yeo;Wangxin He;Yuan-Chun Luo;Shimeng Yu;Jae-Sun Seo
Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the challenges of resistive NVM CIMs. The proposed CIM macro involves encoding ternary input activations and weights into voltages, and enabling parasitic insensitive charge readout. A power-of-two nonlinear SAR ADC is introduced, designed for energy-efficiency and hardware-friendliness. This ADC employs adaptive conversion skipping based on input voltage, resulting in fine precision for concentrated input levels and coarse conversion for sparse input levels. The proposed FCA-based CIM macro in 180-nm CMOS demonstrates $16times 8$ analog MAC operation with an energy efficiency of 1.75 TOPS/W and classification accuracy of 90.2% is obtained for the CIFAR-10 dataset.
{"title":"A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array","authors":"Injune Yeo;Wangxin He;Yuan-Chun Luo;Shimeng Yu;Jae-Sun Seo","doi":"10.1109/LSSC.2024.3361011","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3361011","url":null,"abstract":"Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the challenges of resistive NVM CIMs. The proposed CIM macro involves encoding ternary input activations and weights into voltages, and enabling parasitic insensitive charge readout. A power-of-two nonlinear SAR ADC is introduced, designed for energy-efficiency and hardware-friendliness. This ADC employs adaptive conversion skipping based on input voltage, resulting in fine precision for concentrated input levels and coarse conversion for sparse input levels. The proposed FCA-based CIM macro in 180-nm CMOS demonstrates \u0000<inline-formula> <tex-math>$16times 8$ </tex-math></inline-formula>\u0000 analog MAC operation with an energy efficiency of 1.75 TOPS/W and classification accuracy of 90.2% is obtained for the CIFAR-10 dataset.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139916647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-30DOI: 10.1109/LSSC.2024.3360243
Fei Wang;Siyu Huang;Zhigang Wu;Cheng Ma;Xinyang Wang;Zeyu Cai
An indirect time-of-flight (iToF) CMOS image sensor (CIS) has been designed with 65-nm pixel-level stacked backside-illuminated (BSI) CIS technology. By using an adaptable tap for ambient light detection, the sensor achieves a good balance between the depth noise and the detection range. The residual error caused by the mismatch among different taps is further reduced by a dedicated tap-rotating technique. It also features a multimachine interference suppression (MMIS) technique to further improve imaging quality. The sensor achieves a 0.29% depth noise over a 7-m detection range and 68-dB dynamic range with tap-rotating technique, while consuming only 80 mW of power.
{"title":"A Low-Depth-Noise Indirect Time-of-Flight CMOS Image Sensor With Tap-Rotating Technique for Extended Range and Enhanced Imaging Quality","authors":"Fei Wang;Siyu Huang;Zhigang Wu;Cheng Ma;Xinyang Wang;Zeyu Cai","doi":"10.1109/LSSC.2024.3360243","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3360243","url":null,"abstract":"An indirect time-of-flight (iToF) CMOS image sensor (CIS) has been designed with 65-nm pixel-level stacked backside-illuminated (BSI) CIS technology. By using an adaptable tap for ambient light detection, the sensor achieves a good balance between the depth noise and the detection range. The residual error caused by the mismatch among different taps is further reduced by a dedicated tap-rotating technique. It also features a multimachine interference suppression (MMIS) technique to further improve imaging quality. The sensor achieves a 0.29% depth noise over a 7-m detection range and 68-dB dynamic range with tap-rotating technique, while consuming only 80 mW of power.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139993659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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