Pub Date : 2024-03-09DOI: 10.1109/LSSC.2024.3398779
Kateryna Smirnova;Mark van der Heijden;Domine Leenaerts;Ahmet Çağrı Ulusoy
In this letter, a novel W-band switchless bidirectional active phase shifter with 6-bit resolution is proposed. The circuit is implemented in the SiGe:C BiCMOS technology using a Gilbert-cell core configured in a way to combine the reciprocity of passive phase shifters with the compactness of active topologies. The circuit exhibits a maximum average gain of –7.4 and –8.2 dB in two directions while maintaining the RMS amplitude and phase error lower than 0.84 dB and 3.4° within 85– 100 GHz, respectively. The phase shifter uses 0.04 mm2 of the IC area and the DC power of 38 mW in each direction from a 2.4-V supply voltage, excluding the phase control circuitry.
本文提出了一种分辨率为 6 位的新型 W 波段无开关双向有源移相器。该电路采用 SiGe:C BiCMOS 技术实现,使用 Gilbert-cell 内核,其配置方式结合了无源移相器的互易性和有源拓扑结构的紧凑性。该电路在两个方向上的最大平均增益分别为 -7.4 和 -8.2 dB,同时在 85-100 GHz 范围内保持有效值振幅和相位误差分别低于 0.84 dB 和 3.4°。该移相器的集成电路面积为 0.04 mm2,在 2.4 V 电源电压下,每个方向的直流功率为 38 mW(不包括相位控制电路)。
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Pub Date : 2024-03-08DOI: 10.1109/LSSC.2024.3375110
Gopikrishnan R. Nair;Pragnya S. Nalla;Gokul Krishnan;Anupreetham;Jonghyun Oh;Ahmed Hassan;Injune Yeo;Kishore Kasichainula;Mingoo Seok;Jae-Sun Seo;Yu Cao
Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this design, we adopt a 4-bit autoencoder algorithm and implement it on an AI computing layer with in-memory computing (IMC) to enable real-time compression of DVS data. To support 3-D integration, this architecture is optimized to handle the unique constraints, including footprint to match the size of the sensor array, low latency to manage the continuous data stream, and low-power consumption to avoid thermal issues. Our prototype chip in 65-nm CMOS demonstrates the new concept of 3-D in-sensor computing, achieving < 6 mW power consumption at 1–10 MHz operating frequency, and $10times $