首页 > 最新文献

IEEE Solid-State Circuits Letters最新文献

英文 中文
A 7-b 76-mW 40-GS/s Hybrid Voltage/Time-Domain ADC With Common-Mode Input Tracking 具有共模输入跟踪功能的 7-b 76-mW 40-GS/s 混合电压/时域 ADC
IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-07-18 DOI: 10.1109/LSSC.2024.3430851
Amy Whitcombe;Somnath Kundu;Hariprasad Chandrakumar;Abhishek Agrawal;Thomas Brown;Steven Callender;Brent Carlton;Stefano Pellerano
High-speed links require fast, moderate resolution analog-to-digital converters (ADCs) with low power to maximize efficiency. Hybrid voltage and time (V+T) ADCs can combine the speed benefits of time-domain conversion with the reliability of conventional voltage-domain ADCs. This letter demonstrates 1) how the V+T architecture can simplify time interleaving implementation and 2) highlights two methods for improving V+T sub-ADC robustness: a) a voltage-to-time converter (VTC) with common-mode input voltage tracking and b) a merged time-to-voltage and flash time-to-digital converter. This is demonstrated in a 0.103-mm2 22-nm CMOS prototype that consumes 76 mW and gives 32.3-dB SNDR with a Nyquist input at 40 GS/s, for 57-fJ/step FoMw.
高速链路需要快速、中等分辨率、低功耗的模数转换器 (ADC),以最大限度地提高效率。混合电压和时间(V+T)模数转换器可将时域转换的速度优势与传统电压域模数转换器的可靠性结合起来。这封信展示了:1)V+T 架构如何简化时间交错的实现;2)强调了提高 V+T 子 ADC 稳健性的两种方法:a)具有共模输入电压跟踪功能的电压-时间转换器 (VTC);b)合并的时间-电压转换器和闪存时间-数字转换器。在 0.103 平方毫米的 22 纳米 CMOS 原型中进行了演示,该原型功耗为 76 毫瓦,在 40 GS/s 的 Nyquist 输入条件下可提供 32.3 分贝的 SNDR,FoMw 为 57 fJ/step。
{"title":"A 7-b 76-mW 40-GS/s Hybrid Voltage/Time-Domain ADC With Common-Mode Input Tracking","authors":"Amy Whitcombe;Somnath Kundu;Hariprasad Chandrakumar;Abhishek Agrawal;Thomas Brown;Steven Callender;Brent Carlton;Stefano Pellerano","doi":"10.1109/LSSC.2024.3430851","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3430851","url":null,"abstract":"High-speed links require fast, moderate resolution analog-to-digital converters (ADCs) with low power to maximize efficiency. Hybrid voltage and time (V+T) ADCs can combine the speed benefits of time-domain conversion with the reliability of conventional voltage-domain ADCs. This letter demonstrates 1) how the V+T architecture can simplify time interleaving implementation and 2) highlights two methods for improving V+T sub-ADC robustness: a) a voltage-to-time converter (VTC) with common-mode input voltage tracking and b) a merged time-to-voltage and flash time-to-digital converter. This is demonstrated in a 0.103-mm2 22-nm CMOS prototype that consumes 76 mW and gives 32.3-dB SNDR with a Nyquist input at 40 GS/s, for 57-fJ/step FoMw.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"211-214"},"PeriodicalIF":2.2,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141966121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2-Way W-Band Power Amplifier With an Isolated Combining Output Network for Power Back-Off Efficiency Enhancement in 16-nm FinFet Technology 一款采用 16 纳米 FinFet 技术的双路 W 波段功率放大器,带有隔离式组合输出网络,可提高功率衰减效率
IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-07-10 DOI: 10.1109/LSSC.2024.3426336
Yahia Ibrahim;Ali Niknejad
This letter introduces a W-Band sequential power amplifier (PA) (Lehmann and Knoechel, 2008) with a novel output network designed to minimize passive and combiner losses, while reducing the overall footprint compared to conventional sequential and Doherty PAs (Doherty, 1936). An isolated output combiner sums two PAs operating in two different modes: 1) the main amplifier operates in class AB and 2) the auxiliary amplifier operates in class C. The measured PA achieves a saturated output power $(mathbf {P_{mathrm { sat}}})$ of 13 dBm and a gain of 12.5 dB with 3-dB bandwidth (BW) from 79.5 to 94.5 GHz. Additionally, it demonstrates a peak power-added efficiency (PAE) of 19.4% and a 14.6% PAE at 6-dB power back-off (PBO) at 87.5 GHz. Furthermore, the PA achieves a data rate of 12 Gb/s for a 16QAM signal with an average output power of 5 dBm, an average PAE of 10%, and an EVM (RMS) of -20 dB. The PA was fabricated in 16-nm FinFet technology with core area of 0.15 mm2. To the authors’ knowledge, this PA has the highest PAE at 6-dB PBO for CMOS PAs operating in the W-Band.
这封信介绍了一种 W 波段序列功率放大器(PA)(Lehmann 和 Knoechel,2008 年),与传统序列功率放大器和 Doherty 功率放大器(Doherty,1936 年)相比,它具有新颖的输出网络,旨在最大限度地减少无源损耗和合路器损耗,同时减少整体占地面积。测量的功率放大器实现了 13 dBm 的饱和输出功率 $(mathbf {P_{mathrm { sat}})$ 和 12.5 dB 的增益,带宽 (BW) 为 3 dB,频率范围为 79.5 至 94.5 GHz。此外,它的峰值功率附加效率(PAE)为 19.4%,在 87.5 GHz 的 6 分贝功率衰减(PBO)条件下,PAE 为 14.6%。此外,该功率放大器在平均输出功率为 5 dBm、平均 PAE 为 10%、EVM(RMS)为 -20 dB 的情况下,16QAM 信号的数据传输速率达到 12 Gb/s。功率放大器采用 16 纳米 FinFet 技术制造,核心面积为 0.15 平方毫米。据作者所知,在工作于 W 波段的 CMOS 功率放大器中,该功率放大器在 6 分贝 PBO 时具有最高的 PAE。
{"title":"A 2-Way W-Band Power Amplifier With an Isolated Combining Output Network for Power Back-Off Efficiency Enhancement in 16-nm FinFet Technology","authors":"Yahia Ibrahim;Ali Niknejad","doi":"10.1109/LSSC.2024.3426336","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3426336","url":null,"abstract":"This letter introduces a W-Band sequential power amplifier (PA) (Lehmann and Knoechel, 2008) with a novel output network designed to minimize passive and combiner losses, while reducing the overall footprint compared to conventional sequential and Doherty PAs (Doherty, 1936). An isolated output combiner sums two PAs operating in two different modes: 1) the main amplifier operates in class AB and 2) the auxiliary amplifier operates in class C. The measured PA achieves a saturated output power \u0000<inline-formula> <tex-math>$(mathbf {P_{mathrm { sat}}})$ </tex-math></inline-formula>\u0000 of 13 dBm and a gain of 12.5 dB with 3-dB bandwidth (BW) from 79.5 to 94.5 GHz. Additionally, it demonstrates a peak power-added efficiency (PAE) of 19.4% and a 14.6% PAE at 6-dB power back-off (PBO) at 87.5 GHz. Furthermore, the PA achieves a data rate of 12 Gb/s for a 16QAM signal with an average output power of 5 dBm, an average PAE of 10%, and an EVM (RMS) of -20 dB. The PA was fabricated in 16-nm FinFet technology with core area of 0.15 mm2. To the authors’ knowledge, this PA has the highest PAE at 6-dB PBO for CMOS PAs operating in the W-Band.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"203-206"},"PeriodicalIF":2.2,"publicationDate":"2024-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141964880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Ultrawide Load-Range Fast-Transient Output Capacitor-Less Digital LDO With Adaptive Gate Modulation and Droop Detection 具有自适应栅极调制和下拉检测功能的超宽负载范围快速瞬态输出无电容数字 LDO
IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-27 DOI: 10.1109/LSSC.2024.3420117
Gunmo Koo;Jaejin Kim;Seongmin Lee;Jae Hoon Shim;Kunhee Cho
An ultrawide load-range output capacitor-less digital LDO (DLDO) with an adaptive gate modulation scheme is described. The proposed DLDO is primarily regulated by digital codes with a synchronous clock signal while the gate driving level is dynamically adjusted according to the load current level. The proposed gate modulation scheme can significantly widen the dynamic range of load current and reduce the output voltage ripple. In addition, an asynchronous droop detection circuit, coupled with adaptive gate modulation, is added to improve the voltage droop and ensure fast recovery from load transients. The proposed DLDO was fabricated in 28-nm CMOS process. The dynamic load range of 57 $143times $ (1.4– $80~mu $ A) is achieved and the output voltage ripple of under 17 mV is measured across the entire load current range. A response time of less than 10 ns and a recovery time of less than 30 ns are measured in various load transient conditions.
本文介绍了一种采用自适应栅极调制方案的超宽负载范围输出无电容数字 LDO(DLDO)。所提出的 DLDO 主要通过同步时钟信号的数字代码进行调节,同时根据负载电流水平动态调整栅极驱动电平。所提出的栅极调制方案可显著拓宽负载电流的动态范围,并降低输出电压纹波。此外,在自适应栅极调制的基础上还增加了一个异步电压下垂检测电路,以改善电压下垂并确保从负载瞬态中快速恢复。所提出的 DLDO 采用 28 纳米 CMOS 工艺制造。实现了 57 $143/times $ (1.4- $80~mu $ A) 的动态负载范围,并在整个负载电流范围内测得低于 17 mV 的输出电压纹波。在各种负载瞬态条件下测得的响应时间小于 10 ns,恢复时间小于 30 ns。
{"title":"An Ultrawide Load-Range Fast-Transient Output Capacitor-Less Digital LDO With Adaptive Gate Modulation and Droop Detection","authors":"Gunmo Koo;Jaejin Kim;Seongmin Lee;Jae Hoon Shim;Kunhee Cho","doi":"10.1109/LSSC.2024.3420117","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3420117","url":null,"abstract":"An ultrawide load-range output capacitor-less digital LDO (DLDO) with an adaptive gate modulation scheme is described. The proposed DLDO is primarily regulated by digital codes with a synchronous clock signal while the gate driving level is dynamically adjusted according to the load current level. The proposed gate modulation scheme can significantly widen the dynamic range of load current and reduce the output voltage ripple. In addition, an asynchronous droop detection circuit, coupled with adaptive gate modulation, is added to improve the voltage droop and ensure fast recovery from load transients. The proposed DLDO was fabricated in 28-nm CMOS process. The dynamic load range of 57\u0000<inline-formula> <tex-math>$143times $ </tex-math></inline-formula>\u0000 (1.4–\u0000<inline-formula> <tex-math>$80~mu $ </tex-math></inline-formula>\u0000A) is achieved and the output voltage ripple of under 17 mV is measured across the entire load current range. A response time of less than 10 ns and a recovery time of less than 30 ns are measured in various load transient conditions.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"199-202"},"PeriodicalIF":2.2,"publicationDate":"2024-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A PVT-Tolerant STR-Based TRNG in 4-nm Achieving 60 Mbp/s and Its Performance Analysis via Mathematical Modeling 在 4 纳米工艺中实现 60 Mbp/s 的基于 STR 的 PVT 容限 TRNG 及其数学建模性能分析
IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-26 DOI: 10.1109/LSSC.2024.3419722
Jieun Park;Yong Ki Lee;Karpinskyy Bohdan;Yunhyeok Choi;Jonghoon Shin;Hyo-Gyuem Rhew;Jongshin Shin
This letter presents a high-performance true random number generator (TRNG) based on self-timed ring (STR), showing robust tolerance to PVT variations. The evaluations were performed over 320 chips (64 chips per process corner of nn, ff, ss, sf, and fs) across three voltages (0.75 V, 0.75 V±10%) and three temperatures ( $- 40~^{circ }$ C, $25~^{circ }$ C, and $150~^{circ }$ C). All 320 test chips demonstrated stable random generation at 60 Mb/s over all the test combinations without a single failure. The verification utilized a TRNG BIST, ensuring a minimum of 0.5 min-entropy per bit. Moreover, a mathematical model for the proposed TRNG is developed to derive the throughput and the entropy of the random output.
这封信介绍了一种基于自定时环(STR)的高性能真随机数发生器(TRNG),显示了对 PVT 变化的强大耐受性。在三种电压(0.75 V、0.75 V±10%)和三种温度($- 40~^{circ }$ C、$25~^{circ }$ C 和 $150~^{circ }$ C)下,对 320 个芯片(nn、ff、ss、ssf 和 fs 的每个工艺角 64 个芯片)进行了评估。在所有测试组合中,所有 320 个测试芯片都以 60 Mb/s 的速度稳定生成随机数据,没有出现任何故障。验证采用了 TRNG BIST,确保了每比特最小 0.5 min-熵。此外,还为拟议的 TRNG 建立了一个数学模型,以推导随机输出的吞吐量和熵。
{"title":"A PVT-Tolerant STR-Based TRNG in 4-nm Achieving 60 Mbp/s and Its Performance Analysis via Mathematical Modeling","authors":"Jieun Park;Yong Ki Lee;Karpinskyy Bohdan;Yunhyeok Choi;Jonghoon Shin;Hyo-Gyuem Rhew;Jongshin Shin","doi":"10.1109/LSSC.2024.3419722","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3419722","url":null,"abstract":"This letter presents a high-performance true random number generator (TRNG) based on self-timed ring (STR), showing robust tolerance to PVT variations. The evaluations were performed over 320 chips (64 chips per process corner of nn, ff, ss, sf, and fs) across three voltages (0.75 V, 0.75 V±10%) and three temperatures (\u0000<inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>\u0000C, \u0000<inline-formula> <tex-math>$25~^{circ }$ </tex-math></inline-formula>\u0000C, and \u0000<inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>\u0000C). All 320 test chips demonstrated stable random generation at 60 Mb/s over all the test combinations without a single failure. The verification utilized a TRNG BIST, ensuring a minimum of 0.5 min-entropy per bit. Moreover, a mathematical model for the proposed TRNG is developed to derive the throughput and the entropy of the random output.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"255-258"},"PeriodicalIF":2.2,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142276462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 44.3 TOPS/W SRAM Compute-in-Memory With Near-CIM Analog Memory and Activation for DAC/ADC-Less Operations 具有近 CIM 模拟存储器的 44.3 TOPS/W SRAM 存贮器计算功能,可激活无 DAC/ADC 操作
IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-24 DOI: 10.1109/LSSC.2024.3418099
Peiyu Chen;Meng Wu;Wentao Zhao;Yufei Ma;Tianyu Jia;Le Ye
In this letter, we present an analog compute-in-memory (CIM) macro design which incorporates near-CIM analog memory and nonlinearity activation unit (NAU) to alleviate the DAC/ADC power bottleneck. Fully differential analog memory is designed with switched capacitor storage circuits. Activation function, e.g., rectified linear unit, is also performed in analog domain in NAU. The CIM macro is fabricated using TSMC 55-nm technology, with a peak macro-level efficiency of 44.3 TOPS/W and a system energy efficiency of 27.7 TOPS/W for analog input and output with 4-bit weight. The near-CIM analog memory and NAU solution brings 76.0% energy reduction compared with DAC/ADC solution, which contributes $1.34times $ to $2.37times $ energy efficiency improvement.
在这封信中,我们介绍了一种模拟内存计算 (CIM) 宏设计,它结合了近 CIM 模拟存储器和非线性激活单元 (NAU),以缓解 DAC/ADC 的功率瓶颈。全差分模拟存储器采用开关电容存储电路设计。激活功能(如整流线性单元)也在 NAU 的模拟域中执行。CIM 宏采用台积电 55 纳米技术制造,峰值宏级能效为 44.3 TOPS/W,模拟输入和输出的系统能效为 27.7 TOPS/W,权重为 4 位。与 DAC/ADC 解决方案相比,近 CIM 模拟存储器和 NAU 解决方案的能耗降低了 76.0%,能效提高了 1.34 美元至 2.37 美元。
{"title":"A 44.3 TOPS/W SRAM Compute-in-Memory With Near-CIM Analog Memory and Activation for DAC/ADC-Less Operations","authors":"Peiyu Chen;Meng Wu;Wentao Zhao;Yufei Ma;Tianyu Jia;Le Ye","doi":"10.1109/LSSC.2024.3418099","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3418099","url":null,"abstract":"In this letter, we present an analog compute-in-memory (CIM) macro design which incorporates near-CIM analog memory and nonlinearity activation unit (NAU) to alleviate the DAC/ADC power bottleneck. Fully differential analog memory is designed with switched capacitor storage circuits. Activation function, e.g., rectified linear unit, is also performed in analog domain in NAU. The CIM macro is fabricated using TSMC 55-nm technology, with a peak macro-level efficiency of 44.3 TOPS/W and a system energy efficiency of 27.7 TOPS/W for analog input and output with 4-bit weight. The near-CIM analog memory and NAU solution brings 76.0% energy reduction compared with DAC/ADC solution, which contributes \u0000<inline-formula> <tex-math>$1.34times $ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$2.37times $ </tex-math></inline-formula>\u0000 energy efficiency improvement.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"299-302"},"PeriodicalIF":2.2,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142430727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 620-pF-Compensated Dual-Mode Capacitance Readout IC for Subdisplay Panel Applications 用于副显示面板应用的 620-pF 补偿双模电容读出集成电路
IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-24 DOI: 10.1109/LSSC.2024.3418523
Hamin Lee;Juwon Ham;Junmin Lee;Wooseok Jang;Seunghoon Ko
This letter presents a touch readout integrated circuit (IC) integrating both mutual- and self-capacitance sensing capabilities. The proposed IC aims to compensate for self-capacitance up to 620 pF by employing a combination of current-mode and capacitive-mode compensation techniques. A noise-monitoring scheme, based on the orthogonality of multicapacitance driving sequences, enhances readout performance by selectively detecting external noises during mutual-capacitance sensing operation. The IC achieved the measured signal-to-noise ratio (SNR) of 47.3, 30.6, and 36.1 dB in mutual-capacitance sensing and self-capacitance sensing of T/RX electrodes, respectively. By applying the noise-monitoring scheme, a 7-times higher noise power compared to the absence of external noise were successfully detected.
这封信介绍了一种集成了互电容和自电容传感功能的触摸读出集成电路(IC)。该集成电路采用电流模式和电容模式补偿技术,旨在补偿高达 620 pF 的自电容。噪声监测方案以多电容驱动序列的正交性为基础,通过在互电容感应操作期间选择性地检测外部噪声来提高读出性能。在 T/RX 电极的互电容传感和自电容传感中,集成电路测得的信噪比(SNR)分别为 47.3、30.6 和 36.1 dB。通过应用噪声监测方案,成功检测到的噪声功率是没有外部噪声时的 7 倍。
{"title":"A 620-pF-Compensated Dual-Mode Capacitance Readout IC for Subdisplay Panel Applications","authors":"Hamin Lee;Juwon Ham;Junmin Lee;Wooseok Jang;Seunghoon Ko","doi":"10.1109/LSSC.2024.3418523","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3418523","url":null,"abstract":"This letter presents a touch readout integrated circuit (IC) integrating both mutual- and self-capacitance sensing capabilities. The proposed IC aims to compensate for self-capacitance up to 620 pF by employing a combination of current-mode and capacitive-mode compensation techniques. A noise-monitoring scheme, based on the orthogonality of multicapacitance driving sequences, enhances readout performance by selectively detecting external noises during mutual-capacitance sensing operation. The IC achieved the measured signal-to-noise ratio (SNR) of 47.3, 30.6, and 36.1 dB in mutual-capacitance sensing and self-capacitance sensing of T/RX electrodes, respectively. By applying the noise-monitoring scheme, a 7-times higher noise power compared to the absence of external noise were successfully detected.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"195-198"},"PeriodicalIF":2.2,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141964919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2-to-10-b Output Precision Reconfigurable Compute-In-Memory Macro Leveraging Input Conditioning Using Residue Amplification 利用残差放大进行输入调节的 2-10-b 输出精度可重构内存计算巨集
IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-17 DOI: 10.1109/LSSC.2024.3415476
Balaji Vijayakumar;Ashwin Balagopal Sundar;Janakiraman Viraraghavan;Varchas Bharadwaj
Artificial intelligence workloads demand a wide range of multiply and accumulate (MAC) precision. Pitch-matching constraints in compute-in-memory (CIM) engines limit the analog-to-digital converter (ADC) precision to about 8 bits. This letter demonstrates a method of mapping a suitable input conditioned MAC range to the input dynamic range of the on-chip 7-b ADC, thereby achieving up to 10 bits of output MAC precision. A 424 Kb SRAM CIM macro was fabricated in TSMC 28 nm, which computes 72 MACs in parallel per cycle. Measurement results at nominal supply voltage show an energy efficiency of 196.6–102 TOPS/W/b for a 2–10 bit output MAC precision. Inference results on MNIST, CIFAR10, and CIFAR100 are shown with $leq 1%$ accuracy loss from the software baseline.
人工智能工作负载需要大范围的乘法和累加(MAC)精度。内存计算 (CIM) 引擎中的节距匹配限制将模数转换器 (ADC) 的精度限制在 8 位左右。这封信展示了一种将合适的输入条件 MAC 范围映射到片上 7-b ADC 输入动态范围的方法,从而实现高达 10 位的输出 MAC 精度。在 TSMC 28 纳米工艺中制造了 424 Kb SRAM CIM 宏,每个周期并行计算 72 个 MAC。在标称电源电压下的测量结果显示,2-10 位输出 MAC 精度的能效为 196.6-102 TOPS/W/b。在MNIST、CIFAR10和CIFAR100上的推理结果显示,与软件基线相比,精度损失为$leq 1%$。
{"title":"A 2-to-10-b Output Precision Reconfigurable Compute-In-Memory Macro Leveraging Input Conditioning Using Residue Amplification","authors":"Balaji Vijayakumar;Ashwin Balagopal Sundar;Janakiraman Viraraghavan;Varchas Bharadwaj","doi":"10.1109/LSSC.2024.3415476","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3415476","url":null,"abstract":"Artificial intelligence workloads demand a wide range of multiply and accumulate (MAC) precision. Pitch-matching constraints in compute-in-memory (CIM) engines limit the analog-to-digital converter (ADC) precision to about 8 bits. This letter demonstrates a method of mapping a suitable input conditioned MAC range to the input dynamic range of the on-chip 7-b ADC, thereby achieving up to 10 bits of output MAC precision. A 424 Kb SRAM CIM macro was fabricated in TSMC 28 nm, which computes 72 MACs in parallel per cycle. Measurement results at nominal supply voltage show an energy efficiency of 196.6–102 TOPS/W/b for a 2–10 bit output MAC precision. Inference results on MNIST, CIFAR10, and CIFAR100 are shown with \u0000<inline-formula> <tex-math>$leq 1%$ </tex-math></inline-formula>\u0000 accuracy loss from the software baseline.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"219-222"},"PeriodicalIF":2.2,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141991495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 81.5dB SNDR, 2.5 MHz Bandwidth Incremental Continuous-Time Delta-Sigma ADC in 180 nm CMOS 采用 180 纳米 CMOS 的 81.5dB SNDR、2.5 MHz 带宽增量式连续时间三角积分 ADC
IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-11 DOI: 10.1109/LSSC.2024.3412634
Aswani Kumar Unnam;Paramita Banerjee;Nagendra Krishnapura
Adapting a continuous time delta-sigma analog-to-digital converter (ADC) for incremental operation at high sampling rates degrades the noise and distortion due to potential overload of the modulator as it comes out of reset and nonlinear residue on the reset switch due to input current flowing through it in the reset phase. It is shown that the input and DAC currents must simultaneously begin to flow through the first integrating capacitor to minimize the possibility of overload. The first integrator reset has to be released just before the start of the DAC pulse. A feedforward path must be used to ensure that the DAC output is close to the input signal from the beginning. Blocking the input current from flowing through the reset switch in the reset phase eliminates the effect of the nonlinear residue. A 320 MS/s fourth-order incremental delta-sigma ADC prototype in an 180nm process using the above techniques has 90 dB dynamic range, 82 dB SNDR, and 84.5 dB SNR in a 2.5 MHz bandwidth. It consumes 46.3 mW from a 1.8V supply and occupies 0.7 mm2.
将连续时间三角积分模数转换器 (ADC) 改用于高采样率下的增量操作会降低噪声和失真,这是由于调制器在复位时可能过载,以及在复位阶段输入电流流过复位开关造成非线性残留。这表明,输入电流和 DAC 电流必须同时开始流过第一个积分电容器,以尽量减少过载的可能性。第一个积分器复位必须在 DAC 脉冲开始之前释放。必须使用前馈路径,以确保 DAC 输出从一开始就接近输入信号。在复位阶段阻止输入电流流经复位开关,可消除非线性残差的影响。采用上述技术的 320 MS/s 四阶增量三角积分 ADC 原型采用 180 纳米工艺制造,在 2.5 MHz 带宽内具有 90 dB 动态范围、82 dB SNDR 和 84.5 dB SNR。其 1.8V 电源功耗为 46.3 mW,占地面积为 0.7 mm2。
{"title":"An 81.5dB SNDR, 2.5 MHz Bandwidth Incremental Continuous-Time Delta-Sigma ADC in 180 nm CMOS","authors":"Aswani Kumar Unnam;Paramita Banerjee;Nagendra Krishnapura","doi":"10.1109/LSSC.2024.3412634","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3412634","url":null,"abstract":"Adapting a continuous time delta-sigma analog-to-digital converter (ADC) for incremental operation at high sampling rates degrades the noise and distortion due to potential overload of the modulator as it comes out of reset and nonlinear residue on the reset switch due to input current flowing through it in the reset phase. It is shown that the input and DAC currents must simultaneously begin to flow through the first integrating capacitor to minimize the possibility of overload. The first integrator reset has to be released just before the start of the DAC pulse. A feedforward path must be used to ensure that the DAC output is close to the input signal from the beginning. Blocking the input current from flowing through the reset switch in the reset phase eliminates the effect of the nonlinear residue. A 320 MS/s fourth-order incremental delta-sigma ADC prototype in an 180nm process using the above techniques has 90 dB dynamic range, 82 dB SNDR, and 84.5 dB SNR in a 2.5 MHz bandwidth. It consumes 46.3 mW from a 1.8V supply and occupies 0.7 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"191-194"},"PeriodicalIF":2.2,"publicationDate":"2024-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141618102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 500-V, 6.25-MHz GaN-IC With Gate Driver and Level Shifter for Off-Line Power Supplies 用于离线电源的 500V、6.25MHz GaN-IC,带栅极驱动器和电平转换器
IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-07 DOI: 10.1109/LSSC.2024.3411390
Niklas Deneke;Bernhard Wicht
Gallium Nitride (GaN) technology enables essential progress in energy efficiency and density, especially in off-line power supplies. This letter presents a monolithic GaN-IC, including a half-bridge, formed by two high-voltage power FETs with respective gate drivers and a high-voltage level shifter, forming a signal interface between high-side and low-side domain, making use of a GaN-on-SOI technology. Verified by experimental results, it achieves 500-V switching at 6.25 MHz and is thus well suited for off-line power supplies.
氮化镓(GaN)技术在能源效率和密度方面取得了重大进展,尤其是在离线电源方面。本文介绍了一种单片式氮化镓集成电路(GaN-IC),包括一个半桥,由两个高压功率场效应晶体管与各自的栅极驱动器和一个高压电平转换器组成,形成了高压侧和低压侧域之间的信号接口,并采用了氮化镓硅 (GaN-on-SOI) 技术。实验结果证明,它能在 6.25 MHz 频率下实现 500 V 开关,因此非常适合离线电源。
{"title":"A 500-V, 6.25-MHz GaN-IC With Gate Driver and Level Shifter for Off-Line Power Supplies","authors":"Niklas Deneke;Bernhard Wicht","doi":"10.1109/LSSC.2024.3411390","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3411390","url":null,"abstract":"Gallium Nitride (GaN) technology enables essential progress in energy efficiency and density, especially in off-line power supplies. This letter presents a monolithic GaN-IC, including a half-bridge, formed by two high-voltage power FETs with respective gate drivers and a high-voltage level shifter, forming a signal interface between high-side and low-side domain, making use of a GaN-on-SOI technology. Verified by experimental results, it achieves 500-V switching at 6.25 MHz and is thus well suited for off-line power supplies.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"207-210"},"PeriodicalIF":2.2,"publicationDate":"2024-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141964881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 33V to 1V Ripple-Less Buck Converter With the Inverted AC Current Replica Circuit and Sub-0.5% Output Ripple for 5G Low Earth Orbit Application 一种 33V 至 1V 无纹波降压转换器,具有反向交流电流复制电路和低于 0.5% 的输出纹波,适用于 5G 低地球轨道应用
IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-05 DOI: 10.1109/LSSC.2024.3410034
Yi-Hsiang Kao;Jie-Lin Wu;Chih-Cherng Liao;Hui-Hsuan Chang;Wei-Cheng Huang;Hsing-Yen Tsai;Rong-Bin Guo;Ke-Horng Chen;Kuo-Lin Zeng;Ying-Hsi Lin;Shian-Ru Lin;Tsung-Yen Tsai
The proposed ripple-less buck converter (RLBC) uses a two-phase topology with an inverted ac current replica (IACCR) circuit to reduce output voltage ripple to meet the error vector magnitude (EVM) requirement of 5G new radio (5G NR) low earth orbit (LEO) application. Assistance inductance (AI) circuit emulates inductor current to avoid using extra inductors. Ripple minimization (RM) circuit further reduces output ripple by synchronizing the switching moment of power MOSFETs. Therefore, the proposed RLBC achieves 5G NR LEO standards with an EVM of -28.85dB.
所提出的无纹波降压转换器(RLBC)采用带有反相交流电流复制(IACCR)电路的两相拓扑结构,以降低输出电压纹波,从而满足 5G 新无线电(5G NR)低地球轨道(LEO)应用对误差矢量幅度(EVM)的要求。辅助电感 (AI) 电路模拟电感电流,以避免使用额外的电感器。纹波最小化(RM)电路通过同步功率 MOSFET 的开关时刻,进一步降低输出纹波。因此,拟议的 RLBC 实现了 5G NR LEO 标准,EVM 为 -28.85dB。
{"title":"A 33V to 1V Ripple-Less Buck Converter With the Inverted AC Current Replica Circuit and Sub-0.5% Output Ripple for 5G Low Earth Orbit Application","authors":"Yi-Hsiang Kao;Jie-Lin Wu;Chih-Cherng Liao;Hui-Hsuan Chang;Wei-Cheng Huang;Hsing-Yen Tsai;Rong-Bin Guo;Ke-Horng Chen;Kuo-Lin Zeng;Ying-Hsi Lin;Shian-Ru Lin;Tsung-Yen Tsai","doi":"10.1109/LSSC.2024.3410034","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3410034","url":null,"abstract":"The proposed ripple-less buck converter (RLBC) uses a two-phase topology with an inverted ac current replica (IACCR) circuit to reduce output voltage ripple to meet the error vector magnitude (EVM) requirement of 5G new radio (5G NR) low earth orbit (LEO) application. Assistance inductance (AI) circuit emulates inductor current to avoid using extra inductors. Ripple minimization (RM) circuit further reduces output ripple by synchronizing the switching moment of power MOSFETs. Therefore, the proposed RLBC achieves 5G NR LEO standards with an EVM of -28.85dB.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"183-186"},"PeriodicalIF":2.2,"publicationDate":"2024-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141474854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
期刊
IEEE Solid-State Circuits Letters
全部 Acc. Chem. Res. ACS Applied Bio Materials ACS Appl. Electron. Mater. ACS Appl. Energy Mater. ACS Appl. Mater. Interfaces ACS Appl. Nano Mater. ACS Appl. Polym. Mater. ACS BIOMATER-SCI ENG ACS Catal. ACS Cent. Sci. ACS Chem. Biol. ACS Chemical Health & Safety ACS Chem. Neurosci. ACS Comb. Sci. ACS Earth Space Chem. ACS Energy Lett. ACS Infect. Dis. ACS Macro Lett. ACS Mater. Lett. ACS Med. Chem. Lett. ACS Nano ACS Omega ACS Photonics ACS Sens. ACS Sustainable Chem. Eng. ACS Synth. Biol. Anal. Chem. BIOCHEMISTRY-US Bioconjugate Chem. BIOMACROMOLECULES Chem. Res. Toxicol. Chem. Rev. Chem. Mater. CRYST GROWTH DES ENERG FUEL Environ. Sci. Technol. Environ. Sci. Technol. Lett. Eur. J. Inorg. Chem. IND ENG CHEM RES Inorg. Chem. J. Agric. Food. Chem. J. Chem. Eng. Data J. Chem. Educ. J. Chem. Inf. Model. J. Chem. Theory Comput. J. Med. Chem. J. Nat. Prod. J PROTEOME RES J. Am. Chem. Soc. LANGMUIR MACROMOLECULES Mol. Pharmaceutics Nano Lett. Org. Lett. ORG PROCESS RES DEV ORGANOMETALLICS J. Org. Chem. J. Phys. Chem. J. Phys. Chem. A J. Phys. Chem. B J. Phys. Chem. C J. Phys. Chem. Lett. Analyst Anal. Methods Biomater. Sci. Catal. Sci. Technol. Chem. Commun. Chem. Soc. Rev. CHEM EDUC RES PRACT CRYSTENGCOMM Dalton Trans. Energy Environ. Sci. ENVIRON SCI-NANO ENVIRON SCI-PROC IMP ENVIRON SCI-WAT RES Faraday Discuss. Food Funct. Green Chem. Inorg. Chem. Front. Integr. Biol. J. Anal. At. Spectrom. J. Mater. Chem. A J. Mater. Chem. B J. Mater. Chem. C Lab Chip Mater. Chem. Front. Mater. Horiz. MEDCHEMCOMM Metallomics Mol. Biosyst. Mol. Syst. Des. Eng. Nanoscale Nanoscale Horiz. Nat. Prod. Rep. New J. Chem. Org. Biomol. Chem. Org. Chem. Front. PHOTOCH PHOTOBIO SCI PCCP Polym. Chem.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1