This letter presents a backscatter chip that features bidirectional communication with commodity bluetooth low-energy (BLE) transceivers. For uplink, the chip reflects a reverse-whitened BLE tone into single-sideband (SSB) GFSK-modulated BLE packets via a proposed replica VCO-based GFSK modulator and an inductor-free SSB reflector. For downlink, the BLE packets are frequency down-converted passively by utilizing a reverse-whitened BLE tone followed by a proposed self-calibrated GFSK demodulator to recover the downlink data at ultralow power with improved robustness. A dual-linearly polarized microstrip patch antenna (DPMPA) is integrated to enable concurrent RF energy harvesting and communication in a wearable form factor. Implemented in 65-nm CMOS, the chip consumes $1.4~mu $ W for downlink and $15.8~mu $ W for uplink. Wireless tests demonstrated a 50 cm downlink and >3 m uplink ranges at 20 dBm EIRP.
{"title":"A Battery-Free BLE Backscatter Communication Chip for Wearable Systems","authors":"Yongling Zhang;Ji Xiong;Junzai Chen;Xiaoyu Li;Jinrui Zuo;Yan Wang;Xiaoyi Wang;Miao Meng","doi":"10.1109/LSSC.2025.3612423","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3612423","url":null,"abstract":"This letter presents a backscatter chip that features bidirectional communication with commodity bluetooth low-energy (BLE) transceivers. For uplink, the chip reflects a reverse-whitened BLE tone into single-sideband (SSB) GFSK-modulated BLE packets via a proposed replica VCO-based GFSK modulator and an inductor-free SSB reflector. For downlink, the BLE packets are frequency down-converted passively by utilizing a reverse-whitened BLE tone followed by a proposed self-calibrated GFSK demodulator to recover the downlink data at ultralow power with improved robustness. A dual-linearly polarized microstrip patch antenna (DPMPA) is integrated to enable concurrent RF energy harvesting and communication in a wearable form factor. Implemented in 65-nm CMOS, the chip consumes <inline-formula> <tex-math>$1.4~mu $ </tex-math></inline-formula>W for downlink and <inline-formula> <tex-math>$15.8~mu $ </tex-math></inline-formula>W for uplink. Wireless tests demonstrated a 50 cm downlink and >3 m uplink ranges at 20 dBm EIRP.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"297-300"},"PeriodicalIF":2.0,"publicationDate":"2025-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145223688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sparsity has recently attracted increased attention in the machine learning (ML) community due to its potential to improve performance and energy efficiency by eliminating ineffectual computations. As ML models evolve rapidly, reconfigurable architectures, such as coarse-grained reconfigurable arrays (CGRAs), are being explored to adapt to and accelerate emerging models. Previous CGRA designs have supported unstructured sparsity and reported promising speedups and energy savings for compute-intensive kernels. However, these approaches still face performance bottlenecks when accelerating entire sparse ML networks. In this letter, we identify the primary sources of inefficiency in prior CGRA-based approaches and present Opal, a CGRA SoC with three key contributions: 1) flexible dataflow architecture supporting Gustavson’s dataflow for sparse matrix multiplication; 2) high-throughput sparse hardware primitives; and 3) enhanced processing elements to support mapping all ML operations on the CGRA. As a result, Opal achieves a 66% to 79% reduction in runtime and energy consumption across our evaluated sparse graph neural network benchmarks compared to prior CGRA solutions which only target kernel acceleration.
{"title":"Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications","authors":"Po-Han Chen;Bo Wun Cheng;Michael Oduoza;Zhouhua Xie;Rupert Lu;Sai Gautham Ravipati;Kalhan Koul;Alex Carsello;Yuchen Mei;Mark Horowitz;Priyanka Raina","doi":"10.1109/LSSC.2025.3613245","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3613245","url":null,"abstract":"Sparsity has recently attracted increased attention in the machine learning (ML) community due to its potential to improve performance and energy efficiency by eliminating ineffectual computations. As ML models evolve rapidly, reconfigurable architectures, such as coarse-grained reconfigurable arrays (CGRAs), are being explored to adapt to and accelerate emerging models. Previous CGRA designs have supported unstructured sparsity and reported promising speedups and energy savings for compute-intensive kernels. However, these approaches still face performance bottlenecks when accelerating entire sparse ML networks. In this letter, we identify the primary sources of inefficiency in prior CGRA-based approaches and present Opal, a CGRA SoC with three key contributions: 1) flexible dataflow architecture supporting Gustavson’s dataflow for sparse matrix multiplication; 2) high-throughput sparse hardware primitives; and 3) enhanced processing elements to support mapping all ML operations on the CGRA. As a result, Opal achieves a 66% to 79% reduction in runtime and energy consumption across our evaluated sparse graph neural network benchmarks compared to prior CGRA solutions which only target kernel acceleration.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"293-296"},"PeriodicalIF":2.0,"publicationDate":"2025-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145223703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Capacitive touch screens have become the dominant user interface over the past decade. Achieving high framerates with low power consumption remains a critical design goal for touch systems. The conventional charge-recycling technique reduces driving power by 64%, but it relies on off-chip capacitors. To address this issue, we propose a tri-level energy recycling scheme, in which energy released during the 2-to-1 transition is recycled to power the 0-to-1 transition on the complementary channel. This approach achieves a 25% power reduction using on-chip transmission gates. Additionally, a compressive sensing method is introduced to selectively process touched RX channels while bypassing the others, reducing the number of fine ADCs by a factor of four compared to conventional two-step sensing. The proposed techniques are implemented in a 65-nm CMOS process and integrated into a $32times 20$ channel prototype occupying 2.4 mm2. Measurement results show that the chip consumes only 2.6 mW at a framerate of 1513 Hz. The signal-to-noise ratio (SNR) reaches 49.7 dB for finger touch and 28.7 dB for a 1-mm $Phi $ stylus, resulting in an energy efficiency of 10.66 pJ/step.
{"title":"A Fully Dynamic Capacitive Touch Sensor With Tri-Level Energy Recycling and Compressive Sensing Technique","authors":"Xiangdong Feng;Zhiyu Wang;Haoyang Li;Jiaqing Li;Wei-Chin Lin;Xin Hu;Zhong Tang;Yuyan Liu;Qinwen Fan;Yuxuan Luo;Bo Zhao","doi":"10.1109/LSSC.2025.3612093","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3612093","url":null,"abstract":"Capacitive touch screens have become the dominant user interface over the past decade. Achieving high framerates with low power consumption remains a critical design goal for touch systems. The conventional charge-recycling technique reduces driving power by 64%, but it relies on off-chip capacitors. To address this issue, we propose a tri-level energy recycling scheme, in which energy released during the 2-to-1 transition is recycled to power the 0-to-1 transition on the complementary channel. This approach achieves a 25% power reduction using on-chip transmission gates. Additionally, a compressive sensing method is introduced to selectively process touched RX channels while bypassing the others, reducing the number of fine ADCs by a factor of four compared to conventional two-step sensing. The proposed techniques are implemented in a 65-nm CMOS process and integrated into a <inline-formula> <tex-math>$32times 20$ </tex-math></inline-formula> channel prototype occupying 2.4 mm2. Measurement results show that the chip consumes only 2.6 mW at a framerate of 1513 Hz. The signal-to-noise ratio (SNR) reaches 49.7 dB for finger touch and 28.7 dB for a 1-mm <inline-formula> <tex-math>$Phi $ </tex-math></inline-formula> stylus, resulting in an energy efficiency of 10.66 pJ/step.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"337-340"},"PeriodicalIF":2.0,"publicationDate":"2025-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-18DOI: 10.1109/LSSC.2025.3611484
Ronald Wijermars;Yi-Han Ou-Yang;Sijun Du;Dante G. Muratore
This letter describes a fast-settling active rectifier for a 40.68 MHz wireless power transfer receiver for implantable applications. Fast-settling and low power are achieved through a novel direct voltage-domain compensation technique. The rectifier maintains high efficiency during load and link variations required for downlink communication. The system was fabricated in 40nm CMOS and achieves a voltage conversion ratio of 93.9% and a simulated power conversion efficiency of 90.1% in a 0.19 mm2 area, resulting in a 118 mW/mm2 power density while integrating the resonance and filter capacitors. The worst-case settling of the ON- and OFF-delay compensation in the active rectifier is 200 ns, which is the fastest reported to date.
{"title":"A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants","authors":"Ronald Wijermars;Yi-Han Ou-Yang;Sijun Du;Dante G. Muratore","doi":"10.1109/LSSC.2025.3611484","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3611484","url":null,"abstract":"This letter describes a fast-settling active rectifier for a 40.68 MHz wireless power transfer receiver for implantable applications. Fast-settling and low power are achieved through a novel direct voltage-domain compensation technique. The rectifier maintains high efficiency during load and link variations required for downlink communication. The system was fabricated in 40nm CMOS and achieves a voltage conversion ratio of 93.9% and a simulated power conversion efficiency of 90.1% in a 0.19 mm2 area, resulting in a 118 mW/mm2 power density while integrating the resonance and filter capacitors. The worst-case settling of the ON- and OFF-delay compensation in the active rectifier is 200 ns, which is the fastest reported to date.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"305-308"},"PeriodicalIF":2.0,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145255928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fully integrated galvanic isolator for gate drivers that supports high-speed, asynchronous, full-duplex communication is presented. Data transmission from the microcontroller to the power device is achieved using amplitude-shift keying (ASK) at 100 Mb/s, while simultaneous communication in the opposite direction is implemented using frequency-shift keying (FSK) at 167 Mb/s. A delay-locked loop (DLL)-based FSK demodulator enables robust operation in a completely asynchronous communication scenario. Prototypes were fabricated in a 0.13-$mu $ m HV CMOS technology, covering an area of 2.2 mm2. The system operates from a low 1.5-V supply with a total power consumption of 8.2 mW. Measured propagation delays are under 8 ns for ASK and below 4 ns for FSK at their respective maximum data rates.
{"title":"A Fully Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication","authors":"Lucrezia Navarin;Karl Norling;Marco Parenzan;Stefano Ruzzu;Andrea Neviani;Andrea Bevilacqua","doi":"10.1109/LSSC.2025.3611018","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3611018","url":null,"abstract":"A fully integrated galvanic isolator for gate drivers that supports high-speed, asynchronous, full-duplex communication is presented. Data transmission from the microcontroller to the power device is achieved using amplitude-shift keying (ASK) at 100 Mb/s, while simultaneous communication in the opposite direction is implemented using frequency-shift keying (FSK) at 167 Mb/s. A delay-locked loop (DLL)-based FSK demodulator enables robust operation in a completely asynchronous communication scenario. Prototypes were fabricated in a 0.13-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m HV CMOS technology, covering an area of 2.2 mm2. The system operates from a low 1.5-V supply with a total power consumption of 8.2 mW. Measured propagation delays are under 8 ns for ASK and below 4 ns for FSK at their respective maximum data rates.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"289-292"},"PeriodicalIF":2.0,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-17DOI: 10.1109/LSSC.2025.3610901
David Dolt;Samuel Palermo
This letter presents a radiation-hardened (rad-hard) subsampled phase-locked loop (SS-PLL) that achieves state-of-the-art jitter performance while incorporating radiation-hardened techniques to mitigate single-event-upsets (SEUs) present in the space environment. Furthermore, rad-hard techniques are incorporated in each core PLL subblock which include a rad-hard charge-pump Gm cell, a pulser circuit with triple modular redundancy (TMR), and a quad-core voltage-controlled oscillator (VCO) with varactor hardening and LC tail filters. Implemented in a 16-nm FinFET process, the PLL consumes 36.5 mW of power and achieves a jitter of 45.82 fs at 19.5 GHz. Testing at a cyclotron facility verifies robust SEU performance up to an LET of 55 MeV$cdot $ cm2/mg.
{"title":"A 19.5-GHz Radiation-Hardened Sub-Sampled PLL With Quad-Core VCO in 16-nm FinFET Achieving Sub-50 fs Jitter","authors":"David Dolt;Samuel Palermo","doi":"10.1109/LSSC.2025.3610901","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3610901","url":null,"abstract":"This letter presents a radiation-hardened (rad-hard) subsampled phase-locked loop (SS-PLL) that achieves state-of-the-art jitter performance while incorporating radiation-hardened techniques to mitigate single-event-upsets (SEUs) present in the space environment. Furthermore, rad-hard techniques are incorporated in each core PLL subblock which include a rad-hard charge-pump Gm cell, a pulser circuit with triple modular redundancy (TMR), and a quad-core voltage-controlled oscillator (VCO) with varactor hardening and LC tail filters. Implemented in a 16-nm FinFET process, the PLL consumes 36.5 mW of power and achieves a jitter of 45.82 fs at 19.5 GHz. Testing at a cyclotron facility verifies robust SEU performance up to an LET of 55 MeV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2/mg.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"285-288"},"PeriodicalIF":2.0,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145223694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-10DOI: 10.1109/LSSC.2025.3608096
Kai Cui;Honglei Xu;Yingduo Duan;Yan Lu;Xiaoya Fan;Yanzhao Ma
This letter presents a linear dynamic voltage scaling (DVS) technique using a dual-loop multistage charge-pump maintaining the minimum voltage headroom for implantable neurostimulation. By adopting an analog DVS with adaptive feedback divider, the stimulus current source could be always kept operating at the boundary of the saturation region and the linear region under different stimulus currents. Furthermore, a simple mode-switched control is introduced to improve the loop response of charge-pump. The design has been fabricated in a 0.18-$mu $ m BCD process. The DVS technique increases the measured stimulus efficiency up to 52.8% higher than a fixed supply voltage with a peak efficiency of 89.6% in the range of the stimulus current from 0.5 mA to 0.9 mA.
{"title":"A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation","authors":"Kai Cui;Honglei Xu;Yingduo Duan;Yan Lu;Xiaoya Fan;Yanzhao Ma","doi":"10.1109/LSSC.2025.3608096","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608096","url":null,"abstract":"This letter presents a linear dynamic voltage scaling (DVS) technique using a dual-loop multistage charge-pump maintaining the minimum voltage headroom for implantable neurostimulation. By adopting an analog DVS with adaptive feedback divider, the stimulus current source could be always kept operating at the boundary of the saturation region and the linear region under different stimulus currents. Furthermore, a simple mode-switched control is introduced to improve the loop response of charge-pump. The design has been fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m BCD process. The DVS technique increases the measured stimulus efficiency up to 52.8% higher than a fixed supply voltage with a peak efficiency of 89.6% in the range of the stimulus current from 0.5 mA to 0.9 mA.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"261-264"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145110302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a low power DSP-based single-chip 800GbE PAM-4 PHY transceiver in 7 nm process capable of driving eight lanes of up to 112-Gb/s. It supports both electrical and optical links with monolithic integrated laser driver enabling direct-drive PAM-4 output capability for EML and silicon photonics. The transceiver supports 42 dB IL channel at Nyquist with pre-FEC BER<3E-8. The per-lane analog power efficiency is 2.59pJ/b for low-swing drive mode and 4.58 pJ/b for direct-drive mode.
本文提出了一种低功耗、基于dsp的单片800GbE PAM-4 PHY收发器，采用7nm工艺，可驱动8通道，最高速率为112gb /s。它通过单片集成激光驱动器支持电气和光学链路，为EML和硅光子学提供直接驱动PAM-4输出能力。收发器在奈奎斯特支持42 dB IL通道，预fec误码率<3E-8。低摆幅驱动模式下的每车道模拟功率效率为2.59pJ/b，直接驱动模式下为4.58 pJ/b。
{"title":"An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm","authors":"Chang Liu;Burak Catli;Yong Liu;Anand Vasani;Guansheng Li;Kun Chuai;Lakshmi Rao;Yang Liu;Xin Meng;Jiawen Zhang;Tim He;Batu Dayanik;Vadim Milirud;Meisam Honarvar Nazari;Hyo Gyuem Rhew;Derui Kong;Arvindh Iyer;Nan Wang;Alireza Nilchi;Aminghasem Safarian;Ray Wang;Hyung-Joon Jeon;Xiaochen Yang;Boyu Hu;Jerry Han;Adesh Garg;Kumar Thasari;Heng Zhang;Namik Kocaman;Ali Nazemi;Delong Cui;Afshin Momtaz;Jun Cao","doi":"10.1109/LSSC.2025.3608134","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608134","url":null,"abstract":"This work presents a low power DSP-based single-chip 800GbE PAM-4 PHY transceiver in 7 nm process capable of driving eight lanes of up to 112-Gb/s. It supports both electrical and optical links with monolithic integrated laser driver enabling direct-drive PAM-4 output capability for EML and silicon photonics. The transceiver supports 42 dB IL channel at Nyquist with pre-FEC BER<3E-8. The per-lane analog power efficiency is 2.59pJ/b for low-swing drive mode and 4.58 pJ/b for direct-drive mode.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"281-284"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-10DOI: 10.1109/LSSC.2025.3608187
Woojin Lee;Changmin Sim;Changjoo Kim;Jinwoo Jeon;Hyundo Jung;Taihyun Kim;Chulwoo Kim
This work presents a capacitive-latch (C-latch) true random number generator (TRNG) that achieves both inverter mismatch autozeroing and accelerated evaluation by utilizing coupling capacitors. The proposed C-latch TRNG samples the mismatch between inverter equalization voltages through coupling capacitors during the equalization phase, effectively autozeroing inverter mismatch and enabling high-entropy raw bit generation without calibration. In addition, larger coupling capacitors reduce the effective capacitance in the gate-node stochastic differential equation, resulting in faster evaluation and reduced energy consumption. Fabricated in a 28-nm CMOS process, the TRNG achieves a minimum energy consumption of 38.1 fJ/bit at 0.4-V supply voltage and the maximum throughput of 162.48 Mb/s at 0.9 V. A 4-bit von Neumann post processor consistently extract a full entropy, which successfully passes all NIST SP800-22 and NIST SP800-90B randomness tests under wide voltage and temperature variations, implying both robustness and cryptographic suitability.
{"title":"A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation","authors":"Woojin Lee;Changmin Sim;Changjoo Kim;Jinwoo Jeon;Hyundo Jung;Taihyun Kim;Chulwoo Kim","doi":"10.1109/LSSC.2025.3608187","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608187","url":null,"abstract":"This work presents a capacitive-latch (C-latch) true random number generator (TRNG) that achieves both inverter mismatch autozeroing and accelerated evaluation by utilizing coupling capacitors. The proposed C-latch TRNG samples the mismatch between inverter equalization voltages through coupling capacitors during the equalization phase, effectively autozeroing inverter mismatch and enabling high-entropy raw bit generation without calibration. In addition, larger coupling capacitors reduce the effective capacitance in the gate-node stochastic differential equation, resulting in faster evaluation and reduced energy consumption. Fabricated in a 28-nm CMOS process, the TRNG achieves a minimum energy consumption of 38.1 fJ/bit at 0.4-V supply voltage and the maximum throughput of 162.48 Mb/s at 0.9 V. A 4-bit von Neumann post processor consistently extract a full entropy, which successfully passes all NIST SP800-22 and NIST SP800-90B randomness tests under wide voltage and temperature variations, implying both robustness and cryptographic suitability.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"265-268"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a tri-well implementation of MOS capacitors designed to tackle the challenge of high parasitic capacitance. By serially connecting the three parasitic well junction capacitors between the three wells (N-Well, deep P-Well, and deep N-Well) and substrate (PSUB), the parasitic capacitance can be significantly decreased. A higher bias voltage is applied using a sufficiently large resistor to further reduce parasitic capacitance. Furthermore, we also present a simple and effective method for testing very small parasitic capacitance using off-chip inverters. The test chip was fabricated using the 180-nm BCD process. The measurement results indicate that the ratio of parasitic to flying capacitance can be reduced to as low as 0.67% for 1.8-V MOS capacitors through series-connected tri-well junctions with effective biasing while only increasing a 7.7% the chip area overhead compared to the dual-well junctions.
这封信提出了一种三孔实现的MOS电容器，旨在解决高寄生电容的挑战。通过在三个孔（n孔、深p孔和深n孔）和衬底（PSUB）之间串联三个寄生孔结电容器，可以显著降低寄生电容。使用足够大的电阻施加更高的偏置电压以进一步减小寄生电容。此外，我们还提出了一种使用片外逆变器测试极小寄生电容的简单有效方法。测试芯片采用180nm BCD工艺制备。测量结果表明，通过有效偏置串联的三孔结，1.8 v MOS电容的寄生/飞行电容比可降至0.67%，而与双孔结相比，芯片面积开销仅增加7.7%。
{"title":"Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions","authors":"Zhendong Li;Yongjuan Shi;Yifan Jiang;Chen Hu;Junting Chen;Mengyuan Hua;Xun Liu;Junmin Jiang","doi":"10.1109/LSSC.2025.3608282","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608282","url":null,"abstract":"This letter presents a tri-well implementation of MOS capacitors designed to tackle the challenge of high parasitic capacitance. By serially connecting the three parasitic well junction capacitors between the three wells (N-Well, deep P-Well, and deep N-Well) and substrate (PSUB), the parasitic capacitance can be significantly decreased. A higher bias voltage is applied using a sufficiently large resistor to further reduce parasitic capacitance. Furthermore, we also present a simple and effective method for testing very small parasitic capacitance using off-chip inverters. The test chip was fabricated using the 180-nm BCD process. The measurement results indicate that the ratio of parasitic to flying capacitance can be reduced to as low as 0.67% for 1.8-V MOS capacitors through series-connected tri-well junctions with effective biasing while only increasing a 7.7% the chip area overhead compared to the dual-well junctions.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"277-280"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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