This letter presents an approximate digital compute-in-memory (CIM) macro for low-power edge AI inference. It introduces three hierarchical innovations: 1) novel fused approximate multiply-add units (FAMUs) that reduces power and area consumption; 2) a bit-critical weight allocation architecture that optimally balances accuracy and hardware cost; and 3) a dynamic sparsity-adaptive configuration method to minimize accuracy loss in real-time. The macro achieves an energy efficiency of 60.35 TOPS/W and an area efficiency of 1105 GOPS/mm2 for INT8 MACs, outperforming prior works. It attains negligible accuracy degradation on multiple mainstream datasets and suits well for edge AI inference.
{"title":"An Approximate Digital CIM Macro With Low-Power Multiply-Add Units and Dynamic Sparse-Adaptive Configuring for Edge AI Inference","authors":"Xiaofeng Li;Yi Zhan;Purui Zhu;Rui Zhou;Jiayin Song;Heng You;Yumei Zhou;Shushan Qiao","doi":"10.1109/LSSC.2026.3652570","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3652570","url":null,"abstract":"This letter presents an approximate digital compute-in-memory (CIM) macro for low-power edge AI inference. It introduces three hierarchical innovations: 1) novel fused approximate multiply-add units (FAMUs) that reduces power and area consumption; 2) a bit-critical weight allocation architecture that optimally balances accuracy and hardware cost; and 3) a dynamic sparsity-adaptive configuration method to minimize accuracy loss in real-time. The macro achieves an energy efficiency of 60.35 TOPS/W and an area efficiency of 1105 GOPS/mm2 for INT8 MACs, outperforming prior works. It attains negligible accuracy degradation on multiple mainstream datasets and suits well for edge AI inference.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"45-48"},"PeriodicalIF":2.0,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Advanced CMOS memory requires voltage biasing assist techniques to achieve low operating voltages (Vmin), which must be deactivated at higher voltages for high electric field reliability. Centralized power management unit (PMU) control signals face timing synchronization and process tracking challenges when distributed across cores to activate assist circuits in various static random access memory arrays, limiting their effectiveness. This restricts the power and area benefits that could be gained from an in-situ, memory circuit-assist enable/disable mechanism. To address this, we propose a novel voltage crossover-based memory assist switching circuit implemented in Intel 18A-RibbonFET technology featuring backside power delivery. Its $150times $ area efficiency enables independent placement within memory blocks, offering 19% array-level power and 17% performance improvements. Silicon measurements show tight variation control and strong simulation correlation.
{"title":"A Standalone-in-Memory Voltage Crossover-Based Assist Switching Circuit for Reliable and Efficient Process Tracking Memory Vmin Improvement in Intel 18A-RibbonFET Technology","authors":"Saroj Satapathy;Amlan Ghosh;John Riley;Jalal Quadri;Jaydeep Kulkarni;Feroze Merchant","doi":"10.1109/LSSC.2026.3652110","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3652110","url":null,"abstract":"Advanced CMOS memory requires voltage biasing assist techniques to achieve low operating voltages (Vmin), which must be deactivated at higher voltages for high electric field reliability. Centralized power management unit (PMU) control signals face timing synchronization and process tracking challenges when distributed across cores to activate assist circuits in various static random access memory arrays, limiting their effectiveness. This restricts the power and area benefits that could be gained from an in-situ, memory circuit-assist enable/disable mechanism. To address this, we propose a novel voltage crossover-based memory assist switching circuit implemented in Intel 18A-RibbonFET technology featuring backside power delivery. Its <inline-formula> <tex-math>$150times $ </tex-math></inline-formula> area efficiency enables independent placement within memory blocks, offering 19% array-level power and 17% performance improvements. Silicon measurements show tight variation control and strong simulation correlation.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"37-40"},"PeriodicalIF":2.0,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-02DOI: 10.1109/LSSC.2025.3650657
D. Cerviño Fungueiriño;L. A. Enthoven;J. van Staveren;M. Babaie;F. Sebastiano
This work presents a cryo-CMOS smart temperature sensor operating from room temperature down to 5 K. By adopting sensing elements (CMOS bulk diodes, pMOS/DTMOS in weak inversion) that circumvent the poor cryogenic performance of Si BJTs, a robust switched-capacitor second-order sigma–delta readout and cryogenic-aware design techniques, the sensor achieves a maximum error of ±0.73 K (four samples and two-point trim), a resolution below 0.05 K for a 102.4-ms readout duration, and a power consumption of $mathrm {15.5~mu text {W} }$ ($mathrm {93.5~mu text {W} }$ ) at 5 K (296 K).
这项工作提出了一种低温cmos智能温度传感器，工作温度从室温降至5 K。该传感器采用了克服Si BJTs低温性能差的传感元件（CMOS体二极管、弱反转的pMOS/DTMOS）、稳健的开关电容二阶sigma-delta读出和低温感知设计技术，最大误差为±0.73 K(4个样本和两点trim)，读取时间为102.4 ms，分辨率低于0.05 K, 5 K （296 K）时功耗为$ mathm {15.5~mu text {W}}$ （$ mathm {93.5~mu text {W}}$）。
{"title":"A Cryo-CMOS Smart Temperature Sensor for the Ultrawide Temperature Range From 5 K to 296 K","authors":"D. Cerviño Fungueiriño;L. A. Enthoven;J. van Staveren;M. Babaie;F. Sebastiano","doi":"10.1109/LSSC.2025.3650657","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3650657","url":null,"abstract":"This work presents a cryo-CMOS smart temperature sensor operating from room temperature down to 5 K. By adopting sensing elements (CMOS bulk diodes, pMOS/DTMOS in weak inversion) that circumvent the poor cryogenic performance of Si BJTs, a robust switched-capacitor second-order sigma–delta readout and cryogenic-aware design techniques, the sensor achieves a maximum error of ±0.73 K (four samples and two-point trim), a resolution below 0.05 K for a 102.4-ms readout duration, and a power consumption of <inline-formula> <tex-math>$mathrm {15.5~mu text {W} }$ </tex-math></inline-formula> (<inline-formula> <tex-math>$mathrm {93.5~mu text {W} }$ </tex-math></inline-formula>) at 5 K (296 K).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"29-32"},"PeriodicalIF":2.0,"publicationDate":"2026-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145982208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-29DOI: 10.1109/LSSC.2025.3649215
Qibang Sun;Liqun Feng;Woogeun Rhee;Hanjun Jiang
This brief presents a 0.015-mm2 0.5-V synthesizable hybrid phase locked loop (PLL). All blocks including an analog proportional-gain path can be logically or physically synthesized with digital cells and hardware languages. To mitigate the mismatch and common-mode fluctuation problems of a voltage-mode phase detector, multiphase proportional-gain paths are designed for low spur. An 1.2-GHz prototype PLL implemented in 28-nm CMOS achieves <–65-dBc reference spur under 0.5-V supply. The proposed PLL occupies a core area of only 0.015 mm2 by leveraging the synthesized design.
{"title":"A 0.015-mm2 0.5 -V Synthesizable Hybrid PLL With Multiphase Linear Proportional-Gain Paths","authors":"Qibang Sun;Liqun Feng;Woogeun Rhee;Hanjun Jiang","doi":"10.1109/LSSC.2025.3649215","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3649215","url":null,"abstract":"This brief presents a 0.015-mm2 0.5-V synthesizable hybrid phase locked loop (PLL). All blocks including an analog proportional-gain path can be logically or physically synthesized with digital cells and hardware languages. To mitigate the mismatch and common-mode fluctuation problems of a voltage-mode phase detector, multiphase proportional-gain paths are designed for low spur. An 1.2-GHz prototype PLL implemented in 28-nm CMOS achieves <–65-dBc reference spur under 0.5-V supply. The proposed PLL occupies a core area of only 0.015 mm2 by leveraging the synthesized design.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"77-80"},"PeriodicalIF":2.0,"publicationDate":"2025-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146223694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-22DOI: 10.1109/LSSC.2025.3646815
Chaorong Wang;Quan Pan;Xiaohu Fang
This letter presents a design methodology for broadband and compact millimeter-wave (mm-wave) single-pole double-throw (SPDT) switches targeting the Ku–Ka band. Conventional SPDT switches based on quarter-wavelength transmission line typically occupy significant chip area, while alternative designs utilizing standard $pi $ -type equivalent circuits often suffer from bandwidth degradation due to the parasitic inductance at the isolation path. To overcome these limitations, a novel SPDT architecture based on modified $pi $ -networks is proposed. This approach incorporates the parasitic inductance of the isolation path into the $pi $ -network design, effectively enhancing the bandwidth performance without increasing circuit complexity. For validation, an SPDT switch was implemented using a 0.15-$mu $ m GaN MMIC process, covering the 10–28 GHz band. Measurement results confirm that the switch achieves an insertion loss below 2.1 dB, return loss better than 12 dB and isolation greater than 42 dB, with a compact core chip area of only 0.62 mm2.
本文介绍了针对Ku-Ka频段的宽带和紧凑型毫米波（mm波）单极双掷（SPDT）开关的设计方法。基于四分之一波长传输线的传统SPDT开关通常占用大量芯片面积，而利用标准$pi $型等效电路的替代设计通常由于隔离路径上的寄生电感而导致带宽下降。为了克服这些限制，提出了一种基于改进$pi $ -网络的SPDT架构。该方法将隔离路径的寄生电感集成到$pi $ -网络设计中，在不增加电路复杂性的情况下有效地提高了带宽性能。为了验证，使用0.15- $mu $ m GaN MMIC工艺实现了SPDT开关，覆盖10-28 GHz频段。测量结果证实，该开关的插入损耗低于2.1 dB，回波损耗优于12 dB，隔离度大于42 dB，核心芯片面积仅为0.62 mm2。
{"title":"A Broadband and Compact GaN Millimeter-Wave MMIC SPDT Switch Using Modified π-Networks","authors":"Chaorong Wang;Quan Pan;Xiaohu Fang","doi":"10.1109/LSSC.2025.3646815","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3646815","url":null,"abstract":"This letter presents a design methodology for broadband and compact millimeter-wave (mm-wave) single-pole double-throw (SPDT) switches targeting the Ku–Ka band. Conventional SPDT switches based on quarter-wavelength transmission line typically occupy significant chip area, while alternative designs utilizing standard <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-type equivalent circuits often suffer from bandwidth degradation due to the parasitic inductance at the isolation path. To overcome these limitations, a novel SPDT architecture based on modified <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-networks is proposed. This approach incorporates the parasitic inductance of the isolation path into the <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-network design, effectively enhancing the bandwidth performance without increasing circuit complexity. For validation, an SPDT switch was implemented using a 0.15-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m GaN MMIC process, covering the 10–28 GHz band. Measurement results confirm that the switch achieves an insertion loss below 2.1 dB, return loss better than 12 dB and isolation greater than 42 dB, with a compact core chip area of only 0.62 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"21-24"},"PeriodicalIF":2.0,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145886581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a broadband $G$ -band power amplifier (PA) designed in a 130-nm silicon-germanium (SiGe) bipolar complementary metal-oxide-semiconductor technology. Unlike dual-band matching and staggered tuning techniques to obtain large operation bandwidth (BW), we propose a common broadband amplification stage in this work for its flexibility. In each stage, inductive gain peaking is employed at the base terminal of the common-base (CB) transistor for BW extension. Meanwhile, the correlation between BW, inband gain and gain flatness is studied to determine the practical value of the inductance and AC decoupling capacitance. A current-mirror with thermal runaway protection is placed close to the amplifier in the implementation of each stage. The proposed PA achieves a peak small-signal gain of 27.6 dB over an operation BW from 140 to 238.7 GHz in measurements. The saturated output power, $P_{text {sat}}$ , is 8.5 dBm at 220 GHz with a peak power-added efficiency (PAE) of 2.1%. The 3-dB $P_{text {sat}}$ BW ranges from 150 to 220 GHz with fractional BW of 31.8% in measurements. To the best of the authors’ knowledge, the PA demonstrates the largest BW in $G$ -band compared to other reported silicon-based PAs to date. Furthermore, the inband gain and output power over BW are easily adjustable based on system requirements due to the flexibility of the common broadband amplification stage.
{"title":"220 GHz, 8.5-dBm Saturated Output Power Wideband Power Amplifier in SiGe BiCMOS","authors":"Xun Chen;Jonas Winkelhake;Muh-Dey Wei;Renato Negra","doi":"10.1109/LSSC.2025.3646267","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3646267","url":null,"abstract":"This letter presents a broadband <inline-formula> <tex-math>$G$ </tex-math></inline-formula>-band power amplifier (PA) designed in a 130-nm silicon-germanium (SiGe) bipolar complementary metal-oxide-semiconductor technology. Unlike dual-band matching and staggered tuning techniques to obtain large operation bandwidth (BW), we propose a common broadband amplification stage in this work for its flexibility. In each stage, inductive gain peaking is employed at the base terminal of the common-base (CB) transistor for BW extension. Meanwhile, the correlation between BW, inband gain and gain flatness is studied to determine the practical value of the inductance and AC decoupling capacitance. A current-mirror with thermal runaway protection is placed close to the amplifier in the implementation of each stage. The proposed PA achieves a peak small-signal gain of 27.6 dB over an operation BW from 140 to 238.7 GHz in measurements. The saturated output power, <inline-formula> <tex-math>$P_{text {sat}}$ </tex-math></inline-formula>, is 8.5 dBm at 220 GHz with a peak power-added efficiency (PAE) of 2.1%. The 3-dB <inline-formula> <tex-math>$P_{text {sat}}$ </tex-math></inline-formula> BW ranges from 150 to 220 GHz with fractional BW of 31.8% in measurements. To the best of the authors’ knowledge, the PA demonstrates the largest BW in <inline-formula> <tex-math>$G$ </tex-math></inline-formula>-band compared to other reported silicon-based PAs to date. Furthermore, the inband gain and output power over BW are easily adjustable based on system requirements due to the flexibility of the common broadband amplification stage.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"17-20"},"PeriodicalIF":2.0,"publicationDate":"2025-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11304730","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145886577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Advances in integrated circuit (IC) technology have amplified the effects of process, voltage, and temperature (PVT) variations, particularly dynamic IR drop, which severely affects timing. Post-silicon IR drop monitoring circuits are lacking, forcing designers to reserve substantial static guard bands for worst-case scenarios, compromising energy efficiency. Inspired by biomimetics, this letter proposes an Actiniaria-shaped structure for distributed monitoring of multiple IR drop hotspots without invading critical paths (CPs). It comprises lightweight tentacles + central monitor. The tentacles use voltage-sensitive cells to sense the impact of IR drop on timing, while also supporting adaptive tuning for global variations. By using on-chip PVT sensors, Actiniaria tracks the timing characteristics of the longest CP in real time under PVT variations. A two-stage prewarning timing monitor captures timing margins and employs adaptive voltage/frequency scaling (AVFS) strategies to compress redundant guard bands. When applied to an open-source multicore RISC-V processor fabricated in 22-nm CMOS, Actiniaria achieves a 40.6% reduction in power consumption through noninvasive dynamic IR drop monitoring while having only 0.08% area overhead.
{"title":"Actiniaria: Distributed Dynamic-IR-Drop-Aware Timing Monitor for AVFS With Lightweight Tentacles","authors":"Junyi Qian;Lishuo Deng;Cai Li;Yizhi Ding;Weiwei Shan","doi":"10.1109/LSSC.2025.3645701","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3645701","url":null,"abstract":"Advances in integrated circuit (IC) technology have amplified the effects of process, voltage, and temperature (PVT) variations, particularly dynamic IR drop, which severely affects timing. Post-silicon IR drop monitoring circuits are lacking, forcing designers to reserve substantial static guard bands for worst-case scenarios, compromising energy efficiency. Inspired by biomimetics, this letter proposes an Actiniaria-shaped structure for distributed monitoring of multiple IR drop hotspots without invading critical paths (CPs). It comprises lightweight tentacles + central monitor. The tentacles use voltage-sensitive cells to sense the impact of IR drop on timing, while also supporting adaptive tuning for global variations. By using on-chip PVT sensors, Actiniaria tracks the timing characteristics of the longest CP in real time under PVT variations. A two-stage prewarning timing monitor captures timing margins and employs adaptive voltage/frequency scaling (AVFS) strategies to compress redundant guard bands. When applied to an open-source multicore RISC-V processor fabricated in 22-nm CMOS, Actiniaria achieves a 40.6% reduction in power consumption through noninvasive dynamic IR drop monitoring while having only 0.08% area overhead.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"25-28"},"PeriodicalIF":2.0,"publicationDate":"2025-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-03DOI: 10.1109/LSSC.2025.3640522
Vaidehi Garg;Jianwei Jia;Omkar Phadke;Shimeng Yu
Compute-in-memory (CIM) using emerging nonvolatile memory devices is a promising candidate for energy-efficient deep neural network (DNN) inference at the edge. Ferroelectric field-effect transistors (FeFETs) have recently gained attention as nonvolatile, CMOS-compatible devices with a higher on/off ratio and lower read and write energy compared to resistive random-access memory (RRAM). This work demonstrates a 4-kb FeFET-CIM macro fabricated in the GlobalFoundries 28-nm high-k metal gate (HKMG) process. The macro consists of a $64times 64$ FeFET array with peripheral circuits for program, erase, and current-mode CIM operations and eight 4-bit Flash ADCs to quantize the analog partial sums. The proposed design achieves an energy efficiency of 346.6 TOPS/W for $1times 1$ b MAC, an inference accuracy of 85.2% for 16 row parallel compute with 4-bit ADC resolution, and 89.1% with 8 row parallel compute with 3-bit resolution, compared to a software baseline of 89.7% on the VGG-8 model for CIFAR-10.
{"title":"A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC","authors":"Vaidehi Garg;Jianwei Jia;Omkar Phadke;Shimeng Yu","doi":"10.1109/LSSC.2025.3640522","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3640522","url":null,"abstract":"Compute-in-memory (CIM) using emerging nonvolatile memory devices is a promising candidate for energy-efficient deep neural network (DNN) inference at the edge. Ferroelectric field-effect transistors (FeFETs) have recently gained attention as nonvolatile, CMOS-compatible devices with a higher on/off ratio and lower read and write energy compared to resistive random-access memory (RRAM). This work demonstrates a 4-kb FeFET-CIM macro fabricated in the GlobalFoundries 28-nm high-k metal gate (HKMG) process. The macro consists of a <inline-formula> <tex-math>$64times 64$ </tex-math></inline-formula> FeFET array with peripheral circuits for program, erase, and current-mode CIM operations and eight 4-bit Flash ADCs to quantize the analog partial sums. The proposed design achieves an energy efficiency of 346.6 TOPS/W for <inline-formula> <tex-math>$1times 1$ </tex-math></inline-formula>b MAC, an inference accuracy of 85.2% for 16 row parallel compute with 4-bit ADC resolution, and 89.1% with 8 row parallel compute with 3-bit resolution, compared to a software baseline of 89.7% on the VGG-8 model for CIFAR-10.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"13-16"},"PeriodicalIF":2.0,"publicationDate":"2025-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145729364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a 14-bit 500-MS/s 3-stage pipelined successive approximation register (SAR) analog-to-digital converter (ADC). By exploiting robust 2b/cycle SAR ADCs, this ADC incorporates significant voltage and time redundancy. High SFDR is achieved through several linearity enhancement techniques. First, a DAC splitting technique addresses the common-mode voltage matching problem between the input buffer and the sampling circuit. Second, a reference charge neutralization minimizes reference ripple. Finally, a digital harmonic correction is realized with a low-cost and low-latency LUT. Fabricated in a 28-nm CMOS process, the prototype ADC achieves 64.6-dB SNDR and 82.6-dB SFDR at Nyquist.
这封信提出了一个14位500毫秒/秒3级流水线逐次逼近寄存器（SAR）模数转换器（ADC）。通过利用强大的2b/周期SAR ADC，该ADC具有显著的电压和时间冗余。高SFDR是通过几种线性增强技术实现的。首先，DAC分裂技术解决了输入缓冲器和采样电路之间的共模电压匹配问题。其次，参考电荷中和使参考纹波最小化。最后，利用低成本、低延迟的LUT实现了数字谐波校正。原型ADC采用28纳米CMOS工艺制造，在Nyquist实现了64.6 db SNDR和82.6 db SFDR。
{"title":"A 500 MS/s Robust 2b/cycle Pipelined-SAR ADC Achieving 64.6-dB SNDR and 82.6-dB SFDR With Linearity Enhancement Techniques","authors":"Qiang Yu;Zheng Zhu;Lulu Zhang;Qin Huang;Yao Feng;Chao Liang;Biao Hu;Ling Du;Rongbin Yang;Shuangyi Wu;Qiang Li","doi":"10.1109/LSSC.2025.3639322","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3639322","url":null,"abstract":"This letter presents a 14-bit 500-MS/s 3-stage pipelined successive approximation register (SAR) analog-to-digital converter (ADC). By exploiting robust 2b/cycle SAR ADCs, this ADC incorporates significant voltage and time redundancy. High SFDR is achieved through several linearity enhancement techniques. First, a DAC splitting technique addresses the common-mode voltage matching problem between the input buffer and the sampling circuit. Second, a reference charge neutralization minimizes reference ripple. Finally, a digital harmonic correction is realized with a low-cost and low-latency LUT. Fabricated in a 28-nm CMOS process, the prototype ADC achieves 64.6-dB SNDR and 82.6-dB SFDR at Nyquist.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"9-12"},"PeriodicalIF":2.0,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145729381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01DOI: 10.1109/LSSC.2025.3639178
Yuyao Kong;Haomei Liu;Vaidehi Garg;Shimeng Yu
This work presents a compact digital compute-in-memory (DCIM) Ising annealer targeting large-scale combinatorial optimization. A centroid-based weight mapping method combined with hierarchical clustering reduces the memory capacity required for traveling salesman problem (TSP) weights, enabling efficient mapping with limited on-chip storage. An asynchronous random number generator (ARNG) based on dual ring oscillator provides high-quality randomness with tunable probability bias while incurring much smaller hardware overhead than conventional linear feedback shift registers (LFSRs). The proposed architecture was fabricated in 28-nm CMOS, integrating a DCIM array and an on-chip asynchronous-clock-based random number generator (ARNG). Measurement results demonstrate annealing on TSP problems up to 3038 cities. Compared to LFSR-based randomness, the ARNG achieves solution quality closer to the software baseline while maintaining compact area. This design highlights a scalable and energy-efficient hardware framework for Ising-based optimization, showing clear advantages in both memory efficiency and random source quality over prior approaches.
{"title":"A 28-nm Digital Compute-in-Memory Ising Annealer With Asynchronous Random Number Generator for Traveling Salesman Problem","authors":"Yuyao Kong;Haomei Liu;Vaidehi Garg;Shimeng Yu","doi":"10.1109/LSSC.2025.3639178","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3639178","url":null,"abstract":"This work presents a compact digital compute-in-memory (DCIM) Ising annealer targeting large-scale combinatorial optimization. A centroid-based weight mapping method combined with hierarchical clustering reduces the memory capacity required for traveling salesman problem (TSP) weights, enabling efficient mapping with limited on-chip storage. An asynchronous random number generator (ARNG) based on dual ring oscillator provides high-quality randomness with tunable probability bias while incurring much smaller hardware overhead than conventional linear feedback shift registers (LFSRs). The proposed architecture was fabricated in 28-nm CMOS, integrating a DCIM array and an on-chip asynchronous-clock-based random number generator (ARNG). Measurement results demonstrate annealing on TSP problems up to 3038 cities. Compared to LFSR-based randomness, the ARNG achieves solution quality closer to the software baseline while maintaining compact area. This design highlights a scalable and energy-efficient hardware framework for Ising-based optimization, showing clear advantages in both memory efficiency and random source quality over prior approaches.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"1-4"},"PeriodicalIF":2.0,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145705914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：