Analog computing in memory (CIM) based on resistive nonvolatile memory (NVM) has encountered several issues, such as low parallelism, low computing accuracy, and considerable power consumption. In this letter, a temporal unit based on design technology co-optimization (DTCO) for resistive random access memory is proposed for the first time, with the advantage of eliminating dc current and reducing the deviation of mapped weight. A time-domain (TD) array based on the proposed temporal unit features performing fully parallel matrix-vector multiplication (MVM) in a static-power-free manner, without the consideration of IR drop and limited sensing margin (SM). Besides, a low-power time-digital converter (TDC) with local offset elimination further boosts energy efficiency (EF) and computing accuracy. The fabricated 28-nm TD CIM macro achieves a state-of-the-art normalized EF of 1982 and 1387 TOPS/W/bit under 1b-input, ternary-weight and 4b-input, signed 4b-weight, respectively.
{"title":"A 28-nm Static-Power-Free Fully Parallel RRAM-Based TD CIM Macro With 1982 TOPS/W/Bit for Edge Applications","authors":"Songtao Wei;Peng Yao;Xinying Guo;Dong Wu;Lu Jie;Qi Qin;Bin Gao;Jianshi Tang;He Qian;Sining Pan;Huaqiang Wu","doi":"10.1109/LSSC.2024.3520593","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3520593","url":null,"abstract":"Analog computing in memory (CIM) based on resistive nonvolatile memory (NVM) has encountered several issues, such as low parallelism, low computing accuracy, and considerable power consumption. In this letter, a temporal unit based on design technology co-optimization (DTCO) for resistive random access memory is proposed for the first time, with the advantage of eliminating dc current and reducing the deviation of mapped weight. A time-domain (TD) array based on the proposed temporal unit features performing fully parallel matrix-vector multiplication (MVM) in a static-power-free manner, without the consideration of IR drop and limited sensing margin (SM). Besides, a low-power time-digital converter (TDC) with local offset elimination further boosts energy efficiency (EF) and computing accuracy. The fabricated 28-nm TD CIM macro achieves a state-of-the-art normalized EF of 1982 and 1387 TOPS/W/bit under 1b-input, ternary-weight and 4b-input, signed 4b-weight, respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"21-24"},"PeriodicalIF":2.2,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-19DOI: 10.1109/LSSC.2024.3520338
Christoph Gasser;Christoph Ribisch;Simon Michael Laube;Kerstin Schneider-Hornstein;Horst Zimmermann
This work presents a novel ultrasensitive integrator-based optical frontend that eliminates the need for a reset network to stabilize the operating point. The proposed method introduces a current source at the input node that compensates the average photocurrent. Eliminating the reset phase for the integrator results in better data rate scalability and PVT robustness without the need for correlated double sampling. The full-custom designed PIN-diode receiver was fabricated in 0.35 $mu $ m CMOS and characterized. Using a Manchester encoded PRBS15 bit stream, the best sample achieved a sensitivity of $mathbf {-52.93}$ dBm at a wavelength of 642nm, an effective data rate of 50Mb/s and a bit error ratio of $mathbf {2cdot 10^{-3}}$ . This results in a distance of 20.75 dB to the quantum limit.
{"title":"Ultrasensitive Reset-Less Integrator-Based PIN-Diode Receiver With Input Current Control","authors":"Christoph Gasser;Christoph Ribisch;Simon Michael Laube;Kerstin Schneider-Hornstein;Horst Zimmermann","doi":"10.1109/LSSC.2024.3520338","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3520338","url":null,"abstract":"This work presents a novel ultrasensitive integrator-based optical frontend that eliminates the need for a reset network to stabilize the operating point. The proposed method introduces a current source at the input node that compensates the average photocurrent. Eliminating the reset phase for the integrator results in better data rate scalability and PVT robustness without the need for correlated double sampling. The full-custom designed PIN-diode receiver was fabricated in 0.35\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS and characterized. Using a Manchester encoded PRBS15 bit stream, the best sample achieved a sensitivity of \u0000<inline-formula> <tex-math>$mathbf {-52.93}$ </tex-math></inline-formula>\u0000dBm at a wavelength of 642nm, an effective data rate of 50Mb/s and a bit error ratio of \u0000<inline-formula> <tex-math>$mathbf {2cdot 10^{-3}}$ </tex-math></inline-formula>\u0000. This results in a distance of 20.75 dB to the quantum limit.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"17-20"},"PeriodicalIF":2.2,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10807184","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Most analog compute-in-memory (ACiM) works only focus on the multiple–accumulate (MAC) operation while neglecting the activation function (AF) in the digital domain. The frequent data conversion greatly reduces the benefits obtained by analog computing. This letter proposes an efficient 8-bit in-memory MAC with hybrid capacitor ladders. Then, a sparsity-aware R-2R DAC and an embedded SAR-ADC that reuses the capacitor ladders in the MAC are introduced to reduce the conversion overhead. Two on-chip AF schemes are included to further improve efficiency. Finally, differential signal path offers first-order PVT cancellation that improves computing accuracy and reduces the need for calibration.
{"title":"Enhancing AI Acceleration: A Calibration-Free, PVT-Robust Analog Compute-in-Memory Macro With Activation Functions","authors":"Hechen Wang;Renzhi Liu;Richard Dorrance;Deepak Dasalukunte;Niranjan Mylarappa Gowda;Brent Carlton","doi":"10.1109/LSSC.2024.3510679","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3510679","url":null,"abstract":"Most analog compute-in-memory (ACiM) works only focus on the multiple–accumulate (MAC) operation while neglecting the activation function (AF) in the digital domain. The frequent data conversion greatly reduces the benefits obtained by analog computing. This letter proposes an efficient 8-bit in-memory MAC with hybrid capacitor ladders. Then, a sparsity-aware R-2R DAC and an embedded SAR-ADC that reuses the capacitor ladders in the MAC are introduced to reduce the conversion overhead. Two on-chip AF schemes are included to further improve efficiency. Finally, differential signal path offers first-order PVT cancellation that improves computing accuracy and reduces the need for calibration.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"9-12"},"PeriodicalIF":2.2,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142858877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/LSSC.2024.3511582
Wenyu Zhou;Larry Tarof;Rony E. Amaya
A monolithically integrated optical receiver in InP for 10-Gb/s intensity modulation direct detect (IMDD) application is presented. The sensitivity at the bit error rate (BER) $rm 10^{-3}$ is measured to be –27.1 dBm. An integrated PIN diode photodetector (PD) minimizes the parasitics caused by wire bonds between the PD and the transimpedance amplifier (TIA). For the first time, electronics and photonics are monolithically integrated into a single InP IC. The avalanche photodetector (APD) is replaced with PIN PD, exhibiting comparable sensitivity and requiring a simple 3.3-V supply voltage. A single transistor voltage-to-current convertor between two cascaded TIAs performs automatic gain control (AGC). A total dynamic gain control of 9 dB has been demonstrated with a dynamic range of more than 17 dB, employing only four transistors and dissipating 8.5 mW. Improved gain peaking extends the operating bandwidth and makes it suitable for higher-speed applications. The power supply rejection ratio (PSRR) exceeds 24 dB without needing on-chip bandgap references.
{"title":"A 10-Gb/s Optical Receiver With Monolithically Integrated PIN Photodiode, Novel AGC, and Sensitivity of –27.1 dBm for BER 10-3","authors":"Wenyu Zhou;Larry Tarof;Rony E. Amaya","doi":"10.1109/LSSC.2024.3511582","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3511582","url":null,"abstract":"A monolithically integrated optical receiver in InP for 10-Gb/s intensity modulation direct detect (IMDD) application is presented. The sensitivity at the bit error rate (BER) \u0000<inline-formula> <tex-math>$rm 10^{-3}$ </tex-math></inline-formula>\u0000 is measured to be –27.1 dBm. An integrated PIN diode photodetector (PD) minimizes the parasitics caused by wire bonds between the PD and the transimpedance amplifier (TIA). For the first time, electronics and photonics are monolithically integrated into a single InP IC. The avalanche photodetector (APD) is replaced with PIN PD, exhibiting comparable sensitivity and requiring a simple 3.3-V supply voltage. A single transistor voltage-to-current convertor between two cascaded TIAs performs automatic gain control (AGC). A total dynamic gain control of 9 dB has been demonstrated with a dynamic range of more than 17 dB, employing only four transistors and dissipating 8.5 mW. Improved gain peaking extends the operating bandwidth and makes it suitable for higher-speed applications. The power supply rejection ratio (PSRR) exceeds 24 dB without needing on-chip bandgap references.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"13-16"},"PeriodicalIF":2.2,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778277","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142858878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-02DOI: 10.1109/LSSC.2024.3510597
Po-Jui Chiu;Chi-Yu Chen;Xiao-Quan Wu;Yu-Ting Huang;Tz-Wun Wang;Sheng-Hsi Hung;Ke-Horng Chen;Kuo-Lin Zheng;Chih-Chen Li
The proposed gallium nitride (GaN)-based voltage reference ( $V_{mathrm { REF}}$ ) generator has a low temperature coefficient (TC) of 15.4 ppm/°C, small $V_{mathrm { REF}}$ deviation at different process corners (standard deviation of 0.22%), line sensitivity as low as 0.0023%/V, and high power supply rejection (PSR) of −187 and −114 dB at 100 Hz and 50 MHz, respectively. The proportional-to-absolute-temperature (PTAT) gate current for enhancement-mode GaN (eGaN) optimizes TC. Eliminating depletion-mode GaN (dGaN) gate leakage and using multiple stacked composite dGaNs can improve line regulation and PSR. All performance is achieved with a low power consumption of $10.9~mu $ W.
{"title":"A 15.4-ppm/°C GaN-Based Voltage Reference With Process-Variation-Immunity and High PSR for Electric Vehicle Power Systems","authors":"Po-Jui Chiu;Chi-Yu Chen;Xiao-Quan Wu;Yu-Ting Huang;Tz-Wun Wang;Sheng-Hsi Hung;Ke-Horng Chen;Kuo-Lin Zheng;Chih-Chen Li","doi":"10.1109/LSSC.2024.3510597","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3510597","url":null,"abstract":"The proposed gallium nitride (GaN)-based voltage reference (\u0000<inline-formula> <tex-math>$V_{mathrm { REF}}$ </tex-math></inline-formula>\u0000) generator has a low temperature coefficient (TC) of 15.4 ppm/°C, small \u0000<inline-formula> <tex-math>$V_{mathrm { REF}}$ </tex-math></inline-formula>\u0000 deviation at different process corners (standard deviation of 0.22%), line sensitivity as low as 0.0023%/V, and high power supply rejection (PSR) of −187 and −114 dB at 100 Hz and 50 MHz, respectively. The proportional-to-absolute-temperature (PTAT) gate current for enhancement-mode GaN (eGaN) optimizes TC. Eliminating depletion-mode GaN (dGaN) gate leakage and using multiple stacked composite dGaNs can improve line regulation and PSR. All performance is achieved with a low power consumption of \u0000<inline-formula> <tex-math>$10.9~mu $ </tex-math></inline-formula>\u0000W.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"359-362"},"PeriodicalIF":2.2,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a hybrid, three-step zoom-linear-exponential incremental analog-to-digital converter (ZLE-IADC) for audio applications. The zoom-SAR in the first step provides coarse signal quantization and relaxes the accuracy requirements of subsequent conversions. The second step utilizes a single-loop, first-order delta–sigma modulator ( $Delta Sigma $ M). In the third step, the $Delta Sigma $ M is reconfigured as an exponential counting loop with split positive feedback (SPF). The SPF isolates the loop integrator from the residue sampling network, thereby improving the settling time of the residue amplifier (RA) under the transient switching of linear-exponential loads. Besides, a duty-cycle RA further reduces its average power from 48.4% to 6.1% of the IADC. Last, the zoom-SAR in the first step is reconfigured as a gain-embedded quantizer (GEQ) in the third step, optimizing the hardware cost. Fabricated in a standard 180-nm CMOS technology, the proposed IADC achieves a dynamic range (DR) of 103.9 dB and a signal-to-noise-and-distortion ratio (SNDR) of 100.9 dB, which corresponds to a state-of-the-art Schreier ${mathrm { FoM}}_{mathrm { S,{mathrm {DR}}}}$ of 177.7 dB.
本文介绍了一种用于音频应用的混合三步变焦线性指数增量模数转换器（ZLE-IADC）。第一步的变焦sar提供了粗信号量化，放宽了后续转换的精度要求。第二步采用单回路一阶delta-sigma调制器（$Delta Sigma $ M）。在第三步中，$Delta Sigma $ M被重新配置为具有分裂正反馈（SPF）的指数计数环路。SPF隔离环路积分器和残差采样网络，从而提高了残差放大器（RA）在线性指数负载瞬态切换下的稳定时间。此外，占空比RA进一步降低了其平均功率48.4% to 6.1% of the IADC. Last, the zoom-SAR in the first step is reconfigured as a gain-embedded quantizer (GEQ) in the third step, optimizing the hardware cost. Fabricated in a standard 180-nm CMOS technology, the proposed IADC achieves a dynamic range (DR) of 103.9 dB and a signal-to-noise-and-distortion ratio (SNDR) of 100.9 dB, which corresponds to a state-of-the-art Schreier ${mathrm { FoM}}_{mathrm { S,{mathrm {DR}}}}$ of 177.7 dB.
{"title":"An 828-μW 100.9-dB SNDR 20-kHz BW Zoom-Linear-Exponential Incremental ADC With Split Positive Feedback and Duty-Cycle Amplifier","authors":"Lairong Fang;Shuwen Zhang;Xiaoyang Zeng;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2024.3510423","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3510423","url":null,"abstract":"This letter presents a hybrid, three-step zoom-linear-exponential incremental analog-to-digital converter (ZLE-IADC) for audio applications. The zoom-SAR in the first step provides coarse signal quantization and relaxes the accuracy requirements of subsequent conversions. The second step utilizes a single-loop, first-order delta–sigma modulator (\u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000M). In the third step, the \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000M is reconfigured as an exponential counting loop with split positive feedback (SPF). The SPF isolates the loop integrator from the residue sampling network, thereby improving the settling time of the residue amplifier (RA) under the transient switching of linear-exponential loads. Besides, a duty-cycle RA further reduces its average power from 48.4% to 6.1% of the IADC. Last, the zoom-SAR in the first step is reconfigured as a gain-embedded quantizer (GEQ) in the third step, optimizing the hardware cost. Fabricated in a standard 180-nm CMOS technology, the proposed IADC achieves a dynamic range (DR) of 103.9 dB and a signal-to-noise-and-distortion ratio (SNDR) of 100.9 dB, which corresponds to a state-of-the-art Schreier \u0000<inline-formula> <tex-math>${mathrm { FoM}}_{mathrm { S,{mathrm {DR}}}}$ </tex-math></inline-formula>\u0000 of 177.7 dB.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"1-4"},"PeriodicalIF":2.2,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142858876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A high-speed and power-efficient CMOS integration dynamic comparator is presented. Low-input-referred noise is accomplished by CMOS integration. To achieve low-power consumption, a charge-reusing scheme by flipping the flying capacitors across the pMOS/nMOS integration nodes is introduced. The 22-nm prototype achieves a 0.22- $mu $ Vrms input-referred noise with an energy consumption of 227-fJ per conversion, which is improved by $2times $ compared with the StrongARM counterpart in the same process. Furthermore, with the latch stage embedded, the achieved 0.41-ns CLK-OUT delay shows an over $20times $ improvement compared with the existing works with CMOS integration.
{"title":"A 0.41-ns CLK-OUT Delay, 0.22-μVrms Input-Referred Noise CMOS Integration Dynamic Comparator With Flipping Capacitor for Charge Reuse","authors":"Kwok Cheong Li;Xinhang Xu;Jihang Gao;Siyuan Ye;Jiajia Cui;Yacong Zhang;Ru Huang;Linxiao Shen","doi":"10.1109/LSSC.2024.3510389","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3510389","url":null,"abstract":"A high-speed and power-efficient CMOS integration dynamic comparator is presented. Low-input-referred noise is accomplished by CMOS integration. To achieve low-power consumption, a charge-reusing scheme by flipping the flying capacitors across the pMOS/nMOS integration nodes is introduced. The 22-nm prototype achieves a 0.22-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000Vrms input-referred noise with an energy consumption of 227-fJ per conversion, which is improved by \u0000<inline-formula> <tex-math>$2times $ </tex-math></inline-formula>\u0000 compared with the StrongARM counterpart in the same process. Furthermore, with the latch stage embedded, the achieved 0.41-ns CLK-OUT delay shows an over \u0000<inline-formula> <tex-math>$20times $ </tex-math></inline-formula>\u0000 improvement compared with the existing works with CMOS integration.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"5-8"},"PeriodicalIF":2.2,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-29DOI: 10.1109/LSSC.2024.3509378
John Zhong;Konstantinos Vasilakopoulos;Antonio Liscidini
This letter presents a multichannel quantized analog transmitter to maintain the spectral purity of the analog systems while offering radio-frequency digital-to-analog converter flexibility. Consuming 275 mW power, it achieves an EVM of better than −35 dB with an ACLR1/2 of −51/−54 dBc for a 15 MHz 64-QAM signal at 9.4-dBm output power.
{"title":"A Reconfigurable, Multichannel Quantized-Analog Transmitter With <-35 dB EVM and <-51 dBc ACLR in 22-nm FDSOI","authors":"John Zhong;Konstantinos Vasilakopoulos;Antonio Liscidini","doi":"10.1109/LSSC.2024.3509378","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3509378","url":null,"abstract":"This letter presents a multichannel quantized analog transmitter to maintain the spectral purity of the analog systems while offering radio-frequency digital-to-analog converter flexibility. Consuming 275 mW power, it achieves an EVM of better than −35 dB with an ACLR1/2 of −51/−54 dBc for a 15 MHz 64-QAM signal at 9.4-dBm output power.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"355-358"},"PeriodicalIF":2.2,"publicationDate":"2024-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To simultaneously advance phase noise (PN) performance at a wide frequency-tuning range (FTR) while using the standard supply levels, this letter proposes a multistory multicore multimode oscillator topology based on the following ideas: 1) the N number of cores reduces the PN by $10 log (N)$ dB, and the circular geometry of inductors promotes their high-quality $(Q)$ -factors and compact layout; 2) the multiple stacked cores exploiting current reuse improve the figure of merit (FoM) using an nMOS-only oscillator configuration under a standard supply; and 3) the multiple modes expand the FTR by leveraging the interstory coupling with all oscillator cores turned on simultaneously, only occupying a single resonator’s footprint. A two-story quad-core dual-mode voltage-controlled oscillator (VCO) prototype is fabricated in 65-nm CMOS. Using a standard 1.2-V supply, it achieves PN of −111.3 to −106.2 dBc/Hz at 1-MHz offset over a 25.0–35.9-GHz FTR (35.8%), a 186.5–189.1-dBc/Hz FoM, and a 197.6–200.2-dBc/Hz $rm {FoM}_{T}$ (i.e., FoM with normalized FTR).
{"title":"A Two-Story Quad-Core Dual-Mode VCO in 65-nm CMOS","authors":"Pingda Guan;Haikun Jia;Wei Deng;Ruichang Ma;Huabing Liao;Teerachot Siriburanon;Robert Bogdan Staszewski;Zhihua Wang;Baoyong Chi","doi":"10.1109/LSSC.2024.3506672","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3506672","url":null,"abstract":"To simultaneously advance phase noise (PN) performance at a wide frequency-tuning range (FTR) while using the standard supply levels, this letter proposes a multistory multicore multimode oscillator topology based on the following ideas: 1) the N number of cores reduces the PN by \u0000<inline-formula> <tex-math>$10 log (N)$ </tex-math></inline-formula>\u0000 dB, and the circular geometry of inductors promotes their high-quality \u0000<inline-formula> <tex-math>$(Q)$ </tex-math></inline-formula>\u0000-factors and compact layout; 2) the multiple stacked cores exploiting current reuse improve the figure of merit (FoM) using an nMOS-only oscillator configuration under a standard supply; and 3) the multiple modes expand the FTR by leveraging the interstory coupling with all oscillator cores turned on simultaneously, only occupying a single resonator’s footprint. A two-story quad-core dual-mode voltage-controlled oscillator (VCO) prototype is fabricated in 65-nm CMOS. Using a standard 1.2-V supply, it achieves PN of −111.3 to −106.2 dBc/Hz at 1-MHz offset over a 25.0–35.9-GHz FTR (35.8%), a 186.5–189.1-dBc/Hz FoM, and a 197.6–200.2-dBc/Hz \u0000<inline-formula> <tex-math>$rm {FoM}_{T}$ </tex-math></inline-formula>\u0000 (i.e., FoM with normalized FTR).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"363-366"},"PeriodicalIF":2.2,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Subharmonic pulse injection crystal oscillators enable sub-nW operation with less frequent energy injection at oscillation peaks and valleys. However, this poses stringent requirements on the injection accuracy, which affects operation power, jitter, and reliability. To ensure accurate valley and peak injection across a wide temperature at minimum overhead, this work proposes the zero-voltage detection (ZVD)-based closed-loop timing adaptation, unbalanced differential injection and oscillation DC stabilizing techniques for a single-supply 16th subharmonic pulse-injection-based crystal oscillator (XO). Fabricated in 22-nm FDSOI, the IC enables operation across the widest reported temperature range from $-40~^{circ }$ C to $125~^{circ }$ C, and achieves a 11 ppb Allan deviation floor while consuming 0.72 nW and 0.006 mm2.
{"title":"An Adaptive Subharmonic Pulse Injection Crystal Oscillator Achieving —40 ∘C to 125 ∘C Operation","authors":"Yingjie Zhu;Yiqing Lan;Humiao Li;Haoran Lyu;Zhen Kong;Jian Zhao;Yida Li;Guoxing Wang;Jiamin Li;Longyang Lin","doi":"10.1109/LSSC.2024.3503615","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3503615","url":null,"abstract":"Subharmonic pulse injection crystal oscillators enable sub-nW operation with less frequent energy injection at oscillation peaks and valleys. However, this poses stringent requirements on the injection accuracy, which affects operation power, jitter, and reliability. To ensure accurate valley and peak injection across a wide temperature at minimum overhead, this work proposes the zero-voltage detection (ZVD)-based closed-loop timing adaptation, unbalanced differential injection and oscillation DC stabilizing techniques for a single-supply 16th subharmonic pulse-injection-based crystal oscillator (XO). Fabricated in 22-nm FDSOI, the IC enables operation across the widest reported temperature range from \u0000<inline-formula> <tex-math>$-40~^{circ }$ </tex-math></inline-formula>\u0000C to \u0000<inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>\u0000C, and achieves a 11 ppb Allan deviation floor while consuming 0.72 nW and 0.006 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"351-354"},"PeriodicalIF":2.2,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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