Pub Date : 2024-09-11DOI: 10.1109/LSSC.2024.3457768
Ido Shpernat;Asaf Feldman;Joseph Shor
A new architecture of an on-die process monitor circuit is demonstrated in 28 nm. The proposed circuit can extract the threshold voltage, $V_{mathrm { TH,}}$ and random mismatch of a transistor using multiple extraction methods, including the second derivative method. A sigma-delta modulator analog-to-digital converter samples the output to enable on-die processing of the results. A $V_{mathrm { DS}}$ voltage control loop enables $V_{mathrm { TH}}$ extraction in both the linear and saturation regions of the device. The circuit has a compact area of $5510~mu $ m2.
{"title":"A Fully Integrated 5510-μm² Process Monitor and Threshold Voltage Extractor Circuit in 28 nm","authors":"Ido Shpernat;Asaf Feldman;Joseph Shor","doi":"10.1109/LSSC.2024.3457768","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3457768","url":null,"abstract":"A new architecture of an on-die process monitor circuit is demonstrated in 28 nm. The proposed circuit can extract the threshold voltage, \u0000<inline-formula> <tex-math>$V_{mathrm { TH,}}$ </tex-math></inline-formula>\u0000 and random mismatch of a transistor using multiple extraction methods, including the second derivative method. A sigma-delta modulator analog-to-digital converter samples the output to enable on-die processing of the results. A \u0000<inline-formula> <tex-math>$V_{mathrm { DS}}$ </tex-math></inline-formula>\u0000 voltage control loop enables \u0000<inline-formula> <tex-math>$V_{mathrm { TH}}$ </tex-math></inline-formula>\u0000 extraction in both the linear and saturation regions of the device. The circuit has a compact area of \u0000<inline-formula> <tex-math>$5510~mu $ </tex-math></inline-formula>\u0000m2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142438622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-10DOI: 10.1109/LSSC.2024.3457272
Suyang Song;Alessandro Novello;Taekwang Jang
This letter presents recent design challenges of modern power delivery architectures and circuit techniques for them. Recent computational loads impose significant power output demands on dc-dc converters while ever-shrinking Internet of Things (IoT) systems demand dc-dc converters with small footprints. Consequently, fully integrated dc-dc converters are highly desirable in contemporary power delivery architectures thanks to their compact footprint, high power density, and fast output regulation. However, numerous challenges exist in fully integrating dc-dc converters, necessitating the investigation of various circuit topologies and complex regulation schemes to ensure proper operation and versatility.
{"title":"Design Challenges of Fully Integrated DC–DC Converters for Modern Power Delivery Architectures","authors":"Suyang Song;Alessandro Novello;Taekwang Jang","doi":"10.1109/LSSC.2024.3457272","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3457272","url":null,"abstract":"This letter presents recent design challenges of modern power delivery architectures and circuit techniques for them. Recent computational loads impose significant power output demands on dc-dc converters while ever-shrinking Internet of Things (IoT) systems demand dc-dc converters with small footprints. Consequently, fully integrated dc-dc converters are highly desirable in contemporary power delivery architectures thanks to their compact footprint, high power density, and fast output regulation. However, numerous challenges exist in fully integrating dc-dc converters, necessitating the investigation of various circuit topologies and complex regulation schemes to ensure proper operation and versatility.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142328412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a D-band low-noise amplifier (LNA) for joint radar-communication applications in 22-nm CMOS technology. The 4-stage LNA uses transistor switching and bias class changes to achieve dual-mode functionality. In the radar mode, the LNA achieves gain of 17 dB, noise figure (NF) of 7.7 dB, 3-dB bandwidth (BW) of 117–129 GHz, and IP1dB of −20 dBm, respectively. In the communication mode, the LNA achieves gain of 22.6 dB, NF of 8.5 dB, BW of 115.9–128.9 GHz, and IP1dB of −29 dBm, respectively. The power consumption for the radar and communication modes is 13 and 12.2 mW, respectively. The LNA has a core area of $0.06~text {mm}^{2}$ .
{"title":"A D-Band 13-mW Dual-Mode CMOS LNA for Joint Radar–Communication in 22-nm FD-SOI CMOS","authors":"Shankkar Balasubramanian;Kristof Vaesen;Anirudh Kankuppe;Sehoon Park;Carsten Wulff","doi":"10.1109/LSSC.2024.3455889","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3455889","url":null,"abstract":"This letter presents a D-band low-noise amplifier (LNA) for joint radar-communication applications in 22-nm CMOS technology. The 4-stage LNA uses transistor switching and bias class changes to achieve dual-mode functionality. In the radar mode, the LNA achieves gain of 17 dB, noise figure (NF) of 7.7 dB, 3-dB bandwidth (BW) of 117–129 GHz, and IP1dB of −20 dBm, respectively. In the communication mode, the LNA achieves gain of 22.6 dB, NF of 8.5 dB, BW of 115.9–128.9 GHz, and IP1dB of −29 dBm, respectively. The power consumption for the radar and communication modes is 13 and 12.2 mW, respectively. The LNA has a core area of \u0000<inline-formula> <tex-math>$0.06~text {mm}^{2}$ </tex-math></inline-formula>\u0000.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10669787","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142276432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a receiver analog front-end (AFE) circuit specifically for photoacoustic (PA) imaging system. Due to the uncertain nature of the PA signal’s spectrum, this design is proposed featuring multiple bandwidth options that can self-adaptively adjust the loop bandwidth based on the received PA signals in different frequency bands, greatly reducing out-of-band noise and interference. The circuit includes a low-noise amplifier (LNA) and a low-pass filter (LPF), offering four bandwidth options. Frequency detection and bandwidth selection logic are implemented to achieve self-adaptive bandwidth adjustment. The chip is fabricated in a 0.18- $mu $ m CMOS process with variable gain settings and 4 bandwidth options, achieving 39.5 dB maximum gain, 4 MHz maximum bandwidth, minimum $3.47~mu $ Vrms input-referred noise and maximum 12.2 mW power consumption, specifically suitable for PA signal detection.
本文介绍了一种专门用于光声（PA）成像系统的接收器模拟前端（AFE）电路。由于 PA 信号频谱的不确定性，该设计具有多个带宽选项，可根据接收到的不同频段 PA 信号自适应调节环路带宽，从而大大降低带外噪声和干扰。电路包括一个低噪声放大器（LNA）和一个低通滤波器（LPF），提供四个带宽选项。通过频率检测和带宽选择逻辑来实现自适应带宽调整。该芯片采用 0.18- $mu $ m CMOS 工艺制造，具有可变增益设置和 4 个带宽选项，实现了 39.5 dB 最大增益、4 MHz 最大带宽、最小 3.47~mu $ Vrms 输入参考噪声和最大 12.2 mW 功耗，特别适合 PA 信号检测。
{"title":"A Self-Adaptively Bandwidth-Adjustable Receiver Analog Front-End for Sensitive Photoacoustic Signal Detection","authors":"Wei Fu;Wenshuo Zhu;Jiawei Liu;Luyao Zhu;Yi Li;Fei Gao;Yuan Gao","doi":"10.1109/LSSC.2024.3456374","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3456374","url":null,"abstract":"This letter presents a receiver analog front-end (AFE) circuit specifically for photoacoustic (PA) imaging system. Due to the uncertain nature of the PA signal’s spectrum, this design is proposed featuring multiple bandwidth options that can self-adaptively adjust the loop bandwidth based on the received PA signals in different frequency bands, greatly reducing out-of-band noise and interference. The circuit includes a low-noise amplifier (LNA) and a low-pass filter (LPF), offering four bandwidth options. Frequency detection and bandwidth selection logic are implemented to achieve self-adaptive bandwidth adjustment. The chip is fabricated in a 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS process with variable gain settings and 4 bandwidth options, achieving 39.5 dB maximum gain, 4 MHz maximum bandwidth, minimum \u0000<inline-formula> <tex-math>$3.47~mu $ </tex-math></inline-formula>\u0000Vrms input-referred noise and maximum 12.2 mW power consumption, specifically suitable for PA signal detection.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142276433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-30DOI: 10.1109/LSSC.2024.3452280
Jaewon Oh;Seonghwan Cho
This letter introduces a background quadrature phase and duty-cycle error corrector featuring a shared NAND-based phase detector and a differential voltage-controlled delay line, which are used to determine and compensate for the phase and duty-cycle errors of the quadrature signals. In contrast to prior quadrature phase error correctors that require 50% duty-cycle inputs, the proposed corrector can minimize errors in both quadrature phase and duty-cycle with a wide operating frequency, low jitter, and low power consumption. Implemented in 28-nm CMOS, the prototype operates over a frequency range of 1.15–11 GHz and achieves a quadrature phase error of less than 2.3° and a duty-cycle error of less than 0.8% for input phase error up to 80°. It consumes 2.1 mW and achieves a low RMS jitter of 21.6 fs at 5 GHz while occupying only 0.001 mm2.
{"title":"A 0.001-mm², 1.15–11-GHz Background Quadrature Phase and Duty-Cycle Error Corrector Using a NAND- Based Phase Detector in 28-nm CMOS","authors":"Jaewon Oh;Seonghwan Cho","doi":"10.1109/LSSC.2024.3452280","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3452280","url":null,"abstract":"This letter introduces a background quadrature phase and duty-cycle error corrector featuring a shared NAND-based phase detector and a differential voltage-controlled delay line, which are used to determine and compensate for the phase and duty-cycle errors of the quadrature signals. In contrast to prior quadrature phase error correctors that require 50% duty-cycle inputs, the proposed corrector can minimize errors in both quadrature phase and duty-cycle with a wide operating frequency, low jitter, and low power consumption. Implemented in 28-nm CMOS, the prototype operates over a frequency range of 1.15–11 GHz and achieves a quadrature phase error of less than 2.3° and a duty-cycle error of less than 0.8% for input phase error up to 80°. It consumes 2.1 mW and achieves a low RMS jitter of 21.6 fs at 5 GHz while occupying only 0.001 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142231967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-29DOI: 10.1109/LSSC.2024.3451966
Zhiyuan Cao;Xi Xiao;Ziyue Dang;Jin He
This letter demonstrates a low-noise linear transimpedance amplifier (TIA) for single-ended coherent optical receivers (ORXs) in 0.13- $mu $ m SiGe BiCMOS. The TIA achieves relatively low noise, excellent linearity, and approximately unchanged bandwidth (BW) within a wide gain dynamic range by employing a cascade structure of an improved shunt-feedback (SFB) high- $R_{F}$ TIA Core optimized for high linearity and a variable-gain single-to-differential (VG-S2D) circuit with adjustable peaking. The measured results of the TIA exhibit 42-GHz −3-dB BW at 74-dB $Omega $ maximum transimpedance gain $(Z_{T}) {_{,}}~37$ -dB gain dynamic range, 12.5-pA/ $sqrt {mathrm {(Hz)}}$ input reference noise (IRN) current density, and <3%> $2{^{{31}}} -1$ . The TIA draws 72-mA current from a 3.3-V voltage supply and takes up 1 mm2 of the chip area with all its testing pads.
{"title":"A Low-Noise Linear TIA With 42-GHz Bandwidth for Single-Ended Coherent Optical Receivers","authors":"Zhiyuan Cao;Xi Xiao;Ziyue Dang;Jin He","doi":"10.1109/LSSC.2024.3451966","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3451966","url":null,"abstract":"This letter demonstrates a low-noise linear transimpedance amplifier (TIA) for single-ended coherent optical receivers (ORXs) in 0.13-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m SiGe BiCMOS. The TIA achieves relatively low noise, excellent linearity, and approximately unchanged bandwidth (BW) within a wide gain dynamic range by employing a cascade structure of an improved shunt-feedback (SFB) high-\u0000<inline-formula> <tex-math>$R_{F}$ </tex-math></inline-formula>\u0000 TIA Core optimized for high linearity and a variable-gain single-to-differential (VG-S2D) circuit with adjustable peaking. The measured results of the TIA exhibit 42-GHz −3-dB BW at 74-dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 maximum transimpedance gain \u0000<inline-formula> <tex-math>$(Z_{T}) {_{,}}~37$ </tex-math></inline-formula>\u0000-dB gain dynamic range, 12.5-pA/\u0000<inline-formula> <tex-math>$sqrt {mathrm {(Hz)}}$ </tex-math></inline-formula>\u0000 input reference noise (IRN) current density, and <3%> <tex-math>$2{^{{31}}} -1$ </tex-math></inline-formula>\u0000. The TIA draws 72-mA current from a 3.3-V voltage supply and takes up 1 mm2 of the chip area with all its testing pads.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142165014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A $2048times 60$ m4 SRAM design in Intel 4 using PowerVia is presented. Instead of integrating PowerVia directly into bitcell, an around-the-array power-delivery scheme is introduced to limit the area increase of an SRAM bitcell array, while utilizing the benefits of PowerVias in logic peripheral circuits. The measured test chip demonstrates an improved or comparable $rm V_{MIN}$ and performance compared to similar nonPowerVia designs. An 8.3-Mb macro comprising of HCC bitcell-based $2048times 60$ m4 instance is 2% smaller than similar nonPowerVia design and shows a clean voltage-frequency Shmoo.
{"title":"A 2048×60m4 SRAM Design in Intel 4 With Around-the-Array Power Delivery Scheme Using PowerVia","authors":"Daeyeon Kim;Yusung Kim;Gyusung Park;Anandkumar Mahadevan Pillai;Kunal Bannore;Tri Doan;Muktadir Rahman;Gwanghyeon Baek;Xiaofei Wang;Zheng Guo;Eric Karl","doi":"10.1109/LSSC.2024.3443757","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3443757","url":null,"abstract":"A \u0000<inline-formula> <tex-math>$2048times 60$ </tex-math></inline-formula>\u0000 m4 SRAM design in Intel 4 using PowerVia is presented. Instead of integrating PowerVia directly into bitcell, an around-the-array power-delivery scheme is introduced to limit the area increase of an SRAM bitcell array, while utilizing the benefits of PowerVias in logic peripheral circuits. The measured test chip demonstrates an improved or comparable \u0000<inline-formula> <tex-math>$rm V_{MIN}$ </tex-math></inline-formula>\u0000 and performance compared to similar nonPowerVia designs. An 8.3-Mb macro comprising of HCC bitcell-based \u0000<inline-formula> <tex-math>$2048times 60$ </tex-math></inline-formula>\u0000 m4 instance is 2% smaller than similar nonPowerVia design and shows a clean voltage-frequency Shmoo.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142233074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-14DOI: 10.1109/LSSC.2024.3443744
Xiaoyu Lian;Eric Stang;Kangping Hu;Pradeep R. Guduru;Jacob K. Rosenstein
This letter presents a high-speed global-shutter thermal imaging system, with a $24^{V} times 24^{H} $ pixel HgCdTe infrared focal plane array (FPA) detector and a custom CMOS readout integrated circuit (ROIC), including a 768-frame on-chip analog burst memory bank. Each pixel contains a buffered current injection circuit and a background current reduction circuit. The system is designed for cryogenic operation at liquid nitrogen temperatures, and it achieves a maximum burst-mode frame rate of five million frames per second, which is the fastest demonstrated imaging array for mid/long-wavelength infrared.
{"title":"A 5,000,000 Frame/Sec Burst-Mode Cryogenic Thermal Imager With On-Chip Frame Memory","authors":"Xiaoyu Lian;Eric Stang;Kangping Hu;Pradeep R. Guduru;Jacob K. Rosenstein","doi":"10.1109/LSSC.2024.3443744","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3443744","url":null,"abstract":"This letter presents a high-speed global-shutter thermal imaging system, with a \u0000<inline-formula> <tex-math>$24^{V} times 24^{H} $ </tex-math></inline-formula>\u0000 pixel HgCdTe infrared focal plane array (FPA) detector and a custom CMOS readout integrated circuit (ROIC), including a 768-frame on-chip analog burst memory bank. Each pixel contains a buffered current injection circuit and a background current reduction circuit. The system is designed for cryogenic operation at liquid nitrogen temperatures, and it achieves a maximum burst-mode frame rate of five million frames per second, which is the fastest demonstrated imaging array for mid/long-wavelength infrared.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142099832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, a fully integrated capacitive-coupled digital isolator is proposed. By utilizing the adaptive carrier frequency control (AFC) scheme, the power consumption at low data rate is significantly reduced while maintaining a maximum data rate of 250 Mb/s. The on-chip isolation capacitor provides 2.5-kVRMS isolation rating with compact silicon area. The transmitter (TX) and receiver (RX) are fabricated in a 180-nm CMOS technology. Measurement results show that the transmitter consumes 0.6 and 1.15 mA at 100 kb/s and 250 Mb/s, respectively.
{"title":"A 250-Mb/s On-Chip Capacitive Digital Isolator With Adaptive Frequency Control","authors":"Dongfang Pan;Zhiyong Xiong;Qiming Lu;Fangting Miao;Litao Wu;Lin Cheng","doi":"10.1109/LSSC.2024.3439534","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3439534","url":null,"abstract":"In this letter, a fully integrated capacitive-coupled digital isolator is proposed. By utilizing the adaptive carrier frequency control (AFC) scheme, the power consumption at low data rate is significantly reduced while maintaining a maximum data rate of 250 Mb/s. The on-chip isolation capacitor provides 2.5-kVRMS isolation rating with compact silicon area. The transmitter (TX) and receiver (RX) are fabricated in a 180-nm CMOS technology. Measurement results show that the transmitter consumes 0.6 and 1.15 mA at 100 kb/s and 250 Mb/s, respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141993931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-06DOI: 10.1109/LSSC.2024.3439399
Guan-Yu Chen;Tai-Cheng Lee
This letter describes a single-ended transmitter (TX) output driver, which combines a feed-forward equalizer (FFE) and a far-end crosstalk (FEXT) canceller. The proposed output driver reduces the crosstalk-induced jitter (CIJ) between the two parallel coupled microstrip lines while preserving the inherent high-frequency boosting signal for the channel loss compensation. A prototype operating at a supply voltage of 0.9 V was fabricated in a 28-nm CMOS technology, occupying an area of $0.025~{text {mm}^{2}}$ . This prototype reduces the peak-to-peak jitter and CIJ by 48% (29 ps) and 114%, respectively, at 8 Gb/s. Furthermore, it increases the horizontal eye-opening (BER < 1E-12) by 34%, with an energy efficiency of 1.08 pJ/bit/channel.
{"title":"An 8 Gb/s Far-End Crosstalk Cancelation and FFE Co-Designed TX Output Driver","authors":"Guan-Yu Chen;Tai-Cheng Lee","doi":"10.1109/LSSC.2024.3439399","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3439399","url":null,"abstract":"This letter describes a single-ended transmitter (TX) output driver, which combines a feed-forward equalizer (FFE) and a far-end crosstalk (FEXT) canceller. The proposed output driver reduces the crosstalk-induced jitter (CIJ) between the two parallel coupled microstrip lines while preserving the inherent high-frequency boosting signal for the channel loss compensation. A prototype operating at a supply voltage of 0.9 V was fabricated in a 28-nm CMOS technology, occupying an area of \u0000<inline-formula> <tex-math>$0.025~{text {mm}^{2}}$ </tex-math></inline-formula>\u0000. This prototype reduces the peak-to-peak jitter and CIJ by 48% (29 ps) and 114%, respectively, at 8 Gb/s. Furthermore, it increases the horizontal eye-opening (BER < 1E-12) by 34%, with an energy efficiency of 1.08 pJ/bit/channel.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141993901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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