Pub Date : 2025-11-28DOI: 10.1109/LSSC.2025.3637833
Huanan Guo;Yufeng Yao;Xiang Gao
To reduce the bit-error-rate (BER), equalizers are implemented in high-speed SerDes receivers (RX) to compensate for channel insertion loss and mitigate intersymbol interference (ISI). Conventional analog front-end (AFE) designs primarily focus on amplitude gain while neglecting the influence of phase shift. This brief presents a phase equalization (PEQ) AFE design in a 7-nm FinFET 112 Gb/s DSP-based RX, which reduces the nonlinear phase shift within the Nyquist frequency $(f_{mathrm { nyq}})$ . The proposed PEQ compensates for the phase distortion and helps to achieve a pre-DSP eye opening of 0.17 UI and 47 mV over a 20.7 dB loss channel. The total RX demonstrates a BER less than 3e-7 with 1-tap DFE and 18-tap FFE over a 42.4 dB loss channel, achieving a power efficiency of 2.18 pJ/bit excluding the DSP power.
{"title":"A 112-Gb/s PAM4 Receiver With a Phase Equalization AFE in 7-nm FinFET","authors":"Huanan Guo;Yufeng Yao;Xiang Gao","doi":"10.1109/LSSC.2025.3637833","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3637833","url":null,"abstract":"To reduce the bit-error-rate (BER), equalizers are implemented in high-speed SerDes receivers (RX) to compensate for channel insertion loss and mitigate intersymbol interference (ISI). Conventional analog front-end (AFE) designs primarily focus on amplitude gain while neglecting the influence of phase shift. This brief presents a phase equalization (PEQ) AFE design in a 7-nm FinFET 112 Gb/s DSP-based RX, which reduces the nonlinear phase shift within the Nyquist frequency <inline-formula> <tex-math>$(f_{mathrm { nyq}})$ </tex-math></inline-formula>. The proposed PEQ compensates for the phase distortion and helps to achieve a pre-DSP eye opening of 0.17 UI and 47 mV over a 20.7 dB loss channel. The total RX demonstrates a BER less than 3e-7 with 1-tap DFE and 18-tap FFE over a 42.4 dB loss channel, achieving a power efficiency of 2.18 pJ/bit excluding the DSP power.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"5-8"},"PeriodicalIF":2.0,"publicationDate":"2025-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145705916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-21DOI: 10.1109/LSSC.2025.3636192
Suyash Shrivastava;Pydi Ganga Bahubalindruni
This manuscript presents an experimental characterization of a novel high speed D flip-flop (D-FF). The circuit was fabricated on a $27mu $ m thick flexible polyimide substrate using a nMOS only, single gate amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) technology. Reliable response of the D-FF was noticed from measurements up to a clock and an input signal frequency of $20{mathrm {,}}$ MHz and $2{mathrm {,}}$ MHz, respectively. Further, with an output voltage swing of 60%, D-FF functionality was observed up to clock and input signal frequencies of $25{mathrm {,}}$ MHz and $3{mathrm {,}}$ MHz, respectively. This circuit has shown a power dissipation of $140{mathrm {,}} mu $ W including buffers and the figure-of-merit (FOM) of $142{mathrm {,}}$ MHz/mW, which is almost a 52% improvement compared to the state-of-the-art. In addition, this D-FF is employed in the implementation of an 11-bit up/down (U/D) counter. The U/D counter has shown a reliable operation up to an operating frequency of $8{mathrm {,}}$ MHz with a power consumption of $4.8{mathrm {,}}$ mW. Both circuits were characterized at a low supply voltage of $3{mathrm {,}}$ V, occupying an active area of $0.144{mathrm {,}}$ mm2 and $4.32{mathrm {,}}$ mm2, respectively. These circuits would find potential application in biomedical wearable devices.
{"title":"A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil","authors":"Suyash Shrivastava;Pydi Ganga Bahubalindruni","doi":"10.1109/LSSC.2025.3636192","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3636192","url":null,"abstract":"This manuscript presents an experimental characterization of a novel high speed D flip-flop (D-FF). The circuit was fabricated on a <inline-formula> <tex-math>$27mu $ </tex-math></inline-formula>m thick flexible polyimide substrate using a nMOS only, single gate amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) technology. Reliable response of the D-FF was noticed from measurements up to a clock and an input signal frequency of <inline-formula> <tex-math>$20{mathrm {,}}$ </tex-math></inline-formula>MHz and <inline-formula> <tex-math>$2{mathrm {,}}$ </tex-math></inline-formula>MHz, respectively. Further, with an output voltage swing of 60%, D-FF functionality was observed up to clock and input signal frequencies of <inline-formula> <tex-math>$25{mathrm {,}}$ </tex-math></inline-formula>MHz and <inline-formula> <tex-math>$3{mathrm {,}}$ </tex-math></inline-formula>MHz, respectively. This circuit has shown a power dissipation of <inline-formula> <tex-math>$140{mathrm {,}} mu $ </tex-math></inline-formula>W including buffers and the figure-of-merit (FOM) of <inline-formula> <tex-math>$142{mathrm {,}}$ </tex-math></inline-formula>MHz/mW, which is almost a 52% improvement compared to the state-of-the-art. In addition, this D-FF is employed in the implementation of an 11-bit up/down (U/D) counter. The U/D counter has shown a reliable operation up to an operating frequency of <inline-formula> <tex-math>$8{mathrm {,}}$ </tex-math></inline-formula>MHz with a power consumption of <inline-formula> <tex-math>$4.8{mathrm {,}}$ </tex-math></inline-formula>mW. Both circuits were characterized at a low supply voltage of <inline-formula> <tex-math>$3{mathrm {,}}$ </tex-math></inline-formula>V, occupying an active area of <inline-formula> <tex-math>$0.144{mathrm {,}}$ </tex-math></inline-formula>mm2 and <inline-formula> <tex-math>$4.32{mathrm {,}}$ </tex-math></inline-formula>mm2, respectively. These circuits would find potential application in biomedical wearable devices.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"373-376"},"PeriodicalIF":2.0,"publicationDate":"2025-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145674680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-18DOI: 10.1109/LSSC.2025.3634340
Simon Foster;Scott Block;Daniel McMitchell;Edgar Colin-Beltran;Robert Dailey
A cell monitoring system for performance and safety enhancement is presented. It is the first commercially available single-chip-on-cell near-field contactless solution for automotive battery management, simplifying pack interconnect and reducing points of failure. This letter is a companion paper to the earlier ISSCC paper. It provides further details on the benefits of this architecture, including earlier thermal runaway detection capabilities. It also presents further data on the robustness of the near-field communication link in the presence of common and differential mode interference.
{"title":"Advancing On-Cell Near-Field Monitoring for Thermal Runaway Detection in EV Batteries","authors":"Simon Foster;Scott Block;Daniel McMitchell;Edgar Colin-Beltran;Robert Dailey","doi":"10.1109/LSSC.2025.3634340","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3634340","url":null,"abstract":"A cell monitoring system for performance and safety enhancement is presented. It is the first commercially available single-chip-on-cell near-field contactless solution for automotive battery management, simplifying pack interconnect and reducing points of failure. This letter is a companion paper to the earlier ISSCC paper. It provides further details on the benefits of this architecture, including earlier thermal runaway detection capabilities. It also presents further data on the robustness of the near-field communication link in the presence of common and differential mode interference.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"369-372"},"PeriodicalIF":2.0,"publicationDate":"2025-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11257864","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145674662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-03DOI: 10.1109/LSSC.2025.3628176
Harold Pilo;Manish Arora;Chien-An Lai;Mike Lee;Zack Lo;Mayur Randeria
A high-density (HD), SRAM-based register file (RF) has been demonstrated in Intel 18A Technology (Wang et al., 2025 and Pilo et al., 2025) featuring RibbonFET GAA transistors and a back side power delivery network (BSDPN). The RF is optimized for HD and array efficiency and achieves a density of 37.8 Mb/mm2, the highest density reported to date for an RF in the most advanced technology nodes (Wang et al., 2025, Chang et al., 2025, and Pilo et al., 2025). It is implemented with a conventional bitline (BL), two-bank memory architecture and it can be used as the SRAM workhorse for most SoC applications with maximum bit-count of 262Kb.
在Intel 18A Technology （Wang et al., 2025 and Pilo et al., 2025）中已经演示了一种高密度（HD）、基于sram的寄存器文件（RF），该文件具有带状场效应晶体管GAA晶体管和背面供电网络（BSDPN）。该射频针对高清和阵列效率进行了优化，密度达到37.8 Mb/mm2，这是迄今为止报道的最先进技术节点射频的最高密度（Wang et al., 2025; Chang et al., 2025; Pilo et al., 2025）。它采用传统的位线（BL）、双银行存储器架构，可以作为SRAM的主力，用于大多数SoC应用，最大比特数为262Kb。
{"title":"A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection","authors":"Harold Pilo;Manish Arora;Chien-An Lai;Mike Lee;Zack Lo;Mayur Randeria","doi":"10.1109/LSSC.2025.3628176","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3628176","url":null,"abstract":"A high-density (HD), SRAM-based register file (RF) has been demonstrated in Intel 18A Technology (Wang et al., 2025 and Pilo et al., 2025) featuring RibbonFET GAA transistors and a back side power delivery network (BSDPN). The RF is optimized for HD and array efficiency and achieves a density of 37.8 Mb/mm2, the highest density reported to date for an RF in the most advanced technology nodes (Wang et al., 2025, Chang et al., 2025, and Pilo et al., 2025). It is implemented with a conventional bitline (BL), two-bank memory architecture and it can be used as the SRAM workhorse for most SoC applications with maximum bit-count of 262Kb.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"357-360"},"PeriodicalIF":2.0,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a CMOS image sensor (CIS) that integrates two operation modes: 1) a high-resolution viewing mode with $0.8~mu $ m 32 Mpixels and 2) a low-power always-on object recognition mode consuming 2.67 mW at 10 frames/s. The CIS features a unique windmill-pattern analog edge extraction circuit that is resilient to illumination variations. An on-chip deep neural network processor was implemented alongside a compact algorithm with only 12 kB for coefficients and 48 kB for working memory. The design incorporates separate circuit areas for high-speed viewing and low-power sensing modes, thereby ensuring optimal performance and energy efficiency.
本文介绍了一种集成了两种工作模式的CMOS图像传感器（CIS）： 1)高分辨率观看模式，像素为0.8~ 3.2 m; 2)低功耗始终在线的目标识别模式，以10帧/秒的速度消耗2.67 mW。CIS具有独特的风车模式模拟边缘提取电路，可适应光照变化。片上深度神经网络处理器与紧凑的算法一起实现，系数只有12 kB，工作内存只有48 kB。该设计结合了独立的电路区域，用于高速观看和低功耗传感模式，从而确保了最佳性能和能源效率。
{"title":"A 0.8-μm 32-Mpixel Always-On CMOS Image Sensor With Windmill-Pattern Edge Extraction and On-Chip DNN","authors":"Mamoru Sato;Sachio Akebono;Kazuyoshi Yasuoka;Eriko Kato;Masahiro Tsuruta;Chiaki Takano;Kensuke Ota;Kazuki Haraguchi;Masahiro Watanabe;Genki Fujii;Koichiro Yamanaka;Kazunori Yasuda;Satoshi Minami;Katsuhiko Hanzawa;Kohei Matsuda;Akihiko Kato;Yosuke Ueno","doi":"10.1109/LSSC.2025.3628314","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3628314","url":null,"abstract":"This letter presents a CMOS image sensor (CIS) that integrates two operation modes: 1) a high-resolution viewing mode with <inline-formula> <tex-math>$0.8~mu $ </tex-math></inline-formula>m 32 Mpixels and 2) a low-power always-on object recognition mode consuming 2.67 mW at 10 frames/s. The CIS features a unique windmill-pattern analog edge extraction circuit that is resilient to illumination variations. An on-chip deep neural network processor was implemented alongside a compact algorithm with only 12 kB for coefficients and 48 kB for working memory. The design incorporates separate circuit areas for high-speed viewing and low-power sensing modes, thereby ensuring optimal performance and energy efficiency.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"353-356"},"PeriodicalIF":2.0,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents an ultralow-noise, power-efficient, and pulse-width modulation (PWM)-dimming-tolerant photocurrent readout circuit for under-display ambient light sensor (ALS). A transimpedance amplifier (TIA) with a feedback diode achieves G$Omega $ -level resistance and 6 fA/$surd $ Hz input current noise, enabling sub-pA resolution. Instability and noise folding are mitigated at low power through a signal-dependent auto-tracking zero for frequency compensation and a low-pass filter for high-frequency noise suppression. A 2-point calibration algorithm improves the linearity of the current-to-frequency (I2F) quantizer without incurring additional power. To extract ambient light in the presence of PWM dimming interference, the readout supports under-sampling, allowing digital cancellation of interference. Fabricated in 180 nm CMOS, the prototype achieves $0.36~rm pA_{pp}$ resolution, 146.3 dB dynamic range (DR), and a 206.3 dB $rm FoM_{DR}$ in 0.84 ms readout time, representing best-in-class performance. Optical ALS measurements under PWM dimming interference are experimentally validated.
{"title":"A 560 μ W, 6 fA/√Hz, 146 dB-DR Ultrasensitive Current Readout Circuit for PWM-Dimming-Tolerant Under-Display Ambient Light Sensors","authors":"Xiuzhi Zhao;Liheng Liu;Shi Chen;Tianxiang Qu;Qinjing Pan;Dan Li;Gan Guo;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2025.3626378","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3626378","url":null,"abstract":"This letter presents an ultralow-noise, power-efficient, and pulse-width modulation (PWM)-dimming-tolerant photocurrent readout circuit for under-display ambient light sensor (ALS). A transimpedance amplifier (TIA) with a feedback diode achieves G<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>-level resistance and 6 fA/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz input current noise, enabling sub-pA resolution. Instability and noise folding are mitigated at low power through a signal-dependent auto-tracking zero for frequency compensation and a low-pass filter for high-frequency noise suppression. A 2-point calibration algorithm improves the linearity of the current-to-frequency (I2F) quantizer without incurring additional power. To extract ambient light in the presence of PWM dimming interference, the readout supports under-sampling, allowing digital cancellation of interference. Fabricated in 180 nm CMOS, the prototype achieves <inline-formula> <tex-math>$0.36~rm pA_{pp}$ </tex-math></inline-formula> resolution, 146.3 dB dynamic range (DR), and a 206.3 dB <inline-formula> <tex-math>$rm FoM_{DR}$ </tex-math></inline-formula> in 0.84 ms readout time, representing best-in-class performance. Optical ALS measurements under PWM dimming interference are experimentally validated.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"361-364"},"PeriodicalIF":2.0,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-30DOI: 10.1109/LSSC.2025.3627274
Jakob Finkbeiner;Raphael Nägele;Manuel Wittlinger;Markus Grözing;Manfred Berroth;Georg Rademacher
Analog computing offers intrinsic energy and latency benefits that makes it attractive for real-time and edge applications. Conventional analog accelerators suffer from repeated conversions between analog and digital domain, which degrades efficiency and throughput. We propose an all-analog pipelined neural network accelerator architecture in 22 nm fully-depleted silicon-on-insulator (FD-SOI) complementary metal-oxide-semiconductor (CMOS). Measurements of a demonstrator ASIC with analog I/Os and 6 bit weights are presented. The system energy efficiency is 290 TOPS/W or 558 TOPS/W if the energy for bias generation is neglected. The pipelined architecture achieves a throughput of 500M inferences/s and a latency of 1 ns/layer.
{"title":"PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI","authors":"Jakob Finkbeiner;Raphael Nägele;Manuel Wittlinger;Markus Grözing;Manfred Berroth;Georg Rademacher","doi":"10.1109/LSSC.2025.3627274","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3627274","url":null,"abstract":"Analog computing offers intrinsic energy and latency benefits that makes it attractive for real-time and edge applications. Conventional analog accelerators suffer from repeated conversions between analog and digital domain, which degrades efficiency and throughput. We propose an all-analog pipelined neural network accelerator architecture in 22 nm fully-depleted silicon-on-insulator (FD-SOI) complementary metal-oxide-semiconductor (CMOS). Measurements of a demonstrator ASIC with analog I/Os and 6 bit weights are presented. The system energy efficiency is 290 TOPS/W or 558 TOPS/W if the energy for bias generation is neglected. The pipelined architecture achieves a throughput of 500M inferences/s and a latency of 1 ns/layer.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"365-368"},"PeriodicalIF":2.0,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-28DOI: 10.1109/LSSC.2025.3626442
Ethan Chou;Hesham Beshary;Nima Baniasadi;Ali M. Niknejad
This letter presents a wideband and low-power direct-downconversion 200 GHz receiver element for digital-beamforming applications implemented in 16 nm FinFET technology. Wideband and low integrated receiver noise figure of 9.8 dB across a 21 GHz baseband bandwidth is realized with a differential low-noise amplifier leveraging an active input balun stage, while wideband gain of 29 dB with a 3-dB bandwidth at RF of 42 GHz is maintained throughout the receiver chain. Low-loss I/Q splitting and current-efficient variable-gain baseband amplification enable relatively low total DC power consumption of 130 mW, including the LO chain. The high instantaneous bandwidth and low power consumption enable potentially high data rates with high energy efficiency.
{"title":"A 200 GHz Wideband and Low-Power Direct-Downconversion Receiver Element in 16 nm FinFET Technology","authors":"Ethan Chou;Hesham Beshary;Nima Baniasadi;Ali M. Niknejad","doi":"10.1109/LSSC.2025.3626442","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3626442","url":null,"abstract":"This letter presents a wideband and low-power direct-downconversion 200 GHz receiver element for digital-beamforming applications implemented in 16 nm FinFET technology. Wideband and low integrated receiver noise figure of 9.8 dB across a 21 GHz baseband bandwidth is realized with a differential low-noise amplifier leveraging an active input balun stage, while wideband gain of 29 dB with a 3-dB bandwidth at RF of 42 GHz is maintained throughout the receiver chain. Low-loss I/Q splitting and current-efficient variable-gain baseband amplification enable relatively low total DC power consumption of 130 mW, including the LO chain. The high instantaneous bandwidth and low power consumption enable potentially high data rates with high energy efficiency.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"349-352"},"PeriodicalIF":2.0,"publicationDate":"2025-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-22DOI: 10.1109/LSSC.2025.3624096
Xiaosen Liu;Xichen Sun;Renwei Chen;Haozhe Zhang;Zhoutong Liu;Yan Wang
With the rapid advancement of chiplet and heterogenous integration technologies, delivering power through the package, redistribution layer (RDL), and chip layers in 3-D space has become a fundamental challenge for high-performance SoCs. This letter provides a comprehensive overview of power delivery solutions, including low-dropout regulator (LDOs), switched capacitor converters, and Buck converters. It further details and compares advanced techniques such as novel conversion topologies, control schemes, optimization strategies, and integration strategies, offering insights into overcoming the power wall in emerging 3D-ICs.
{"title":"3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter","authors":"Xiaosen Liu;Xichen Sun;Renwei Chen;Haozhe Zhang;Zhoutong Liu;Yan Wang","doi":"10.1109/LSSC.2025.3624096","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3624096","url":null,"abstract":"With the rapid advancement of chiplet and heterogenous integration technologies, delivering power through the package, redistribution layer (RDL), and chip layers in 3-D space has become a fundamental challenge for high-performance SoCs. This letter provides a comprehensive overview of power delivery solutions, including low-dropout regulator (LDOs), switched capacitor converters, and Buck converters. It further details and compares advanced techniques such as novel conversion topologies, control schemes, optimization strategies, and integration strategies, offering insights into overcoming the power wall in emerging 3D-ICs.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"341-344"},"PeriodicalIF":2.0,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-22DOI: 10.1109/LSSC.2025.3624263
Changjoo Kim;Sooho Park;Yohan Choi;Minkyun Shim;Woojin Lee;Donghwi Seo;Chulwoo Kim
This letter presents an 8-bit 400 MS/s 1-then-2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) employing a comparator rotation-based background offset calibration (CRBC) technique. Unlike conventional 1-then-2-bit/cycle architectures, where calibration validity depends on the input voltage, the proposed comparator rotation-based background calibration enables input-independent background calibration, ensuring rapid calibration convergence and the reliable detection of time-varying errors, irrespective of input conditions. The prototype ADC was fabricated in 28 nm CMOS technology and achieves a signal-to-noise and distortion ratio (SNDR) of 42.9 dB and a spurious-free dynamic range (SFDR) of 56.5 dB at the Nyquist frequency. It consumes 1.67 mW at 400 MS/s, resulting in a Walden figure-of-merit (FoMW) of 36.6 fJ/conversion-step.
{"title":"An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration","authors":"Changjoo Kim;Sooho Park;Yohan Choi;Minkyun Shim;Woojin Lee;Donghwi Seo;Chulwoo Kim","doi":"10.1109/LSSC.2025.3624263","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3624263","url":null,"abstract":"This letter presents an 8-bit 400 MS/s 1-then-2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) employing a comparator rotation-based background offset calibration (CRBC) technique. Unlike conventional 1-then-2-bit/cycle architectures, where calibration validity depends on the input voltage, the proposed comparator rotation-based background calibration enables input-independent background calibration, ensuring rapid calibration convergence and the reliable detection of time-varying errors, irrespective of input conditions. The prototype ADC was fabricated in 28 nm CMOS technology and achieves a signal-to-noise and distortion ratio (SNDR) of 42.9 dB and a spurious-free dynamic range (SFDR) of 56.5 dB at the Nyquist frequency. It consumes 1.67 mW at 400 MS/s, resulting in a Walden figure-of-merit (FoMW) of 36.6 fJ/conversion-step.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"345-348"},"PeriodicalIF":2.0,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：