Pub Date : 2024-07-30DOI: 10.1109/TCPMT.2024.3435863
Chen-Chen Li;Liang-Feng Qiu;Lin-Sheng Wu;Jun-Fa Mao
A parametric model is proposed for the coupled stripline coupler with arbitrary operating frequency and coupling coefficient in silicon-based 3-D RF integration. All the three parts of the coupler configuration, including the coupled stripline section, the coupled bends, and the stripline to grounded coplanar waveguide (GCPW) transitions, are modeled and then constructed. The conformal mapping (CM) method is employed to establish the relationship between the key geometrical parameters and the eigenmode characteristic impedances of coupled striplines. The analytical model is validated with high accuracy and the error is less than 4% when compared with the full-wave simulations. A scalable equivalent circuit model is established for the coupled bends with the arbitrary bend angle between 0° and 90°, which is formed by the integration of subregions. An equivalent circuit model is proposed for the stripline-to-GCPW transition and validated by full-wave simulation. Nine coupler prototypes are synthesized and fabricated with three typical coupling coefficients (7, 8, and 11 dB) and three central frequencies (10, 20, and 26.5 GHz). Good agreement is achieved among the S-parameters obtained by the proposed circuit model, full-wave simulations, and on-wafer measurements. The return loss and isolation of the couplers are better than 15 and 20 dB, respectively.
{"title":"Parametric Modeling of Coupled Stripline Coupler With Arbitrary Operating Frequency and Coupling Coefficient in Silicon-Based 3-D RF Integration","authors":"Chen-Chen Li;Liang-Feng Qiu;Lin-Sheng Wu;Jun-Fa Mao","doi":"10.1109/TCPMT.2024.3435863","DOIUrl":"10.1109/TCPMT.2024.3435863","url":null,"abstract":"A parametric model is proposed for the coupled stripline coupler with arbitrary operating frequency and coupling coefficient in silicon-based 3-D RF integration. All the three parts of the coupler configuration, including the coupled stripline section, the coupled bends, and the stripline to grounded coplanar waveguide (GCPW) transitions, are modeled and then constructed. The conformal mapping (CM) method is employed to establish the relationship between the key geometrical parameters and the eigenmode characteristic impedances of coupled striplines. The analytical model is validated with high accuracy and the error is less than 4% when compared with the full-wave simulations. A scalable equivalent circuit model is established for the coupled bends with the arbitrary bend angle between 0° and 90°, which is formed by the integration of subregions. An equivalent circuit model is proposed for the stripline-to-GCPW transition and validated by full-wave simulation. Nine coupler prototypes are synthesized and fabricated with three typical coupling coefficients (7, 8, and 11 dB) and three central frequencies (10, 20, and 26.5 GHz). Good agreement is achieved among the S-parameters obtained by the proposed circuit model, full-wave simulations, and on-wafer measurements. The return loss and isolation of the couplers are better than 15 and 20 dB, respectively.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 8","pages":"1441-1453"},"PeriodicalIF":2.3,"publicationDate":"2024-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141864151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-30DOI: 10.1109/TCPMT.2024.3435835
Hutao Shi;Chunmin Cheng;Chao Sun;Zhenyang Lei;Gai Wu;Lijie Li;Kang Liang;Wei Shen;Sheng Liu
In 2.5-D packaging, thermal aggregation and signal crosstalk have been major obstacles in the development of high-density interconnect technology, greatly impacting the reliability of devices. This work presents a polycrystal/monocrystal diamond interposer with excellent thermal conductivity and low dielectric constant as a substitute for the Si interposer, aiming to address both thermal and electrical issues simultaneously. The thermal and electrical characteristics of Si, glass, and diamond interposers are investigated by analyzing heat transfer, heat dissipation, and electrical characteristics. The results show that diamond interposers are expected to effectively improve the heat transfer effect with the equivalent thermal conductivity of through-diamond via (TDV) cell always greater than 1200 W/m $cdot $ K. The overall thermal resistance and peak temperature of the polycrystal diamond interposer drop by $0.75~^{circ }$ C/W and $23.9~^{circ }$ C compared to Si, respectively. The improved temperature uniformity of diamond interposer helps to reduce the risk of mechanical failure and delay of the chip. Furthermore, the peak transmission coefficient in TDV cell is -0.24 dB, which experienced a lower return loss compared to through-silicon via (TSV). Diamond interposers provide effective solutions for thermal management and signal crosstalk in 2.5-D packages, making it a promising candidate in the field of highly reliable packaging.
{"title":"Investigation of Heat Dissipation and Electrical Properties of Diamond Interposer for 2.5-D Packagings","authors":"Hutao Shi;Chunmin Cheng;Chao Sun;Zhenyang Lei;Gai Wu;Lijie Li;Kang Liang;Wei Shen;Sheng Liu","doi":"10.1109/TCPMT.2024.3435835","DOIUrl":"10.1109/TCPMT.2024.3435835","url":null,"abstract":"In 2.5-D packaging, thermal aggregation and signal crosstalk have been major obstacles in the development of high-density interconnect technology, greatly impacting the reliability of devices. This work presents a polycrystal/monocrystal diamond interposer with excellent thermal conductivity and low dielectric constant as a substitute for the Si interposer, aiming to address both thermal and electrical issues simultaneously. The thermal and electrical characteristics of Si, glass, and diamond interposers are investigated by analyzing heat transfer, heat dissipation, and electrical characteristics. The results show that diamond interposers are expected to effectively improve the heat transfer effect with the equivalent thermal conductivity of through-diamond via (TDV) cell always greater than 1200 W/m\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000K. The overall thermal resistance and peak temperature of the polycrystal diamond interposer drop by \u0000<inline-formula> <tex-math>$0.75~^{circ }$ </tex-math></inline-formula>\u0000C/W and \u0000<inline-formula> <tex-math>$23.9~^{circ }$ </tex-math></inline-formula>\u0000C compared to Si, respectively. The improved temperature uniformity of diamond interposer helps to reduce the risk of mechanical failure and delay of the chip. Furthermore, the peak transmission coefficient in TDV cell is -0.24 dB, which experienced a lower return loss compared to through-silicon via (TSV). Diamond interposers provide effective solutions for thermal management and signal crosstalk in 2.5-D packages, making it a promising candidate in the field of highly reliable packaging.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1601-1609"},"PeriodicalIF":2.3,"publicationDate":"2024-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141864153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-18DOI: 10.1109/TCPMT.2024.3429353
Youngsang Cho;Heonwoo Kim;Kyoungmin Lee;Hyungyung Jo;Heeseok Lee;Minkyu Kim;Yunhyeok Im
When designing system on chip (SoC), it is crucial to ensure that the temperature stays as lowest as possible during scenario operation. For that, the placement of system blocks on the chip should be carefully planned, and simulations should be conducted repeatedly until the final temperature-optimized floorplan is determined. However, this process is time-consuming. To solve this issue, the authors propose an efficient method for calculating the temperature distribution in real-time based on thermal resistance matrix (TRM), which can help designers identify the optimal arrangement case with the lowest temperature easily. The calculated temperature distribution plots of the chip are presented, which agree with computational fluid dynamics (CFDs) results.
{"title":"Fast and Real-Time Thermal-Aware Floorplan Methodology for SoC","authors":"Youngsang Cho;Heonwoo Kim;Kyoungmin Lee;Hyungyung Jo;Heeseok Lee;Minkyu Kim;Yunhyeok Im","doi":"10.1109/TCPMT.2024.3429353","DOIUrl":"10.1109/TCPMT.2024.3429353","url":null,"abstract":"When designing system on chip (SoC), it is crucial to ensure that the temperature stays as lowest as possible during scenario operation. For that, the placement of system blocks on the chip should be carefully planned, and simulations should be conducted repeatedly until the final temperature-optimized floorplan is determined. However, this process is time-consuming. To solve this issue, the authors propose an efficient method for calculating the temperature distribution in real-time based on thermal resistance matrix (TRM), which can help designers identify the optimal arrangement case with the lowest temperature easily. The calculated temperature distribution plots of the chip are presented, which agree with computational fluid dynamics (CFDs) results.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1568-1576"},"PeriodicalIF":2.3,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141739018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-18DOI: 10.1109/TCPMT.2024.3430220
Ahmad Halal;Balázs Plesz
The precise understanding of perovskite solar cells (PSCs) under different temperature conditions is crucial for quality control and performance evaluation in real-life operational environments. Furthermore, it aids in evaluating how temperature variation affects the current mismatch in the perovskite/crystalline silicon (c-Si)-based tandem solar cells. This study scrutinizes the temperature-dependent performance of PSCs using numerical simulations in SCAPS software, based on the investigations that were performed to determine the effect of temperature on characteristic parameters like open-circuit voltage, short-circuit current, maximum power point voltage and current, efficiency, fill factor (FF) and the spectral response (SR). In addition, single-diode model (SDM) parameters (photocurrent, reverse saturation current, and ideality factor) were determined from the simulated curves of the PSCs. The findings demonstrate a commendable thermal stability for PSCs within the $20~^{circ }$ C– $55~^{circ }$ C temperature range, with a power temperature coefficient of -0.25% °C-1, a lower value than in average c-Si solar cells. However, at temperatures exceeding $55~^{circ }$ C, a significantly higher power temperature coefficient of up to -0.67% °C-1 was observed. The results highlighted a contrasting response to temperature changes between PSCs and c-Si solar cells: in PSCs, an increasing temperature leads to a slight drop in open-circuit voltage ( $V_{mathrm {OC}}$ ) and short-circuit current ( $J_{mathrm {SC}}$ ) values, whereas, in the case of c-Si, there is a drastic drop in $V_{mathrm {OC}}$ while the $J_{mathrm {SC}}$ increases. Moreover, the calculated SR of PSCs demonstrated the same slight difference of temperature behavior at temperatures up to $55~^{circ }$ C and under the whole spectrum wavelength range, whereas c-Si only remains stable in the ultraviolet and visible spectrum. Finally, evaluating the single-diode parameters also revealed contrasting thermal behavior between PSCs and c-Si solar cells, particularly in photocurrent density. PSCs also show a slight rise in ideality factor below $55~^{circ }$ C, but this dependency intensifies at higher temperatures.
{"title":"A Comprehensive Study on the Thermal Behavior of Perovskite Solar Cell","authors":"Ahmad Halal;Balázs Plesz","doi":"10.1109/TCPMT.2024.3430220","DOIUrl":"10.1109/TCPMT.2024.3430220","url":null,"abstract":"The precise understanding of perovskite solar cells (PSCs) under different temperature conditions is crucial for quality control and performance evaluation in real-life operational environments. Furthermore, it aids in evaluating how temperature variation affects the current mismatch in the perovskite/crystalline silicon (c-Si)-based tandem solar cells. This study scrutinizes the temperature-dependent performance of PSCs using numerical simulations in SCAPS software, based on the investigations that were performed to determine the effect of temperature on characteristic parameters like open-circuit voltage, short-circuit current, maximum power point voltage and current, efficiency, fill factor (FF) and the spectral response (SR). In addition, single-diode model (SDM) parameters (photocurrent, reverse saturation current, and ideality factor) were determined from the simulated curves of the PSCs. The findings demonstrate a commendable thermal stability for PSCs within the \u0000<inline-formula> <tex-math>$20~^{circ }$ </tex-math></inline-formula>\u0000C–\u0000<inline-formula> <tex-math>$55~^{circ }$ </tex-math></inline-formula>\u0000C temperature range, with a power temperature coefficient of -0.25% °C-1, a lower value than in average c-Si solar cells. However, at temperatures exceeding \u0000<inline-formula> <tex-math>$55~^{circ }$ </tex-math></inline-formula>\u0000C, a significantly higher power temperature coefficient of up to -0.67% °C-1 was observed. The results highlighted a contrasting response to temperature changes between PSCs and c-Si solar cells: in PSCs, an increasing temperature leads to a slight drop in open-circuit voltage (\u0000<inline-formula> <tex-math>$V_{mathrm {OC}}$ </tex-math></inline-formula>\u0000) and short-circuit current (\u0000<inline-formula> <tex-math>$J_{mathrm {SC}}$ </tex-math></inline-formula>\u0000) values, whereas, in the case of c-Si, there is a drastic drop in \u0000<inline-formula> <tex-math>$V_{mathrm {OC}}$ </tex-math></inline-formula>\u0000 while the \u0000<inline-formula> <tex-math>$J_{mathrm {SC}}$ </tex-math></inline-formula>\u0000 increases. Moreover, the calculated SR of PSCs demonstrated the same slight difference of temperature behavior at temperatures up to \u0000<inline-formula> <tex-math>$55~^{circ }$ </tex-math></inline-formula>\u0000C and under the whole spectrum wavelength range, whereas c-Si only remains stable in the ultraviolet and visible spectrum. Finally, evaluating the single-diode parameters also revealed contrasting thermal behavior between PSCs and c-Si solar cells, particularly in photocurrent density. PSCs also show a slight rise in ideality factor below \u0000<inline-formula> <tex-math>$55~^{circ }$ </tex-math></inline-formula>\u0000C, but this dependency intensifies at higher temperatures.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 10","pages":"1753-1760"},"PeriodicalIF":2.3,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141739019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To meet the essential demands for high-performance microelectromechanical system (MEMS) integration, this study developed a novel Cu–Sn-based solid-liquid interdiffusion (SLID) interconnect solution. The study utilized a metallization stack incorporating a Co layer to interact with low-temperature Cu–Sn–In SLID. Since Cu6(Sn,In)5 forms at a lower temperature than other phases in the Cu–Sn–In SLID system, the goal was to produce single-phase (Cu,Co)6(Sn,In)5 interconnects. Bonding conditions were established for the Cu–Sn–In/Co system and the Cu–Sn/Co system as a reference. Thorough assessments of their thermomechanical reliability were conducted through high-temperature storage (HTS), thermal shock (TS), and tensile tests. The Cu–Sn–In/Co system emerged as a reliable low-temperature solution with the following key attributes: 1) a reduced bonding temperature of 200 °C compared to the nearly 300 °C required for Cu–Sn SLID interconnects to achieve stable phases in the interconnect bondline; 2) the absence of the Cu3Sn phase and resulting void-free interconnects; and 3) high thermomechanical reliability with tensile strengths exceeding the minimum requirements outlined in the MIL-STD-883 method 2027.2, particularly following the HTS test at 150 °C for 1000 h.
{"title":"Novel Low-Temperature Interconnects for 2.5-/3-D MEMS Integration: Demonstration and Reliability","authors":"Fahimeh Emadi;Vesa Vuorinen;Shenyi Liu;Mervi Paulasto-Kröckel","doi":"10.1109/TCPMT.2024.3430061","DOIUrl":"10.1109/TCPMT.2024.3430061","url":null,"abstract":"To meet the essential demands for high-performance microelectromechanical system (MEMS) integration, this study developed a novel Cu–Sn-based solid-liquid interdiffusion (SLID) interconnect solution. The study utilized a metallization stack incorporating a Co layer to interact with low-temperature Cu–Sn–In SLID. Since Cu6(Sn,In)5 forms at a lower temperature than other phases in the Cu–Sn–In SLID system, the goal was to produce single-phase (Cu,Co)6(Sn,In)5 interconnects. Bonding conditions were established for the Cu–Sn–In/Co system and the Cu–Sn/Co system as a reference. Thorough assessments of their thermomechanical reliability were conducted through high-temperature storage (HTS), thermal shock (TS), and tensile tests. The Cu–Sn–In/Co system emerged as a reliable low-temperature solution with the following key attributes: 1) a reduced bonding temperature of 200 °C compared to the nearly 300 °C required for Cu–Sn SLID interconnects to achieve stable phases in the interconnect bondline; 2) the absence of the Cu3Sn phase and resulting void-free interconnects; and 3) high thermomechanical reliability with tensile strengths exceeding the minimum requirements outlined in the MIL-STD-883 method 2027.2, particularly following the HTS test at 150 °C for 1000 h.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 8","pages":"1337-1346"},"PeriodicalIF":2.3,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10600710","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141739020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-16DOI: 10.1109/TCPMT.2024.3429168
Ding Wang;Chen Hui Xia;Yong Fan;Yu Jian Cheng
This article introduces a 94-GHz dual-polarized 1-D beamforming patch antenna array, specifically designed to achieve low sidelobe levels (SLLs) and an extensive scanning range. The array, in a $4times 8$ configuration, is capable of 1-D expansion and utilizes Ajinomoto build-up film (ABF) substrates alongside a precision electroplating process. This combination ensures high accuracy and fulfills the miniaturization demands for 94-GHz operations. A notable achievement of this research is the design of a compact power divider using a coupling line with short end, which establishes a large power dividing ratio. This design is pivotal in maintaining consistently low SLLs, typically below −18.2 dB and often below −20 dB, over the $92sim 96$ -GHz bandwidth within a $1times 8$ linear array. In addition, the array’s transverse profile is optimized by altering the feeder angle, decreasing the distance between linear arrays to $0.52lambda _{0}$ , where $lambda _{0}$ denotes the free-space wavelength at 94 GHz. The proposed $4times 8$ array design facilitates beam steering up to ±45° without grating lobes. The construction and experiments of the dual-polarized array antenna at 94.0 GHz validate its effectiveness, confirming the achievement of low SLL and extensive scanning capabilities in both polarizations.
{"title":"A 94-GHz Dual-Polarized 1-D Series-Fed Phased Array Antenna With Low Sidelobe Level Based on Multilayer Coreless ABF Substrates","authors":"Ding Wang;Chen Hui Xia;Yong Fan;Yu Jian Cheng","doi":"10.1109/TCPMT.2024.3429168","DOIUrl":"10.1109/TCPMT.2024.3429168","url":null,"abstract":"This article introduces a 94-GHz dual-polarized 1-D beamforming patch antenna array, specifically designed to achieve low sidelobe levels (SLLs) and an extensive scanning range. The array, in a \u0000<inline-formula> <tex-math>$4times 8$ </tex-math></inline-formula>\u0000 configuration, is capable of 1-D expansion and utilizes Ajinomoto build-up film (ABF) substrates alongside a precision electroplating process. This combination ensures high accuracy and fulfills the miniaturization demands for 94-GHz operations. A notable achievement of this research is the design of a compact power divider using a coupling line with short end, which establishes a large power dividing ratio. This design is pivotal in maintaining consistently low SLLs, typically below −18.2 dB and often below −20 dB, over the \u0000<inline-formula> <tex-math>$92sim 96$ </tex-math></inline-formula>\u0000-GHz bandwidth within a \u0000<inline-formula> <tex-math>$1times 8$ </tex-math></inline-formula>\u0000 linear array. In addition, the array’s transverse profile is optimized by altering the feeder angle, decreasing the distance between linear arrays to \u0000<inline-formula> <tex-math>$0.52lambda _{0}$ </tex-math></inline-formula>\u0000, where \u0000<inline-formula> <tex-math>$lambda _{0}$ </tex-math></inline-formula>\u0000 denotes the free-space wavelength at 94 GHz. The proposed \u0000<inline-formula> <tex-math>$4times 8$ </tex-math></inline-formula>\u0000 array design facilitates beam steering up to ±45° without grating lobes. The construction and experiments of the dual-polarized array antenna at 94.0 GHz validate its effectiveness, confirming the achievement of low SLL and extensive scanning capabilities in both polarizations.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1638-1648"},"PeriodicalIF":2.3,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141720947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-16DOI: 10.1109/TCPMT.2024.3429108
Yeonseop Yu;Sunyoung Kim;Yunhwan Kim;Taeho Moon
Thermocompression bonding (TC bonding) is a crucial process in the manufacture of high-bandwidth memory (HBM), facilitating the electrical connection between memory dies through microbumps and pads. However, this process is susceptible to defects, such as nonwet, dewet, or solder bridge formation. Understanding the dynamic behavior of molten solder is paramount due to the rapid nature of both solder melting and nonconductive film (NCF) curing, often occurring within seconds at ramp rates as high as $100~^{circ }$ C/s. In this study, we employed Surface Evolver software to simulate solder shape variations by manipulating solder height across a range of solder volumes and pad sizes. Through this simulation, we determined critical solder heights indicative of stable solder joint formation, including the height at which solder shape instability arises and the height at which applied force on the solder becomes zero. The fitting equations derived from these simulations allow for the calculation of microbump design parameters, facilitating stable solder joint formation without the need for complex Surface Evolver or finite element method (FEM) simulation. The validation of these equations against data from various literature sources demonstrates their efficacy in determining microbump design parameters. This work contributes to the advancement of reliable microbump design for TC bonding processes, offering practical insights for engineers and researchers in the field.
{"title":"Optimizing of Microbump Design for Stable Solder Joints in Thermocompression Bonding: A Simulation-Based Approach","authors":"Yeonseop Yu;Sunyoung Kim;Yunhwan Kim;Taeho Moon","doi":"10.1109/TCPMT.2024.3429108","DOIUrl":"10.1109/TCPMT.2024.3429108","url":null,"abstract":"Thermocompression bonding (TC bonding) is a crucial process in the manufacture of high-bandwidth memory (HBM), facilitating the electrical connection between memory dies through microbumps and pads. However, this process is susceptible to defects, such as nonwet, dewet, or solder bridge formation. Understanding the dynamic behavior of molten solder is paramount due to the rapid nature of both solder melting and nonconductive film (NCF) curing, often occurring within seconds at ramp rates as high as \u0000<inline-formula> <tex-math>$100~^{circ }$ </tex-math></inline-formula>\u0000C/s. In this study, we employed Surface Evolver software to simulate solder shape variations by manipulating solder height across a range of solder volumes and pad sizes. Through this simulation, we determined critical solder heights indicative of stable solder joint formation, including the height at which solder shape instability arises and the height at which applied force on the solder becomes zero. The fitting equations derived from these simulations allow for the calculation of microbump design parameters, facilitating stable solder joint formation without the need for complex Surface Evolver or finite element method (FEM) simulation. The validation of these equations against data from various literature sources demonstrates their efficacy in determining microbump design parameters. This work contributes to the advancement of reliable microbump design for TC bonding processes, offering practical insights for engineers and researchers in the field.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1701-1706"},"PeriodicalIF":2.3,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141720952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-15DOI: 10.1109/tcpmt.2024.3428404
Karanvir S. Sidhu, Roni Khazaka
{"title":"Nested Latin Hypercube-based Sampling for efficient Uncertainty Quantification using Sensitivity Assisted Least Squares SVM","authors":"Karanvir S. Sidhu, Roni Khazaka","doi":"10.1109/tcpmt.2024.3428404","DOIUrl":"https://doi.org/10.1109/tcpmt.2024.3428404","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"124 1","pages":""},"PeriodicalIF":2.2,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141720951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-15DOI: 10.1109/TCPMT.2024.3428595
Jie Wang;Gaomin Li;Yuezheng Zhou;Haoyu Bai;Xuan Li;Lijun Zhong;Xiaohu Zhang
Integrated circuit chips are the most common electronic components, and visual internal defect detection is essential for ensuring product quality following packaging. However, efficient detection of chip internal defects is challenging due to the complexity of the background and the faintness of defects. To overcome the above difficulties, a novel deep learning-based defect segmentation framework is proposed, which relies on an image preprocessing (IPP) scheme and a defect segmentation network (DSNet). The IPP is composed of a rotation correction algorithm and a region segmentation algorithm for removing the influence of background and obtaining chip packaging region. The DSNet is proposed to precisely and efficiently segment the internal defects. To address the scarcity of data and avoid overfitting, we proposed the lightweight convolution block by using depth-wise separable convolution (DWSC) to reduce the number of parameters. Besides, the attention gate (AG) module is incorporated into the skip connection to handle the shape varieties of the defects. Moreover, the Focal loss function is designed to guide the network to pay attention to small defects that are difficult to distinguish. The robustness and adaptability of the proposed method are evaluated on three typical types of chip X-ray datasets from real-world inspection lines. Experimental results show that the proposed framework achieves a satisfactory tradeoff between detection accuracy and speed with an $F1$ -score of 72.69% and a frames per second (FPS) of 17.5 on average, resulting in superior segmentation performance even with sparse or insufficient data.
集成电路芯片是最常见的电子元件，可视内部缺陷检测对于确保封装后的产品质量至关重要。然而，由于背景的复杂性和缺陷的模糊性，高效检测芯片内部缺陷具有挑战性。为了克服上述困难，本文提出了一种基于深度学习的新型缺陷分割框架，该框架依赖于图像预处理（IPP）方案和缺陷分割网络（DSNet）。IPP 由旋转校正算法和区域分割算法组成，用于去除背景影响并获得芯片封装区域。DSNet 用于精确有效地分割内部缺陷。针对数据稀缺和避免过拟合的问题，我们提出了轻量级卷积块，利用深度可分离卷积（DWSC）来减少参数数量。此外，在跳转连接中加入了注意门（AG）模块，以处理缺陷的形状变化。此外，还设计了焦点损失函数，以引导网络关注难以区分的小缺陷。我们在实际检测线的三种典型芯片 X 射线数据集上评估了所提方法的鲁棒性和适应性。实验结果表明，所提出的框架在检测精度和速度之间取得了令人满意的平衡，F1$ 分数为 72.69%，平均每秒帧数（FPS）为 17.5，即使在数据稀少或不足的情况下也能实现出色的分割性能。
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Pub Date : 2024-07-15DOI: 10.1109/TCPMT.2024.3428478
Qiuyue Wu;Yuan Xu;Na Liu;Mingwei Zhuang;Qing Huo Liu
In the field of modern electronics engineering, the analysis of electrothermal coupling in multiscale electronic devices is increasingly complex, demanding more computational resources and presenting challenges in rapid convergence. This complexity is further heightened by the continuous evolution of integrated circuit (IC) packaging technologies. Recognizing these challenges, this study introduces a new domain decomposition method (DDM) specifically engineered to address transient electrothermal coupling analysis in such environments. The proposed DDM can utilize meshes with varying densities across different subdomains and employ nonconformal meshes at the interface. This method can optimize computational efficiency while ensuring simulation accuracy. The contribution lies in its ability to flexibly mesh the structure according to its characteristics and reduce the overall degrees of freedom (DoFs). Representative examples are used for a series of tests in modern ICs. The results demonstrate not only the accuracy but also the efficiency in handling intricate electrothermal coupling problems. In the context of escalating multiscale integration complexities, the proposed DDM provides a powerful tool for engineers and designers to optimize device performance.
{"title":"Electrothermal Transient Co-Simulation With Domain Decomposition Method for 3-D Complex Integrated Systems","authors":"Qiuyue Wu;Yuan Xu;Na Liu;Mingwei Zhuang;Qing Huo Liu","doi":"10.1109/TCPMT.2024.3428478","DOIUrl":"10.1109/TCPMT.2024.3428478","url":null,"abstract":"In the field of modern electronics engineering, the analysis of electrothermal coupling in multiscale electronic devices is increasingly complex, demanding more computational resources and presenting challenges in rapid convergence. This complexity is further heightened by the continuous evolution of integrated circuit (IC) packaging technologies. Recognizing these challenges, this study introduces a new domain decomposition method (DDM) specifically engineered to address transient electrothermal coupling analysis in such environments. The proposed DDM can utilize meshes with varying densities across different subdomains and employ nonconformal meshes at the interface. This method can optimize computational efficiency while ensuring simulation accuracy. The contribution lies in its ability to flexibly mesh the structure according to its characteristics and reduce the overall degrees of freedom (DoFs). Representative examples are used for a series of tests in modern ICs. The results demonstrate not only the accuracy but also the efficiency in handling intricate electrothermal coupling problems. In the context of escalating multiscale integration complexities, the proposed DDM provides a powerful tool for engineers and designers to optimize device performance.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 8","pages":"1374-1383"},"PeriodicalIF":2.3,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141720953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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