To enhance the electrical performance and reliability of silicon carbide (SiC) power modules, the study explores Cu-clip as a promising alternative to traditional Al-wire interconnections. SiC power modules, particularly in parallel configurations, encounter challenges in optimizing dynamic current-sharing performance, which limits their maximum current capacity and reliability during switching events. This study proposes an innovative layout design for SiC MOSFET modules, utilizing a coupled parasitic inductance network model to capture better the impact of mutual inductances on dynamic current imbalance. The model derives an equation for equivalent source inductances, accounting for both self-inductance and mutual inductance, providing a foundation for optimizing the layout to minimize dynamic current imbalance. Based on this model, a new Cu-clip structure is designed along with a mathematical analysis aimed at reducing disparities in equivalent source inductances, thereby enhancing dynamic current balancing. The distance between the dies is also increased to mitigate thermal coupling effects. Double-pulse tests and simulations were performed to validate the dynamic current balancing performance of the fabricated power module. The results show a 40% reduction in dynamic current imbalance for the optimized layout (layout B) compared to the baseline configuration (layout A). This work presents a comprehensive solution to improve the dynamic current performance of paralleled SiC MOSFET power modules, offering significant contributions to the design of more efficient and reliable power electronics.
{"title":"Analytical and Optimal Strategy of Dynamic Current Balancing for Paralleled SiC MOSFETs With Cu-Clip Interconnection Considering Mutual Coupled Inductances","authors":"Xun Liu;Kun Ma;Yameng Sun;Yifan Song;Xiao Zhang;Anning Chen;Xuehan Li;Wei Huang;Huimin Shi;Miao Li;Yang Zhou;Sheng Liu","doi":"10.1109/TCPMT.2025.3561273","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3561273","url":null,"abstract":"To enhance the electrical performance and reliability of silicon carbide (SiC) power modules, the study explores Cu-clip as a promising alternative to traditional Al-wire interconnections. SiC power modules, particularly in parallel configurations, encounter challenges in optimizing dynamic current-sharing performance, which limits their maximum current capacity and reliability during switching events. This study proposes an innovative layout design for SiC MOSFET modules, utilizing a coupled parasitic inductance network model to capture better the impact of mutual inductances on dynamic current imbalance. The model derives an equation for equivalent source inductances, accounting for both self-inductance and mutual inductance, providing a foundation for optimizing the layout to minimize dynamic current imbalance. Based on this model, a new Cu-clip structure is designed along with a mathematical analysis aimed at reducing disparities in equivalent source inductances, thereby enhancing dynamic current balancing. The distance between the dies is also increased to mitigate thermal coupling effects. Double-pulse tests and simulations were performed to validate the dynamic current balancing performance of the fabricated power module. The results show a 40% reduction in dynamic current imbalance for the optimized layout (layout B) compared to the baseline configuration (layout A). This work presents a comprehensive solution to improve the dynamic current performance of paralleled SiC MOSFET power modules, offering significant contributions to the design of more efficient and reliable power electronics.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1189-1202"},"PeriodicalIF":2.3,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-15DOI: 10.1109/TCPMT.2025.3560722
Kamil Gradkowski
This study investigates alignment and coupling between a photonic integrated circuit (PIC) and a mixed-mode fiber array (FA), where one of the channels in the normally single-mode (SM) array is replaced by a multimode fiber (MMF). As a result, the tolerances of alignment are significantly relaxed. The proposed method suggests using the single-mode fiber (SMF) at the input and the MMF at the output of the PIC. In such a transmission configuration, the tolerances are relaxed by a factor of $surd 2$ (41%). As this scales with mode size, the beam-expansion mechanisms, for example, utilizing microlenses, can further significantly reduce the requirements for fabrication and packaging of photonic devices, making them more robust and cheaper to manufacture.
{"title":"Mixed-Mode Fiber Array Alignment and Coupling to Photonic Integrated Circuits","authors":"Kamil Gradkowski","doi":"10.1109/TCPMT.2025.3560722","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3560722","url":null,"abstract":"This study investigates alignment and coupling between a photonic integrated circuit (PIC) and a mixed-mode fiber array (FA), where one of the channels in the normally single-mode (SM) array is replaced by a multimode fiber (MMF). As a result, the tolerances of alignment are significantly relaxed. The proposed method suggests using the single-mode fiber (SMF) at the input and the MMF at the output of the PIC. In such a transmission configuration, the tolerances are relaxed by a factor of <inline-formula> <tex-math>$surd 2$ </tex-math></inline-formula> (41%). As this scales with mode size, the beam-expansion mechanisms, for example, utilizing microlenses, can further significantly reduce the requirements for fabrication and packaging of photonic devices, making them more robust and cheaper to manufacture.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1156-1160"},"PeriodicalIF":2.3,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10965704","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-15DOI: 10.1109/TCPMT.2025.3560983
Shuangxu Li;Lei Zhu;Kaixue Ma
In this article, an efficient and accurate synthesis design method for bandpass filters (BPFs) based on low-loss quarter-wavelength ($lambda $ /4) substrate integrated suspended line (SISL) resonators is proposed, using the short-open-load (SOL) calibration technique. The BPF topology is comprised of SISL with two volumes of vias on both side walls and alternating SISL-based J/K inverters. First, with the help of full-wave simulation, the propagation characteristics of the SISL with periodically loaded pins are analyzed and extracted by SOL. Afterward, to facilitate the filter synthesis design, the equivalent circuit parameters of each J/K inverter with symmetrical/asymmetrical feed lines are accurately extracted. Herein, the extra transition for circuit measurement can be directly merged into the input port of the $J_{01}$ inverter and then be regarded as an error box to be calibrated out by SOL. Therefore, the efficient co-design of the resultant SISL BPF containing the feed transition can be achieved. Finally, two 4th-order all-pole Chebyshev SISL BPFs with $lambda $ /4 resonators are designed and fabricated. The synthesized, simulated, and measured results of all the implemented SISL BPFs are found in good agreement, evidently demonstrating the effectiveness of the SOL technique for designing the SISL circuits. In addition, the SISL BPFs have the advantages of low loss and self-packaging against traditional planar BPFs.
{"title":"Synthesis Design of Low-Loss and Self-Packaged Bandpass Filter on λ/4 SISL Resonators Using the Short-Open-Load (SOL) Technique","authors":"Shuangxu Li;Lei Zhu;Kaixue Ma","doi":"10.1109/TCPMT.2025.3560983","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3560983","url":null,"abstract":"In this article, an efficient and accurate synthesis design method for bandpass filters (BPFs) based on low-loss quarter-wavelength (<inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/4) substrate integrated suspended line (SISL) resonators is proposed, using the short-open-load (SOL) calibration technique. The BPF topology is comprised of SISL with two volumes of vias on both side walls and alternating SISL-based <italic>J</i>/<italic>K</i> inverters. First, with the help of full-wave simulation, the propagation characteristics of the SISL with periodically loaded pins are analyzed and extracted by SOL. Afterward, to facilitate the filter synthesis design, the equivalent circuit parameters of each <italic>J</i>/<italic>K</i> inverter with symmetrical/asymmetrical feed lines are accurately extracted. Herein, the extra transition for circuit measurement can be directly merged into the input port of the <inline-formula> <tex-math>$J_{01}$ </tex-math></inline-formula> inverter and then be regarded as an error box to be calibrated out by SOL. Therefore, the efficient co-design of the resultant SISL BPF containing the feed transition can be achieved. Finally, two 4th-order all-pole Chebyshev SISL BPFs with <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/4 resonators are designed and fabricated. The synthesized, simulated, and measured results of all the implemented SISL BPFs are found in good agreement, evidently demonstrating the effectiveness of the SOL technique for designing the SISL circuits. In addition, the SISL BPFs have the advantages of low loss and self-packaging against traditional planar BPFs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1328-1336"},"PeriodicalIF":2.3,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-11DOI: 10.1109/TCPMT.2025.3553729
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information","authors":"","doi":"10.1109/TCPMT.2025.3553729","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3553729","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10964035","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-11DOI: 10.1109/TCPMT.2025.3553727
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors","authors":"","doi":"10.1109/TCPMT.2025.3553727","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3553727","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"884-884"},"PeriodicalIF":2.3,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10964062","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-11DOI: 10.1109/TCPMT.2025.3553725
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information","authors":"","doi":"10.1109/TCPMT.2025.3553725","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3553725","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"C2-C2"},"PeriodicalIF":2.3,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10964063","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143820334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-10DOI: 10.1109/TCPMT.2025.3559525
M. Asaduz Zaman Mamun;Amar Mavinkurve;René Rongen;Michiel van Soestbergen;Muhammad A. Alam
Since the 1950s, and continuing to the present day, wirebond (WB) has remained the most popular interconnection technology. WB is known for its cost-effectiveness, proven reliability, and ease of processing. WB process has advanced significantly with modern developments, such as full automation and optimization of epoxy mold compounds (EMCs). However, mainstream CuAl WB contacts are susceptible to corrosion failures, triggered by the transport and localization of ionic species within the EMCs. The failure is primarily driven by applied bias but exacerbated by environmental factors, such as high relative humidity (RH) and temperature (T). In this scenario, a physics-based generalized failure model for WB corrosion has the potential to offer a robust and standardized qualification approach, streamline the testing process, and facilitate any future WB scaling. In this study, we: i) investigate the in situ ion migration behavior in the EMC using our proposed leakage current-based strategy; ii) simulate and analytically approximate the transient space charge accumulation in the WB-EMC interface; iii) integrate the insights from the simulations and the assumption of a first-order redox reaction into a failure distribution model; and iv) validate the model with integrated circuit (IC) failure data from accelerated tests. The resulting model would serve as a versatile predictive tool for qualifying WB technology.
{"title":"Wirebond Corrosion Failure of Plastic Packages in Extreme Environments: Theory and Experiment","authors":"M. Asaduz Zaman Mamun;Amar Mavinkurve;René Rongen;Michiel van Soestbergen;Muhammad A. Alam","doi":"10.1109/TCPMT.2025.3559525","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3559525","url":null,"abstract":"Since the 1950s, and continuing to the present day, wirebond (WB) has remained the most popular interconnection technology. WB is known for its cost-effectiveness, proven reliability, and ease of processing. WB process has advanced significantly with modern developments, such as full automation and optimization of epoxy mold compounds (EMCs). However, mainstream CuAl WB contacts are susceptible to corrosion failures, triggered by the transport and localization of ionic species within the EMCs. The failure is primarily driven by applied bias but exacerbated by environmental factors, such as high relative humidity (RH) and temperature (<italic>T</i>). In this scenario, a physics-based generalized failure model for WB corrosion has the potential to offer a robust and standardized qualification approach, streamline the testing process, and facilitate any future WB scaling. In this study, we: i) investigate the in situ ion migration behavior in the EMC using our proposed leakage current-based strategy; ii) simulate and analytically approximate the transient space charge accumulation in the WB-EMC interface; iii) integrate the insights from the simulations and the assumption of a first-order redox reaction into a failure distribution model; and iv) validate the model with integrated circuit (IC) failure data from accelerated tests. The resulting model would serve as a versatile predictive tool for qualifying WB technology.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1213-1221"},"PeriodicalIF":2.3,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-10DOI: 10.1109/TCPMT.2025.3559561
Naibo Zhang;Ze Yan;Ke Han;Guangyao Yang;Qiuquan Guo;Ruiliang Song;Zhongliang Deng;Jun Yang
This article demonstrates an integrated wide-angle scanning planar phased array based on pattern reconfigurable antennas (PRAs). The PRA unit consists of four rotationally symmetrical elements with a dimension less than $0.41~lambda times 0.41~lambda $ . By exciting different elements, the beam of the unit switches between four modes and has a 3 dB coverage of ±77°, which helps the antenna array achieve an expanded scanning range. The reconfigurable principle and bandwidth enhancement method of the compact antenna unit are analyzed; the radiation efficiency and the performances of the array are also discussed. The whole system of the phased array is integrated on a multilayer hybrid PCB board, which includes a $4times 4$ reconfigurable antenna array, TR modules, 4-channel RF chips, a beam control circuit, and a power management circuit. The measured return loss of the antenna unit is less than −10 dB in the frequency range of 27–30 GHz, and the scanning range is from −68° to 68° with a maximum gain of 16.4 dBi. The gain fluctuation of the array in beam scanning is less than 2 dB, and the scanning range of −3 dB covers ±80°.
{"title":"An Integrated Wide-Angle Scanning Planar Phased Array Based on Pattern Reconfigurable Antenna","authors":"Naibo Zhang;Ze Yan;Ke Han;Guangyao Yang;Qiuquan Guo;Ruiliang Song;Zhongliang Deng;Jun Yang","doi":"10.1109/TCPMT.2025.3559561","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3559561","url":null,"abstract":"This article demonstrates an integrated wide-angle scanning planar phased array based on pattern reconfigurable antennas (PRAs). The PRA unit consists of four rotationally symmetrical elements with a dimension less than <inline-formula> <tex-math>$0.41~lambda times 0.41~lambda $ </tex-math></inline-formula>. By exciting different elements, the beam of the unit switches between four modes and has a 3 dB coverage of ±77°, which helps the antenna array achieve an expanded scanning range. The reconfigurable principle and bandwidth enhancement method of the compact antenna unit are analyzed; the radiation efficiency and the performances of the array are also discussed. The whole system of the phased array is integrated on a multilayer hybrid PCB board, which includes a <inline-formula> <tex-math>$4times 4$ </tex-math></inline-formula> reconfigurable antenna array, TR modules, 4-channel RF chips, a beam control circuit, and a power management circuit. The measured return loss of the antenna unit is less than −10 dB in the frequency range of 27–30 GHz, and the scanning range is from −68° to 68° with a maximum gain of 16.4 dBi. The gain fluctuation of the array in beam scanning is less than 2 dB, and the scanning range of −3 dB covers ±80°.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1307-1318"},"PeriodicalIF":2.3,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-09DOI: 10.1109/TCPMT.2025.3559013
Yuanjun Chai;Kaixue Ma;Yongqiang Wang;Feng Feng;Ningning Yan
This article presents a 20-W 1.4–5-GHz self-packaged differential power amplifier (PA) using hybrid integrated suspended line (HISL) technology and a compensated distributed balun network that provides the PA optimum load impedance over a wide bandwidth. First, a compensated distributed balun network consisting of two coupled-line sections with compact inductors and capacitors for broadband board-level PAs is proposed. The network extends the bandwidth of board-level two-way PAs by 36.6%~71.6% compared to the same type of PAs and overcomes the challenges of integrating baluns with large packaged power devices with significant parasitics across wide bandwidths by trapezoidal capacitors. Second, closed-form design solutions and design parameters on this new network are derived and analyzed comprehensively to guide the design. Third, the proposed network is designed based on HISL, which is for low loss, small size, and self-packaging. As a proof of concept, a broadband high-gain ultrasmall differential PA with three stages is designed and implemented based on HISL technology, which demonstrates excellent performance and self-packaging. The implemented PA achieves the saturated output power (${P} _{text {sat}}$ ) of 40.5–44.6 dBm with maximum power added efficiency (PAE) of 24.4%–58.3% and 20–28.9-dB power gain from 1.4 to 5 GHz. With a fractional bandwidth over 110%, the PA exhibits a competitive figure of merit (FoM) of 96.7. In addition, an ultrasmall size of $0.68~lambda _{text {g}} times 0.44~lambda _{text {g}} times 0.05~lambda _{text {g}}$ is achieved, where $lambda _{text {g}}$ is the guide wavelength at 2 GHz.
{"title":"A 20-W 1.4–5-GHz Self-Packaged Power Amplifier Using Hybrid Integrated Suspended Line Technology and a Compensated Distributed Balun Network","authors":"Yuanjun Chai;Kaixue Ma;Yongqiang Wang;Feng Feng;Ningning Yan","doi":"10.1109/TCPMT.2025.3559013","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3559013","url":null,"abstract":"This article presents a 20-W 1.4–5-GHz self-packaged differential power amplifier (PA) using hybrid integrated suspended line (HISL) technology and a compensated distributed balun network that provides the PA optimum load impedance over a wide bandwidth. First, a compensated distributed balun network consisting of two coupled-line sections with compact inductors and capacitors for broadband board-level PAs is proposed. The network extends the bandwidth of board-level two-way PAs by 36.6%~71.6% compared to the same type of PAs and overcomes the challenges of integrating baluns with large packaged power devices with significant parasitics across wide bandwidths by trapezoidal capacitors. Second, closed-form design solutions and design parameters on this new network are derived and analyzed comprehensively to guide the design. Third, the proposed network is designed based on HISL, which is for low loss, small size, and self-packaging. As a proof of concept, a broadband high-gain ultrasmall differential PA with three stages is designed and implemented based on HISL technology, which demonstrates excellent performance and self-packaging. The implemented PA achieves the saturated output power (<inline-formula> <tex-math>${P} _{text {sat}}$ </tex-math></inline-formula>) of 40.5–44.6 dBm with maximum power added efficiency (PAE) of 24.4%–58.3% and 20–28.9-dB power gain from 1.4 to 5 GHz. With a fractional bandwidth over 110%, the PA exhibits a competitive figure of merit (FoM) of 96.7. In addition, an ultrasmall size of <inline-formula> <tex-math>$0.68~lambda _{text {g}} times 0.44~lambda _{text {g}} times 0.05~lambda _{text {g}}$ </tex-math></inline-formula> is achieved, where <inline-formula> <tex-math>$lambda _{text {g}}$ </tex-math></inline-formula> is the guide wavelength at 2 GHz.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"2019-2032"},"PeriodicalIF":3.0,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A full-metal millimeter-wave (mmWave) filtering power divider (FPD) featuring sharp roll-off skirt which employs rectangular waveguide (RW) spoof surface plasmon polariton (SSPP) structure is proposed in this article. Both upper and lower cut-off frequencies depend on the dimensions of RW-SSPP unit cells, realizing excellent filtering characteristic. The TE10 mode electromagnetic (EM) wave input in the RW is first converted to SSPP12 mode by loading double-sided RW-SSPP structure, which is finally transformed to two SSPP11 modes through single-sided RW-SSPP structure. To validate the proposed concept, a prototype is fabricated and measured. The proposed FPD achieves a wide 3-dB bandwidth from 22.1 to 27.5 GHz with a 30-dB shape factor (SF) of about 1.15, implying a sharp roll-off skirt. The measured return loss and insertion loss are less than 10 and 1 dB within the operation bandwidth, respectively. The measured phase and magnitude imbalances between the two output ports maintains below 11° and 0.68 dB, respectively.
{"title":"Millimeter-Wave Filtering Power Divider With Sharp Roll-Off Skirt Using Rectangular Waveguide-Spoof Surface Plasmon Polariton Structure","authors":"Jianxing Li;Siyuan Lv;Weiyu He;Qinlong Li;Sen Yan;Kai-Da Xu","doi":"10.1109/TCPMT.2025.3559133","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3559133","url":null,"abstract":"A full-metal millimeter-wave (mmWave) filtering power divider (FPD) featuring sharp roll-off skirt which employs rectangular waveguide (RW) spoof surface plasmon polariton (SSPP) structure is proposed in this article. Both upper and lower cut-off frequencies depend on the dimensions of RW-SSPP unit cells, realizing excellent filtering characteristic. The TE<sub>10</sub> mode electromagnetic (EM) wave input in the RW is first converted to SSPP<sub>12</sub> mode by loading double-sided RW-SSPP structure, which is finally transformed to two SSPP<sub>11</sub> modes through single-sided RW-SSPP structure. To validate the proposed concept, a prototype is fabricated and measured. The proposed FPD achieves a wide 3-dB bandwidth from 22.1 to 27.5 GHz with a 30-dB shape factor (SF) of about 1.15, implying a sharp roll-off skirt. The measured return loss and insertion loss are less than 10 and 1 dB within the operation bandwidth, respectively. The measured phase and magnitude imbalances between the two output ports maintains below 11° and 0.68 dB, respectively.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1454-1461"},"PeriodicalIF":2.3,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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