Pub Date : 2025-04-11DOI: 10.1109/TCPMT.2025.3553725
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information","authors":"","doi":"10.1109/TCPMT.2025.3553725","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3553725","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 4","pages":"C2-C2"},"PeriodicalIF":2.3,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10964063","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143820334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-10DOI: 10.1109/TCPMT.2025.3559525
M. Asaduz Zaman Mamun;Amar Mavinkurve;René Rongen;Michiel van Soestbergen;Muhammad A. Alam
Since the 1950s, and continuing to the present day, wirebond (WB) has remained the most popular interconnection technology. WB is known for its cost-effectiveness, proven reliability, and ease of processing. WB process has advanced significantly with modern developments, such as full automation and optimization of epoxy mold compounds (EMCs). However, mainstream CuAl WB contacts are susceptible to corrosion failures, triggered by the transport and localization of ionic species within the EMCs. The failure is primarily driven by applied bias but exacerbated by environmental factors, such as high relative humidity (RH) and temperature (T). In this scenario, a physics-based generalized failure model for WB corrosion has the potential to offer a robust and standardized qualification approach, streamline the testing process, and facilitate any future WB scaling. In this study, we: i) investigate the in situ ion migration behavior in the EMC using our proposed leakage current-based strategy; ii) simulate and analytically approximate the transient space charge accumulation in the WB-EMC interface; iii) integrate the insights from the simulations and the assumption of a first-order redox reaction into a failure distribution model; and iv) validate the model with integrated circuit (IC) failure data from accelerated tests. The resulting model would serve as a versatile predictive tool for qualifying WB technology.
{"title":"Wirebond Corrosion Failure of Plastic Packages in Extreme Environments: Theory and Experiment","authors":"M. Asaduz Zaman Mamun;Amar Mavinkurve;René Rongen;Michiel van Soestbergen;Muhammad A. Alam","doi":"10.1109/TCPMT.2025.3559525","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3559525","url":null,"abstract":"Since the 1950s, and continuing to the present day, wirebond (WB) has remained the most popular interconnection technology. WB is known for its cost-effectiveness, proven reliability, and ease of processing. WB process has advanced significantly with modern developments, such as full automation and optimization of epoxy mold compounds (EMCs). However, mainstream CuAl WB contacts are susceptible to corrosion failures, triggered by the transport and localization of ionic species within the EMCs. The failure is primarily driven by applied bias but exacerbated by environmental factors, such as high relative humidity (RH) and temperature (<italic>T</i>). In this scenario, a physics-based generalized failure model for WB corrosion has the potential to offer a robust and standardized qualification approach, streamline the testing process, and facilitate any future WB scaling. In this study, we: i) investigate the in situ ion migration behavior in the EMC using our proposed leakage current-based strategy; ii) simulate and analytically approximate the transient space charge accumulation in the WB-EMC interface; iii) integrate the insights from the simulations and the assumption of a first-order redox reaction into a failure distribution model; and iv) validate the model with integrated circuit (IC) failure data from accelerated tests. The resulting model would serve as a versatile predictive tool for qualifying WB technology.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1213-1221"},"PeriodicalIF":2.3,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-10DOI: 10.1109/TCPMT.2025.3559561
Naibo Zhang;Ze Yan;Ke Han;Guangyao Yang;Qiuquan Guo;Ruiliang Song;Zhongliang Deng;Jun Yang
This article demonstrates an integrated wide-angle scanning planar phased array based on pattern reconfigurable antennas (PRAs). The PRA unit consists of four rotationally symmetrical elements with a dimension less than $0.41~lambda times 0.41~lambda $ . By exciting different elements, the beam of the unit switches between four modes and has a 3 dB coverage of ±77°, which helps the antenna array achieve an expanded scanning range. The reconfigurable principle and bandwidth enhancement method of the compact antenna unit are analyzed; the radiation efficiency and the performances of the array are also discussed. The whole system of the phased array is integrated on a multilayer hybrid PCB board, which includes a $4times 4$ reconfigurable antenna array, TR modules, 4-channel RF chips, a beam control circuit, and a power management circuit. The measured return loss of the antenna unit is less than −10 dB in the frequency range of 27–30 GHz, and the scanning range is from −68° to 68° with a maximum gain of 16.4 dBi. The gain fluctuation of the array in beam scanning is less than 2 dB, and the scanning range of −3 dB covers ±80°.
{"title":"An Integrated Wide-Angle Scanning Planar Phased Array Based on Pattern Reconfigurable Antenna","authors":"Naibo Zhang;Ze Yan;Ke Han;Guangyao Yang;Qiuquan Guo;Ruiliang Song;Zhongliang Deng;Jun Yang","doi":"10.1109/TCPMT.2025.3559561","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3559561","url":null,"abstract":"This article demonstrates an integrated wide-angle scanning planar phased array based on pattern reconfigurable antennas (PRAs). The PRA unit consists of four rotationally symmetrical elements with a dimension less than <inline-formula> <tex-math>$0.41~lambda times 0.41~lambda $ </tex-math></inline-formula>. By exciting different elements, the beam of the unit switches between four modes and has a 3 dB coverage of ±77°, which helps the antenna array achieve an expanded scanning range. The reconfigurable principle and bandwidth enhancement method of the compact antenna unit are analyzed; the radiation efficiency and the performances of the array are also discussed. The whole system of the phased array is integrated on a multilayer hybrid PCB board, which includes a <inline-formula> <tex-math>$4times 4$ </tex-math></inline-formula> reconfigurable antenna array, TR modules, 4-channel RF chips, a beam control circuit, and a power management circuit. The measured return loss of the antenna unit is less than −10 dB in the frequency range of 27–30 GHz, and the scanning range is from −68° to 68° with a maximum gain of 16.4 dBi. The gain fluctuation of the array in beam scanning is less than 2 dB, and the scanning range of −3 dB covers ±80°.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1307-1318"},"PeriodicalIF":2.3,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A full-metal millimeter-wave (mmWave) filtering power divider (FPD) featuring sharp roll-off skirt which employs rectangular waveguide (RW) spoof surface plasmon polariton (SSPP) structure is proposed in this article. Both upper and lower cut-off frequencies depend on the dimensions of RW-SSPP unit cells, realizing excellent filtering characteristic. The TE10 mode electromagnetic (EM) wave input in the RW is first converted to SSPP12 mode by loading double-sided RW-SSPP structure, which is finally transformed to two SSPP11 modes through single-sided RW-SSPP structure. To validate the proposed concept, a prototype is fabricated and measured. The proposed FPD achieves a wide 3-dB bandwidth from 22.1 to 27.5 GHz with a 30-dB shape factor (SF) of about 1.15, implying a sharp roll-off skirt. The measured return loss and insertion loss are less than 10 and 1 dB within the operation bandwidth, respectively. The measured phase and magnitude imbalances between the two output ports maintains below 11° and 0.68 dB, respectively.
{"title":"Millimeter-Wave Filtering Power Divider With Sharp Roll-Off Skirt Using Rectangular Waveguide-Spoof Surface Plasmon Polariton Structure","authors":"Jianxing Li;Siyuan Lv;Weiyu He;Qinlong Li;Sen Yan;Kai-Da Xu","doi":"10.1109/TCPMT.2025.3559133","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3559133","url":null,"abstract":"A full-metal millimeter-wave (mmWave) filtering power divider (FPD) featuring sharp roll-off skirt which employs rectangular waveguide (RW) spoof surface plasmon polariton (SSPP) structure is proposed in this article. Both upper and lower cut-off frequencies depend on the dimensions of RW-SSPP unit cells, realizing excellent filtering characteristic. The TE<sub>10</sub> mode electromagnetic (EM) wave input in the RW is first converted to SSPP<sub>12</sub> mode by loading double-sided RW-SSPP structure, which is finally transformed to two SSPP<sub>11</sub> modes through single-sided RW-SSPP structure. To validate the proposed concept, a prototype is fabricated and measured. The proposed FPD achieves a wide 3-dB bandwidth from 22.1 to 27.5 GHz with a 30-dB shape factor (SF) of about 1.15, implying a sharp roll-off skirt. The measured return loss and insertion loss are less than 10 and 1 dB within the operation bandwidth, respectively. The measured phase and magnitude imbalances between the two output ports maintains below 11° and 0.68 dB, respectively.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1454-1461"},"PeriodicalIF":2.3,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-09DOI: 10.1109/TCPMT.2025.3559013
Yuanjun Chai;Kaixue Ma;Yongqiang Wang;Feng Feng;Ningning Yan
This article presents a 20-W 1.4–5-GHz self-packaged differential power amplifier (PA) using hybrid integrated suspended line (HISL) technology and a compensated distributed balun network that provides the PA optimum load impedance over a wide bandwidth. First, a compensated distributed balun network consisting of two coupled-line sections with compact inductors and capacitors for broadband board-level PAs is proposed. The network extends the bandwidth of board-level two-way PAs by 36.6%~71.6% compared to the same type of PAs and overcomes the challenges of integrating baluns with large packaged power devices with significant parasitics across wide bandwidths by trapezoidal capacitors. Second, closed-form design solutions and design parameters on this new network are derived and analyzed comprehensively to guide the design. Third, the proposed network is designed based on HISL, which is for low loss, small size, and self-packaging. As a proof of concept, a broadband high-gain ultrasmall differential PA with three stages is designed and implemented based on HISL technology, which demonstrates excellent performance and self-packaging. The implemented PA achieves the saturated output power (${P} _{text {sat}}$ ) of 40.5–44.6 dBm with maximum power added efficiency (PAE) of 24.4%–58.3% and 20–28.9-dB power gain from 1.4 to 5 GHz. With a fractional bandwidth over 110%, the PA exhibits a competitive figure of merit (FoM) of 96.7. In addition, an ultrasmall size of $0.68~lambda _{text {g}} times 0.44~lambda _{text {g}} times 0.05~lambda _{text {g}}$ is achieved, where $lambda _{text {g}}$ is the guide wavelength at 2 GHz.
{"title":"A 20-W 1.4–5-GHz Self-Packaged Power Amplifier Using Hybrid Integrated Suspended Line Technology and a Compensated Distributed Balun Network","authors":"Yuanjun Chai;Kaixue Ma;Yongqiang Wang;Feng Feng;Ningning Yan","doi":"10.1109/TCPMT.2025.3559013","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3559013","url":null,"abstract":"This article presents a 20-W 1.4–5-GHz self-packaged differential power amplifier (PA) using hybrid integrated suspended line (HISL) technology and a compensated distributed balun network that provides the PA optimum load impedance over a wide bandwidth. First, a compensated distributed balun network consisting of two coupled-line sections with compact inductors and capacitors for broadband board-level PAs is proposed. The network extends the bandwidth of board-level two-way PAs by 36.6%~71.6% compared to the same type of PAs and overcomes the challenges of integrating baluns with large packaged power devices with significant parasitics across wide bandwidths by trapezoidal capacitors. Second, closed-form design solutions and design parameters on this new network are derived and analyzed comprehensively to guide the design. Third, the proposed network is designed based on HISL, which is for low loss, small size, and self-packaging. As a proof of concept, a broadband high-gain ultrasmall differential PA with three stages is designed and implemented based on HISL technology, which demonstrates excellent performance and self-packaging. The implemented PA achieves the saturated output power (<inline-formula> <tex-math>${P} _{text {sat}}$ </tex-math></inline-formula>) of 40.5–44.6 dBm with maximum power added efficiency (PAE) of 24.4%–58.3% and 20–28.9-dB power gain from 1.4 to 5 GHz. With a fractional bandwidth over 110%, the PA exhibits a competitive figure of merit (FoM) of 96.7. In addition, an ultrasmall size of <inline-formula> <tex-math>$0.68~lambda _{text {g}} times 0.44~lambda _{text {g}} times 0.05~lambda _{text {g}}$ </tex-math></inline-formula> is achieved, where <inline-formula> <tex-math>$lambda _{text {g}}$ </tex-math></inline-formula> is the guide wavelength at 2 GHz.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"2019-2032"},"PeriodicalIF":3.0,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-09DOI: 10.1109/TCPMT.2025.3558669
Tarek Gebrael;Arielle R. Gamboa;Muhammad Jahidul Hoque;Shayan Aflatounian;David Huitink;Robert Pilawa-Podgurski;Nenad Miljkovic
Power densification is making thermal design a key step in the development of future electrical devices. Systems such as data centers and electric vehicles are generating more heat, which requires efficient cooling to maintain the electronics at temperatures below their limits and to ensure reliability. Immersion cooling has emerged as a promising thermal management technique that brings the coolant closer to the heat-generating elements, hence reducing thermal impedance and improving cooling. Although the dielectric liquid coolants used in immersion cooling do not compromise the electrical performance of the submerged electrical devices, their cooling performance is inferior compared to ideal coolants such as water. To use water as an immersion coolant, the electronics need to be encapsulated to prevent short circuits. Here, a packaging approach is developed that insulates the electronics from the surrounding water and spreads heat for better cooling. The package consists of an aluminum nitride (AlN) component for insulation and heat spreading, and a Parylene C coating for conformal electrical insulation. The package is characterized electrically by measuring the leakage current in water under dc voltages up to 600 V for periods of up to seven days. The thermal performance of this packaging method is also characterized by calculating the junction-to-coolant thermal resistance. The developed packaging design can be implemented in high-power-density applications where the heat flux is beyond what standard dielectric fluids can handle.
{"title":"Thermally Conductive Electrically Insulating Electronics Packaging for Water Immersion Cooling","authors":"Tarek Gebrael;Arielle R. Gamboa;Muhammad Jahidul Hoque;Shayan Aflatounian;David Huitink;Robert Pilawa-Podgurski;Nenad Miljkovic","doi":"10.1109/TCPMT.2025.3558669","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3558669","url":null,"abstract":"Power densification is making thermal design a key step in the development of future electrical devices. Systems such as data centers and electric vehicles are generating more heat, which requires efficient cooling to maintain the electronics at temperatures below their limits and to ensure reliability. Immersion cooling has emerged as a promising thermal management technique that brings the coolant closer to the heat-generating elements, hence reducing thermal impedance and improving cooling. Although the dielectric liquid coolants used in immersion cooling do not compromise the electrical performance of the submerged electrical devices, their cooling performance is inferior compared to ideal coolants such as water. To use water as an immersion coolant, the electronics need to be encapsulated to prevent short circuits. Here, a packaging approach is developed that insulates the electronics from the surrounding water and spreads heat for better cooling. The package consists of an aluminum nitride (AlN) component for insulation and heat spreading, and a Parylene C coating for conformal electrical insulation. The package is characterized electrically by measuring the leakage current in water under dc voltages up to 600 V for periods of up to seven days. The thermal performance of this packaging method is also characterized by calculating the junction-to-coolant thermal resistance. The developed packaging design can be implemented in high-power-density applications where the heat flux is beyond what standard dielectric fluids can handle.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1222-1236"},"PeriodicalIF":2.3,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10959096","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-07DOI: 10.1109/TCPMT.2025.3558532
Jin-Tai Yan
It is known that ordered escape routing becomes more important in printed circuit board (PCB) designs. In this article, given a set of escape pins with some buses under bus-direction constraints inside a pin array, a set of available boundaries, and the capacity constraint between two adjacent pins, bus-aware ordered escape routing (BOER) under bus-direction constraints can be formulated and an efficient algorithm can be proposed to solve the routing problem. In ordered escape routing for the given buses, based on the locations of the escape pins for any bus with its bus-direction constraint, the target pins of the unrouted nets inside the bus can be first assigned onto the constrained boundary for length minimization and the unrouted nets inside the bus can be further routed for skew minimization. In ordered escape routing for the remaining nets, based on the routing results of the given buses as obstacles and the division of the remaining routing space, the remaining unrouted nets can be first partitioned into some net sets and the nets inside any net set can be further routed inside its specific routing region. Compared with Luo’s SAT-based algorithm, Jiao’s flow-based algorithm, and Yan’s algorithm with no bus-direction consideration, the proposed algorithm can obtain the 100% routability of the escape nets and reduces 38.6%, 34.4%, and 28.9% of the number of the violated buses on the average for the six tested examples with capacity as 1, respectively. Additionally, compared with Yan’s algorithm with no bus-direction consideration, the proposed algorithm can also achieve 100% routability of the escape nets and reduces 37.3% of the number of the violated buses on the average for the other six tested examples with capacity as 2.
{"title":"Bus-Aware Ordered Escape Routing Under Bus-Direction Constraints","authors":"Jin-Tai Yan","doi":"10.1109/TCPMT.2025.3558532","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3558532","url":null,"abstract":"It is known that ordered escape routing becomes more important in printed circuit board (PCB) designs. In this article, given a set of escape pins with some buses under bus-direction constraints inside a pin array, a set of available boundaries, and the capacity constraint between two adjacent pins, bus-aware ordered escape routing (BOER) under bus-direction constraints can be formulated and an efficient algorithm can be proposed to solve the routing problem. In ordered escape routing for the given buses, based on the locations of the escape pins for any bus with its bus-direction constraint, the target pins of the unrouted nets inside the bus can be first assigned onto the constrained boundary for length minimization and the unrouted nets inside the bus can be further routed for skew minimization. In ordered escape routing for the remaining nets, based on the routing results of the given buses as obstacles and the division of the remaining routing space, the remaining unrouted nets can be first partitioned into some net sets and the nets inside any net set can be further routed inside its specific routing region. Compared with Luo’s SAT-based algorithm, Jiao’s flow-based algorithm, and Yan’s algorithm with no bus-direction consideration, the proposed algorithm can obtain the 100% routability of the escape nets and reduces 38.6%, 34.4%, and 28.9% of the number of the violated buses on the average for the six tested examples with capacity as 1, respectively. Additionally, compared with Yan’s algorithm with no bus-direction consideration, the proposed algorithm can also achieve 100% routability of the escape nets and reduces 37.3% of the number of the violated buses on the average for the other six tested examples with capacity as 2.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1292-1306"},"PeriodicalIF":2.3,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-07DOI: 10.1109/TCPMT.2025.3558701
Ioannis Mantis;Kapil Kumar Gupta;Rajan Ambat
In the presented work, the accumulative effect of different manufacturing steps of printed circuit board (PCB) on conformal coating performance is evaluated. An interdigitated comb pattern on an FR-4 board was used as a test PCB. Manufacturing processes included base test PCB produced by three different manufacturers (Man) incorporating copper-clad lamination (CCL) and hot air solder leveling (HASL) steps. In addition, test boards underwent typical wave solder and selective mini-wave steps. Commercial co-polymer polyurethane/polyacrylate and urethane acrylate conformal coatings were applied on test boards before as well as after soldering process. The study aims to evaluate induced contamination on the PCB surface after these manufacturing steps and the effect of PCB surface cleanliness on the protection performance of conformal coating under humidity. The results revealed chloride residues prior to soldering on the PCB surface with variations across Man-1 ($0.2~mu $ g/cm2), Man-2 ($0.4~mu $ g/cm2), and Man-3 ($0.8~mu $ g/cm2). In surface insulation resistance (SIR) measurements under humidity exposure, Man-3 exhibited 100% failure caused by dendrite formation, with resistance levels consistently over a decade lower than Man-1, highlighting the quality of the base PCB materials as a major factor for humidity-related issues. Equal importance was found regarding different wave soldering methods and coatings. However, the initial contamination present dominated over subsequent manufacturing steps with the highest chloride contamination resulting in up to one decade difference depending on the flux and coating chemistries.
{"title":"Effect of PCB Manufacturing Process Step-Related Cleanliness on Performance of Conformal Coating","authors":"Ioannis Mantis;Kapil Kumar Gupta;Rajan Ambat","doi":"10.1109/TCPMT.2025.3558701","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3558701","url":null,"abstract":"In the presented work, the accumulative effect of different manufacturing steps of printed circuit board (PCB) on conformal coating performance is evaluated. An interdigitated comb pattern on an FR-4 board was used as a test PCB. Manufacturing processes included base test PCB produced by three different manufacturers (Man) incorporating copper-clad lamination (CCL) and hot air solder leveling (HASL) steps. In addition, test boards underwent typical wave solder and selective mini-wave steps. Commercial co-polymer polyurethane/polyacrylate and urethane acrylate conformal coatings were applied on test boards before as well as after soldering process. The study aims to evaluate induced contamination on the PCB surface after these manufacturing steps and the effect of PCB surface cleanliness on the protection performance of conformal coating under humidity. The results revealed chloride residues prior to soldering on the PCB surface with variations across Man-1 (<inline-formula> <tex-math>$0.2~mu $ </tex-math></inline-formula>g/cm<sup>2</sup>), Man-2 (<inline-formula> <tex-math>$0.4~mu $ </tex-math></inline-formula>g/cm<sup>2</sup>), and Man-3 (<inline-formula> <tex-math>$0.8~mu $ </tex-math></inline-formula>g/cm<sup>2</sup>). In surface insulation resistance (SIR) measurements under humidity exposure, Man-3 exhibited 100% failure caused by dendrite formation, with resistance levels consistently over a decade lower than Man-1, highlighting the quality of the base PCB materials as a major factor for humidity-related issues. Equal importance was found regarding different wave soldering methods and coatings. However, the initial contamination present dominated over subsequent manufacturing steps with the highest chloride contamination resulting in up to one decade difference depending on the flux and coating chemistries.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1367-1375"},"PeriodicalIF":2.3,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-04DOI: 10.1109/TCPMT.2025.3557270
Ming-Lang Tseng;Nima E. Gorji
X-ray diffraction (XRD) mapping is a nondestructive metrology technique that enables the reconstruction of warpage induced on a silicon wafer through thermomechanical stress. Here, we mapped the wafer’s warpage using a methodology based on a series of line scans in the x- and y-directions and at different 90° rotations of the same sample. These line scans collect rocking curves (RCs) from the wafer’s surface, recording the diffraction angle ($omega $ ) deviated from the Bragg angle due to surface misorientation. The surface warpage reflects in XRD measurements by inducing a difference between the measured diffraction angle and the reference Bragg angle ($omega - omega _{0}$ ) and RC broadening full-width at half-maximum (FWHM). By collecting and integrating the RCs and FWHM broadening from the whole surface and multiple rotations of the wafer, we could generate 3-D maps of the surface function $f(x)$ and the angular misorientation (warpage). The warpage exhibits a convex shape, aligning with optical profilometry measurements reported in the literature. The lab-based XRD imaging (XRDI) has the potential to be developed to map the wafer’s warpage in a shorter time and in situ, as can be perfectly performed in synchrotron radiation source.
{"title":"Metrology of Warpage in Silicon Wafers Using X-Ray Diffraction Mapping","authors":"Ming-Lang Tseng;Nima E. Gorji","doi":"10.1109/TCPMT.2025.3557270","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3557270","url":null,"abstract":"X-ray diffraction (XRD) mapping is a nondestructive metrology technique that enables the reconstruction of warpage induced on a silicon wafer through thermomechanical stress. Here, we mapped the wafer’s warpage using a methodology based on a series of line scans in the <italic>x</i>- and <italic>y</i>-directions and at different 90° rotations of the same sample. These line scans collect rocking curves (<italic>RC</i>s) from the wafer’s surface, recording the diffraction angle (<inline-formula> <tex-math>$omega $ </tex-math></inline-formula>) deviated from the Bragg angle due to surface misorientation. The surface warpage reflects in XRD measurements by inducing a difference between the measured diffraction angle and the reference Bragg angle (<inline-formula> <tex-math>$omega - omega _{0}$ </tex-math></inline-formula>) and <italic>RC</i> broadening full-width at half-maximum (FWHM). By collecting and integrating the <italic>RC</i>s and FWHM broadening from the whole surface and multiple rotations of the wafer, we could generate 3-D maps of the surface function <inline-formula> <tex-math>$f(x)$ </tex-math></inline-formula> and the angular misorientation (warpage). The warpage exhibits a convex shape, aligning with optical profilometry measurements reported in the literature. The lab-based XRD imaging (XRDI) has the potential to be developed to map the wafer’s warpage in a shorter time and in situ, as can be perfectly performed in synchrotron radiation source.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1523-1528"},"PeriodicalIF":2.3,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1109/TCPMT.2025.3557461
Qi Zhang;Yazi Cao;Mingcong Zheng;Shichang Chen;Gaofeng Wang
On-chip bandpass filter (BPF) designs with high out-of-band rejection are proposed by virtue of 3-D glass-based advanced packaging technology. The proposed BPF design employs multiple coupling cells based on a combination of new mixed 2-D and 3-D coupling structures. It can generate multiple transmission zeros (TZs) and transmission poles (TPs). With these generated TZs, the out-of-band rejection of the proposed BPF designs can be greatly improved. The equivalent circuit model is developed and used for theoretical analysis. To prove the concept, two BPFs are designed and fabricated using 3-D glass-based advanced packaging technology. These two fabricated BPFs have center frequencies of 6.55 and 6.2 GHz and fractional bandwidths (FBWs) of 10.69% and 8%, respectively. These two BPFs can achieve insertion losses lower than 2.5 and 2.9 dB, return losses better than 10 and 13 dB, and more than 20-dB rejection up to 16.15 and 17.8 GHz. The sizes of the two BPFs are $2.1times 2.0times 0.35$ mm and $2.3times 4.3times 0.35$ mm. The simulation and measured results show good consistency.
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