Pub Date : 2025-06-04DOI: 10.1109/TCPMT.2025.3576350
Jin Wu;Yuefeng Hou;Liqi Yang;Zhenshuai Fu;Meicheng Liu;Dawei Zhang;Mingtao Zhang;Kaixue Ma
A low-loss and self-packaged full phase shift reflection-type phase shifter (RTPS) based on the hybrid integrated suspended line (HISL) technology is introduced. The proposed RTPS consists of a 90° branch line coupler and two tunable parallel L–C loads connected to the through port and coupled ports. First, an enhanced two-step phase extraction method is proposed, reducing the evaluation state of the RTPS and achieving the minimal phase step while keeping the number of states unchanged. Second, the HISL technology is adopted in the design to achieve low insertion loss (IL). Due to the self-packaging characteristics of HISL, the proposed RTPS effectively avoids interference with surrounding circuits and is highly integrated. Third, the low-power digital tunable capacitor (DTC) with a bus interface is used as the tunable load, making the RTPS easy to integrate into large-scale phased array systems. Finally, a prototype is fabricated by using the sheet metal and PCB process. At the center frequency of 2.45 GHz, the proposed RTPS achieved a measured phase shift range (PSR) of 368° under 128 sweeping states with an IL of 0.9–1.6 dB, and the figure of merit (FoM) is 230°/dB.
{"title":"Low-Loss Self-Packaged Full Phase Shift Reflection-Type Phase Shifter Based on Hybrid Integrated Suspended Line Technology","authors":"Jin Wu;Yuefeng Hou;Liqi Yang;Zhenshuai Fu;Meicheng Liu;Dawei Zhang;Mingtao Zhang;Kaixue Ma","doi":"10.1109/TCPMT.2025.3576350","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3576350","url":null,"abstract":"A low-loss and self-packaged full phase shift reflection-type phase shifter (RTPS) based on the hybrid integrated suspended line (HISL) technology is introduced. The proposed RTPS consists of a 90° branch line coupler and two tunable parallel <italic>L</i>–<italic>C</i> loads connected to the through port and coupled ports. First, an enhanced two-step phase extraction method is proposed, reducing the evaluation state of the RTPS and achieving the minimal phase step while keeping the number of states unchanged. Second, the HISL technology is adopted in the design to achieve low insertion loss (IL). Due to the self-packaging characteristics of HISL, the proposed RTPS effectively avoids interference with surrounding circuits and is highly integrated. Third, the low-power digital tunable capacitor (DTC) with a bus interface is used as the tunable load, making the RTPS easy to integrate into large-scale phased array systems. Finally, a prototype is fabricated by using the sheet metal and PCB process. At the center frequency of 2.45 GHz, the proposed RTPS achieved a measured phase shift range (PSR) of 368° under 128 sweeping states with an IL of 0.9–1.6 dB, and the figure of merit (FoM) is 230°/dB.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"2010-2018"},"PeriodicalIF":3.0,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-28DOI: 10.1109/TCPMT.2025.3564833
Xinyue Chang;Bjorn Vermeersch;Herman Oprins;Melina Lofrano;Vladimir Cherman;Seongho Park;Zsolt Tokei;Ingrid De Wolf
In this article, we introduce a modular thermal modeling methodology, BTE-FEM, that combines the Boltzmann transport equation (BTE) with finite element modeling (FEM) for simulations of advanced back-end-of-line (BEOL) stacks with high accuracy and efficiency. BTE-FEM is validated against direct BTE-based simulations using simplified BEOL stack test cases across various technology nodes and via connectivity configurations. It is demonstrated that conventional FEM, using bulk material properties, increasingly underestimates the BEOL thermal resistance as the technology node scales. In contrast, the BTE-FEM developed in this study demonstrates good agreement with direct BTE simulations for all test cases, but at much shorter runtimes. The impact of material properties, metal densities, and boundary conditions on the derived BEOL thermal properties are benchmarked and the developed models are experimentally validated at two distinct technology nodes. Finally, the developed methodology is applied to a 12-layer, 18 nm metal pitch BEOL stack from an A10 high density core design, demonstrating its ability to simulate complex and realistic BEOL routings with the precision of direct BTE simulations while substantially reduced simulation time. This approach enables extensive design of experiments (DOEs) for fast turnaround design iterations.
{"title":"Thermal Modeling and Analysis of Equivalent Thermal Properties for Advanced BEOL Stacks","authors":"Xinyue Chang;Bjorn Vermeersch;Herman Oprins;Melina Lofrano;Vladimir Cherman;Seongho Park;Zsolt Tokei;Ingrid De Wolf","doi":"10.1109/TCPMT.2025.3564833","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3564833","url":null,"abstract":"In this article, we introduce a modular thermal modeling methodology, BTE-FEM, that combines the Boltzmann transport equation (BTE) with finite element modeling (FEM) for simulations of advanced back-end-of-line (BEOL) stacks with high accuracy and efficiency. BTE-FEM is validated against direct BTE-based simulations using simplified BEOL stack test cases across various technology nodes and via connectivity configurations. It is demonstrated that conventional FEM, using bulk material properties, increasingly underestimates the BEOL thermal resistance as the technology node scales. In contrast, the BTE-FEM developed in this study demonstrates good agreement with direct BTE simulations for all test cases, but at much shorter runtimes. The impact of material properties, metal densities, and boundary conditions on the derived BEOL thermal properties are benchmarked and the developed models are experimentally validated at two distinct technology nodes. Finally, the developed methodology is applied to a 12-layer, 18 nm metal pitch BEOL stack from an A10 high density core design, demonstrating its ability to simulate complex and realistic BEOL routings with the precision of direct BTE simulations while substantially reduced simulation time. This approach enables extensive design of experiments (DOEs) for fast turnaround design iterations.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"1708-1716"},"PeriodicalIF":3.0,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144891152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-28DOI: 10.1109/TCPMT.2025.3563936
Lifang Zhao;Kaixue Ma;Yongqiang Wang
The millimeter-wave micro-transmission line with GSG turning point is designed and prepared in this letter. The circuit breaking problem occurs in the initial measurement. Through the thermal stress analysis, material interface matching, and process improvement, the tested insertion loss at 40 GHz is 0.2 dB/cm, and the reflection loss is better than 17.32 dB. After three thermal reflow at $220~^{circ }$ C and 500 h high-temperature storage at $150~^{circ }$ C, there is no obvious difference between the performance tests before and after. It shows that the structure stability of the millimeter wave micro-transmission line is very good, which provides a reference solution for the key technical problems in the preparation process of micro-transmission line and reliability verification.
本文设计并制作了具有GSG拐点的毫米波微传输线。在初始测量中会出现断路问题。通过热应力分析、材料界面匹配和工艺改进，测试的40 GHz插入损耗为0.2 dB/cm，反射损耗优于17.32 dB。经过$220~^{circ}$ C三次热回流和$150~^{circ}$ C 500 h的高温贮存，前后性能测试无明显差异。结果表明，该毫米波微传输线的结构稳定性非常好，为微传输线制备过程中的关键技术问题和可靠性验证提供了参考解决方案。
{"title":"Reliability Analysis of MEMS Millimeter-Wave Micro-Transmission Line","authors":"Lifang Zhao;Kaixue Ma;Yongqiang Wang","doi":"10.1109/TCPMT.2025.3563936","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3563936","url":null,"abstract":"The millimeter-wave micro-transmission line with GSG turning point is designed and prepared in this letter. The circuit breaking problem occurs in the initial measurement. Through the thermal stress analysis, material interface matching, and process improvement, the tested insertion loss at 40 GHz is 0.2 dB/cm, and the reflection loss is better than 17.32 dB. After three thermal reflow at <inline-formula> <tex-math>$220~^{circ }$ </tex-math></inline-formula>C and 500 h high-temperature storage at <inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>C, there is no obvious difference between the performance tests before and after. It shows that the structure stability of the millimeter wave micro-transmission line is very good, which provides a reference solution for the key technical problems in the preparation process of micro-transmission line and reliability verification.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1269-1274"},"PeriodicalIF":2.3,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study investigates the bonding mechanisms between cold gas-sprayed (CGS) copper (Cu) particles and aluminum nitride (AlN) substrates. A 300-$mu $ m-thick Cu coating was successfully deposited and characterized by electron backscatter diffraction (EBSD) techniques revealing microstructural evolution differences between the bulk of the Cu coating and the Cu/AlN interface. The Cu/AlN interface showed finer, homogeneous grains, and the evidence of dynamic recrystallization, while the distal portion of the coating exhibited larger, heterogeneous grains with higher intragranular strains. Image quality (IQ) maps and grain orientation spread analysis confirmed lower strains at the Cu/AlN interface that correlated with smaller microhardness readings suggesting a recrystallization phenomenon. Finite-element simulations of particle impact revealed large plastic deformations, jetting, and a thermal response surpassing the recrystallization temperature of copper. These findings are indicative of a bonding mechanism involving mechanical interlocking and dynamic recrystallization at the Cu/AlN interface. The roughened AlN substrate, with an average surface roughness (Sa) of $0.5~mu $ m, promoted mechanical interlocking, thus enhancing adhesion. This work provides insights into optimizing CGS for metal coatings on ceramic substrates, particularly in electronic packaging applications, where strong metal-ceramic adhesion is critical for reliable operation in harsh environments.
{"title":"Bonding Mechanism of Cold Gas-Sprayed Copper Particles Onto Aluminum Nitride Substrates for Power Electronics Packaging","authors":"Margie Guerrero-Fernandez;Ozan Ozdemir;Zhu Ning;Paul Allison;Brian Jordon;Pedro Quintero","doi":"10.1109/TCPMT.2025.3564520","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3564520","url":null,"abstract":"This study investigates the bonding mechanisms between cold gas-sprayed (CGS) copper (Cu) particles and aluminum nitride (AlN) substrates. A 300-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick Cu coating was successfully deposited and characterized by electron backscatter diffraction (EBSD) techniques revealing microstructural evolution differences between the bulk of the Cu coating and the Cu/AlN interface. The Cu/AlN interface showed finer, homogeneous grains, and the evidence of dynamic recrystallization, while the distal portion of the coating exhibited larger, heterogeneous grains with higher intragranular strains. Image quality (IQ) maps and grain orientation spread analysis confirmed lower strains at the Cu/AlN interface that correlated with smaller microhardness readings suggesting a recrystallization phenomenon. Finite-element simulations of particle impact revealed large plastic deformations, jetting, and a thermal response surpassing the recrystallization temperature of copper. These findings are indicative of a bonding mechanism involving mechanical interlocking and dynamic recrystallization at the Cu/AlN interface. The roughened AlN substrate, with an average surface roughness (Sa) of <inline-formula> <tex-math>$0.5~mu $ </tex-math></inline-formula>m, promoted mechanical interlocking, thus enhancing adhesion. This work provides insights into optimizing CGS for metal coatings on ceramic substrates, particularly in electronic packaging applications, where strong metal-ceramic adhesion is critical for reliable operation in harsh environments.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1511-1522"},"PeriodicalIF":2.3,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-24DOI: 10.1109/TCPMT.2025.3564215
Nicholas Sturim;Premjeet Chahal;Matthew Hodek;John D. Albrecht;John Papapolymerou
This article presents an innovative, fully additive manufactured approach to millimeter-wave multilayer circuits. An aerosol jet printer is used to fabricate a multilayer stepped-impedance low-pass filter. By leveraging the second layer for miniaturization, we achieve a more compact design. By precisely controlling conductor separation and utilizing 3-D printing technology, we were able to optimize the width of the high- and low-impedance segments for optimal filter performance. Two filter types were successfully fabricated: a low-pass microstrip filter and a low-pass stripline filter, both with a cutoff frequency near 29 GHz and exhibiting acceptable stopband attenuation. The stripline configuration allows for a 36% decrease in the stripline waveguide conductor area while achieving a great passband insertion loss of just 0.62 dB, enabled by aerosol jet printing (AJP). The line loss of both designs was characterized using a microstrip through line and a stripline through line. Both designs demonstrated low overall loss, with the microstrip line exhibiting a loss of 0.26 dB/mm and the stripline having a loss of 0.37 dB/mm at 29 GHz. This work demonstrates a multilayer integration solution and offers an advantage in reducing the size of RF circuits such as filter banks for next-generation integrated RF front ends.
{"title":"Miniaturized Millimeter-Wave Multilayer Filter Design Using Additive Manufacturing","authors":"Nicholas Sturim;Premjeet Chahal;Matthew Hodek;John D. Albrecht;John Papapolymerou","doi":"10.1109/TCPMT.2025.3564215","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3564215","url":null,"abstract":"This article presents an innovative, fully additive manufactured approach to millimeter-wave multilayer circuits. An aerosol jet printer is used to fabricate a multilayer stepped-impedance low-pass filter. By leveraging the second layer for miniaturization, we achieve a more compact design. By precisely controlling conductor separation and utilizing 3-D printing technology, we were able to optimize the width of the high- and low-impedance segments for optimal filter performance. Two filter types were successfully fabricated: a low-pass microstrip filter and a low-pass stripline filter, both with a cutoff frequency near 29 GHz and exhibiting acceptable stopband attenuation. The stripline configuration allows for a 36% decrease in the stripline waveguide conductor area while achieving a great passband insertion loss of just 0.62 dB, enabled by aerosol jet printing (AJP). The line loss of both designs was characterized using a microstrip through line and a stripline through line. Both designs demonstrated low overall loss, with the microstrip line exhibiting a loss of 0.26 dB/mm and the stripline having a loss of 0.37 dB/mm at 29 GHz. This work demonstrates a multilayer integration solution and offers an advantage in reducing the size of RF circuits such as filter banks for next-generation integrated RF front ends.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1170-1178"},"PeriodicalIF":2.3,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-22DOI: 10.1109/TCPMT.2025.3563367
Mei-Ling Wu;Che-Wei Kang
This study investigates how local warpage and stress near the sawing lines of quad flat no-lead (QFN) packages, under stringent automotive conditions, influence the wire bonding process. A finite element model, validated through experimental measurements, was developed to quantify deformation and stress distributions along the cutting paths. Three lead frame strip designs—one row one block, multiblock, and one block—were comparatively assessed under both thermal and mechanical loads. Results show that the one row one block design can reduce local deformation by up to 70%–75% (e.g., $45~mu $ m versus $159~mu $ m) compared to the one block configuration, significantly mitigating alignment errors and fatigue risk. Concurrently, its peak local stress is about 212 MPa—a 70% reduction relative to the 708 MPa observed in the one block design. These combined improvements highlight the necessity of balanced structural design in sawing regions to enhance wire bonding stability. Overall, these findings provide a robust framework for optimizing QFN packages under stringent automotive conditions, particularly by refining wire bonding design.
{"title":"Optimization of the Wire Bonding Process for Enhanced Thermomechanical Performance of Quad Flat No-Lead (QFN) Packages in Automotive Applications","authors":"Mei-Ling Wu;Che-Wei Kang","doi":"10.1109/TCPMT.2025.3563367","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3563367","url":null,"abstract":"This study investigates how local warpage and stress near the sawing lines of quad flat no-lead (QFN) packages, under stringent automotive conditions, influence the wire bonding process. A finite element model, validated through experimental measurements, was developed to quantify deformation and stress distributions along the cutting paths. Three lead frame strip designs—one row one block, multiblock, and one block—were comparatively assessed under both thermal and mechanical loads. Results show that the one row one block design can reduce local deformation by up to 70%–75% (e.g., <inline-formula> <tex-math>$45~mu $ </tex-math></inline-formula>m versus <inline-formula> <tex-math>$159~mu $ </tex-math></inline-formula>m) compared to the one block configuration, significantly mitigating alignment errors and fatigue risk. Concurrently, its peak local stress is about 212 MPa—a 70% reduction relative to the 708 MPa observed in the one block design. These combined improvements highlight the necessity of balanced structural design in sawing regions to enhance wire bonding stability. Overall, these findings provide a robust framework for optimizing QFN packages under stringent automotive conditions, particularly by refining wire bonding design.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1417-1424"},"PeriodicalIF":2.3,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-22DOI: 10.1109/TCPMT.2025.3563253
Pengcheng Yin;Jonghwan Ha;Junbo Yang;Karthik Deo;Yangyang Lai;Seungbae Park
By employing optimized outer packaging designs and materials, the impact energy can be effectively absorbed or dissipated, thereby preventing potential damage to interconnections and chips. This includes mitigating solder-joint fractures, chip cracks, pad cratering or lifting, and other mechanical stresses that commonly result from impact forces. To ensure that the internal ionic sensor remains resilient to moisture intrusion and can endure impact velocities of up to 30 mph, advanced packaging solutions have been developed. In this study, the ANSYS/LS-DYNA finite element analysis (FEAs) tool was utilized to evaluate the performance of various packaging designs in minimizing the shock energy transferred to the printed circuit board (PCB). Modifications were made to the external foam packaging to increase the effective thickness and stiffness of the PCB, thus limiting its deformation under impact. These adjustments involved testing several configurations, including a two-layer foam system, a single-layer foam, and variations in the foam material’s stress-strain characteristics. The results demonstrated a significant reduction in PCB deformation—by 86.9%—with the final design achieving a deformation of just $52~mu $ m, compared to $398.7~mu $ m in the initial design. Furthermore, the simulations of the final design were conducted for different drop orientations to ensure that out-of-plane deformations remained within the same order of magnitude, regardless of the drop direction.
{"title":"Enhanced Design of Airborne Radiation Sensor for Improved Survivability During Deployment Impact","authors":"Pengcheng Yin;Jonghwan Ha;Junbo Yang;Karthik Deo;Yangyang Lai;Seungbae Park","doi":"10.1109/TCPMT.2025.3563253","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3563253","url":null,"abstract":"By employing optimized outer packaging designs and materials, the impact energy can be effectively absorbed or dissipated, thereby preventing potential damage to interconnections and chips. This includes mitigating solder-joint fractures, chip cracks, pad cratering or lifting, and other mechanical stresses that commonly result from impact forces. To ensure that the internal ionic sensor remains resilient to moisture intrusion and can endure impact velocities of up to 30 mph, advanced packaging solutions have been developed. In this study, the ANSYS/LS-DYNA finite element analysis (FEAs) tool was utilized to evaluate the performance of various packaging designs in minimizing the shock energy transferred to the printed circuit board (PCB). Modifications were made to the external foam packaging to increase the effective thickness and stiffness of the PCB, thus limiting its deformation under impact. These adjustments involved testing several configurations, including a two-layer foam system, a single-layer foam, and variations in the foam material’s stress-strain characteristics. The results demonstrated a significant reduction in PCB deformation—by 86.9%—with the final design achieving a deformation of just <inline-formula> <tex-math>$52~mu $ </tex-math></inline-formula>m, compared to <inline-formula> <tex-math>$398.7~mu $ </tex-math></inline-formula>m in the initial design. Furthermore, the simulations of the final design were conducted for different drop orientations to ensure that out-of-plane deformations remained within the same order of magnitude, regardless of the drop direction.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1410-1416"},"PeriodicalIF":2.3,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144623875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-17DOI: 10.1109/TCPMT.2025.3561801
Ubade Kemerli;Yogendra Joshi
This study experimentally and computationally investigates the convection heat transfer performance of metal foams (MFs) having the same pores per inch (PPI) but different porosities attached to a uniformly heated surface using three different thermal interface materials (TIMs). Of the three TIMs considered, flexible graphite showed the best heat transfer performance by around 10%–25% compared to the reference case, where no TIM was used, due to its high in-plane thermal conductivity. In contrast, thermal epoxy was the worst, with a decrease in heat transfer by around 10%–30%, relative to the reference case. A comparable performance to the reference case was exhibited by the thermal gap pad. The MF hydraulic modeling parameters were extracted from the pressure drop data, and pore and filament diameters were obtained from micro-CT ($mu $ CT) scans and used in the numerical simulations. Thermal contact resistances (TCRs) are assessed from the numerical simulations. The results showed that total TCR tends to increase with increasing filament diameter and decreasing porosity. Moreover, the steady-state thermal analyses showed that the flexible graphite effectively spreads the heat in the TIM and reduces the overall TCR. Detailed temperature contours on the heated surface of the thermal gap pad and flexible graphite TIMs used with different porosity MFs are presented to support these findings.
{"title":"Thermal Performance of Liquid-Cooled Metal Foams Attached Using Different Thermal Interface Materials","authors":"Ubade Kemerli;Yogendra Joshi","doi":"10.1109/TCPMT.2025.3561801","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3561801","url":null,"abstract":"This study experimentally and computationally investigates the convection heat transfer performance of metal foams (MFs) having the same pores per inch (PPI) but different porosities attached to a uniformly heated surface using three different thermal interface materials (TIMs). Of the three TIMs considered, flexible graphite showed the best heat transfer performance by around 10%–25% compared to the reference case, where no TIM was used, due to its high in-plane thermal conductivity. In contrast, thermal epoxy was the worst, with a decrease in heat transfer by around 10%–30%, relative to the reference case. A comparable performance to the reference case was exhibited by the thermal gap pad. The MF hydraulic modeling parameters were extracted from the pressure drop data, and pore and filament diameters were obtained from micro-CT (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>CT) scans and used in the numerical simulations. Thermal contact resistances (TCRs) are assessed from the numerical simulations. The results showed that total TCR tends to increase with increasing filament diameter and decreasing porosity. Moreover, the steady-state thermal analyses showed that the flexible graphite effectively spreads the heat in the TIM and reduces the overall TCR. Detailed temperature contours on the heated surface of the thermal gap pad and flexible graphite TIMs used with different porosity MFs are presented to support these findings.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1179-1188"},"PeriodicalIF":2.3,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To enhance the electrical performance and reliability of silicon carbide (SiC) power modules, the study explores Cu-clip as a promising alternative to traditional Al-wire interconnections. SiC power modules, particularly in parallel configurations, encounter challenges in optimizing dynamic current-sharing performance, which limits their maximum current capacity and reliability during switching events. This study proposes an innovative layout design for SiC MOSFET modules, utilizing a coupled parasitic inductance network model to capture better the impact of mutual inductances on dynamic current imbalance. The model derives an equation for equivalent source inductances, accounting for both self-inductance and mutual inductance, providing a foundation for optimizing the layout to minimize dynamic current imbalance. Based on this model, a new Cu-clip structure is designed along with a mathematical analysis aimed at reducing disparities in equivalent source inductances, thereby enhancing dynamic current balancing. The distance between the dies is also increased to mitigate thermal coupling effects. Double-pulse tests and simulations were performed to validate the dynamic current balancing performance of the fabricated power module. The results show a 40% reduction in dynamic current imbalance for the optimized layout (layout B) compared to the baseline configuration (layout A). This work presents a comprehensive solution to improve the dynamic current performance of paralleled SiC MOSFET power modules, offering significant contributions to the design of more efficient and reliable power electronics.
{"title":"Analytical and Optimal Strategy of Dynamic Current Balancing for Paralleled SiC MOSFETs With Cu-Clip Interconnection Considering Mutual Coupled Inductances","authors":"Xun Liu;Kun Ma;Yameng Sun;Yifan Song;Xiao Zhang;Anning Chen;Xuehan Li;Wei Huang;Huimin Shi;Miao Li;Yang Zhou;Sheng Liu","doi":"10.1109/TCPMT.2025.3561273","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3561273","url":null,"abstract":"To enhance the electrical performance and reliability of silicon carbide (SiC) power modules, the study explores Cu-clip as a promising alternative to traditional Al-wire interconnections. SiC power modules, particularly in parallel configurations, encounter challenges in optimizing dynamic current-sharing performance, which limits their maximum current capacity and reliability during switching events. This study proposes an innovative layout design for SiC MOSFET modules, utilizing a coupled parasitic inductance network model to capture better the impact of mutual inductances on dynamic current imbalance. The model derives an equation for equivalent source inductances, accounting for both self-inductance and mutual inductance, providing a foundation for optimizing the layout to minimize dynamic current imbalance. Based on this model, a new Cu-clip structure is designed along with a mathematical analysis aimed at reducing disparities in equivalent source inductances, thereby enhancing dynamic current balancing. The distance between the dies is also increased to mitigate thermal coupling effects. Double-pulse tests and simulations were performed to validate the dynamic current balancing performance of the fabricated power module. The results show a 40% reduction in dynamic current imbalance for the optimized layout (layout B) compared to the baseline configuration (layout A). This work presents a comprehensive solution to improve the dynamic current performance of paralleled SiC MOSFET power modules, offering significant contributions to the design of more efficient and reliable power electronics.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1189-1202"},"PeriodicalIF":2.3,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-15DOI: 10.1109/TCPMT.2025.3560722
Kamil Gradkowski
This study investigates alignment and coupling between a photonic integrated circuit (PIC) and a mixed-mode fiber array (FA), where one of the channels in the normally single-mode (SM) array is replaced by a multimode fiber (MMF). As a result, the tolerances of alignment are significantly relaxed. The proposed method suggests using the single-mode fiber (SMF) at the input and the MMF at the output of the PIC. In such a transmission configuration, the tolerances are relaxed by a factor of $surd 2$ (41%). As this scales with mode size, the beam-expansion mechanisms, for example, utilizing microlenses, can further significantly reduce the requirements for fabrication and packaging of photonic devices, making them more robust and cheaper to manufacture.
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