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A 3-D Heterogeneously Integrated Application of the RF-Module With Micro-Bump Filter and Embedded AiP at W-Band 带有微型凸块滤波器和嵌入式 AiP 的射频模块在 W 波段的三维异构集成应用
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-15 DOI: 10.1109/TCPMT.2024.3428930
Xiao Yang;Xiao-Long Huang;Liang Zhou;Zi-Qi Zhang;Jun-Zhe Zhao;Jun-Fa Mao
In this study, we present the design, fabrication, and measurements of a 3-D heterogeneous integrated RF-module at W-band. A 3-D transition structure based on micro-bumps is fabricated and measured to obtain the transition loss of one bump. One micro-bump has an insertion loss of 0.21 dB at the W-band. A packaged filter and a benzocyclobutene (BCB)-based back cavity antenna are designed and analyzed in detail. The filter has a 2.6-dB insertion loss at 94 GHz with four transmission zeros (TZs) and a $2.14f_{0}~10$ -dB stopband. An extra loss of 0.9 dB is found after packaging. Then, the filter and antenna are integrated with a SiGe-based low-noise amplifier (LNA) and a mixer to realize a fully packaged receiver by using our in-house Si-based micro-electromechanical systems (MEMS) through-silicon-trench (TST) technology and multilayer photosensitive composite film. The proposed 3-D heterogeneous integrated receiver is measured on-wafer. This low-loss packaging solution can be further used in millimeter-wave communication or radar systems.
在本研究中,我们介绍了 W 波段三维异质集成射频模块的设计、制造和测量。我们制作并测量了基于微凸块的三维过渡结构,从而获得了一个凸块的过渡损耗。一个微凸块在 W 波段的插入损耗为 0.21 dB。设计并详细分析了一个封装滤波器和一个基于苯并环丁烯(BCB)的背腔天线。滤波器在 94 GHz 时的插入损耗为 2.6 分贝,具有四个传输零点(TZ)和一个 2.14f_{0}~10$ 分贝的阻带。封装后的额外损耗为 0.9 dB。然后,利用我们自主研发的硅基微机电系统(MEMS)通硅沟(TST)技术和多层光敏复合膜,将滤波器和天线与硅基低噪声放大器(LNA)和混频器集成在一起,实现了完全封装的接收器。所提出的三维异质集成接收器是在晶片上测量的。这种低损耗封装解决方案可进一步用于毫米波通信或雷达系统。
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引用次数: 0
Compact IPD Bandpass Filters Based on Coupling-Enhanced Transformer and Metamaterial Lowpass Structure 基于耦合增强变压器和超材料低通结构的紧凑型 IPD 带通滤波器
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-08 DOI: 10.1109/TCPMT.2024.3424783
Bukun Xu;Yazi Cao;Bo Yuan;Shichang Chen;Gaofeng Wang
Two compact bandpass filters (BPFs) based on the coupling-enhanced transformer and metamaterial lowpass structure are presented. The coupling-enhanced transformer is introduced to reduce the insertion loss in the desired passband. Moreover, for the first time, a new metamaterial lowpass structure is proposed to generate multiple transmission zeros (TZs) and can achieve high stopband suppression in a wide upper stopband. Its even-odd mode equivalent circuits are discussed, and its Bloch impedance and dispersion are analyzed. The first BPF operates at 1.85 GHz and the second BPF operates at 2.45 GHz, which can achieve an insertion loss of less than 1.0 and 0.8 dB, respectively. These two BPFs can achieve 30 dB attenuation from 4.7 to 7.5 GHz and 20 dB attenuation up to $7.2~f_{0}$ , respectively. Both designs have a compact size of less than $1.3times 10^{-2}~lambda _{0} times 6.5times 10^{-3}~lambda _{0}$ . Two prototypes are fabricated using Si-based integrated passive devices (IPDs) technology and validated with measurements.
本文介绍了两个基于耦合增强变压器和超材料低通结构的紧凑型带通滤波器(BPF)。耦合增强变压器的引入可降低所需通带内的插入损耗。此外,还首次提出了一种新的超材料低通结构,可产生多个传输零点(TZ),并能在宽上止带实现高止带抑制。我们讨论了它的偶偶模等效电路,并分析了它的布洛赫阻抗和色散。第一个 BPF 工作频率为 1.85 GHz,第二个 BPF 工作频率为 2.45 GHz,插入损耗分别小于 1.0 和 0.8 dB。这两个 BPF 在 4.7 至 7.5 GHz 频段可分别实现 30 dB 衰减,在 7.2~f_{0}$ 频段可分别实现 20 dB 衰减。这两种设计的体积均小于 1.3 (times 10^{-2}~lambda _{0} 美元)。6.5 倍 10^{-3}~lambda _{0}$ 。利用硅基集成无源器件(IPDs)技术制造了两个原型,并通过测量进行了验证。
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引用次数: 0
Drop Shock Testing Analysis at Elevated Temperature: Assessing SAC305 Solder Alloy Reliability in BGA Assemblies 高温跌落冲击测试分析:评估 BGA 组件中 SAC305 焊接合金的可靠性
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-05 DOI: 10.1109/TCPMT.2024.3424343
Palash Pranav Vyas;Ali Alahmer;Sergio Bolanos;Seyed Soroosh Alavi;Sa’d Hamasha
The electronics industry is increasingly prioritizing the reliability of SnAgCu (SAC)-based alloys due to environmental concerns related to lead-based alloys. Considering the frequent occurrence of drops during the typical use of portable electronic devices, guaranteeing robust board-level drop shock reliability becomes vital for ensuring their optimal performance and longevity. Traditionally, drop shock tests have predominantly been conducted at room temperature, which does not fully simulate real-world conditions where electronic circuits are subjected to operational or environmental thermal strains during the normal operation. To address this knowledge gap, this study aims to conduct drop shock tests at elevated temperatures, ensuring the reliability of solder joints in practical applications. In this study, ball grid array (BGA) assemblies containing SAC305 solder alloy were tested at various temperatures. The drop shock experiments were performed according to the Joint Electron Device Engineering Council (JEDEC) drop test standard JESD22- B111A, with a peak acceleration of 1500 G and a pulse duration of 0.5 ms. Subsequently, the drop shock reliability of the solder joints under each test condition was assessed using the Weibull analysis. In addition, the Arrhenius model was applied to develop a drop life prediction model. Furthermore, comprehensive microscopy analysis was performed to identify the failure modes and trends with increasing temperature. The results indicated that SAC305 exhibits best performance at room temperature (25 ° C). However, its drop shock lifespan significantly decreases as the temperature rises, with reductions of 64%, 76%, and 78% at 50 ° C, 75 ° C, and 100 ° C, respectively. Moreover, a failure mode transition was observed with an increase in temperature.
由于铅基合金对环境的影响,电子行业越来越重视锡银铜(SAC)合金的可靠性。考虑到便携式电子设备在通常使用过程中会频繁发生跌落,因此保证稳健的板级跌落冲击可靠性对于确保其最佳性能和使用寿命至关重要。传统的跌落冲击测试主要是在室温下进行的,无法完全模拟电子电路在正常工作时受到操作或环境热应变的实际条件。针对这一知识空白,本研究旨在进行高温下的跌落冲击测试,以确保焊点在实际应用中的可靠性。在这项研究中,含有 SAC305 焊接合金的球栅阵列 (BGA) 组件在不同温度下进行了测试。跌落冲击实验按照电子器件工程联合委员会(JEDEC)跌落测试标准 JESD22- B111A 进行,峰值加速度为 1500 G,脉冲持续时间为 0.5 ms。随后,使用 Weibull 分析法评估了每种测试条件下焊点的跌落冲击可靠性。此外,还应用 Arrhenius 模型建立了跌落寿命预测模型。此外,还进行了全面的显微镜分析,以确定失效模式和随温度升高而变化的趋势。结果表明,SAC305 在室温(25 ° C)下表现出最佳性能。然而,随着温度的升高,其跌落冲击寿命明显缩短,在 50 ° C、75 ° C 和 100 ° C 时分别缩短了 64%、76% 和 78%。此外,随着温度的升高,还观察到了失效模式的转变。
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引用次数: 0
Flexible/Conformal Inkjet-Printed 3-D “Ramp” Interconnects for 5G/mmWave System-on-Package Designs and Wearable Applications 用于 5G/mmWave 系统级封装设计和可穿戴应用的柔性/共形喷墨打印三维 "斜坡 "互连器件
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-05 DOI: 10.1109/TCPMT.2024.3424277
Kexin Hu;Yi Zhou;Suresh K. Sitaraman;Manos M. Tentzeris
This article presents the first and most comprehensive design, fabrication, and reliability evaluation of the electrical and mechanical performance of fully inkjet-printed 3-D “ramp” interconnects. Inkjet-printed interconnects feature superior RF performance and better mechanical reliability for heterogeneous integration for 5G mmWave flexible electronics packaging. The packaged systems are required to survive various flexing conditions over a large number of cyclic bending for conformal applications. In this work, ramp interconnects are designed with excellent and reliable performance for flexible packaging over the 20–40-GHz frequency band. A test vehicle of a monolithic microwave integrated circuit (MMIC) attenuator die placed in the middle of two microstrip lines is used, where ramp interconnects are fabricated by inkjet printing SU8 dielectric ink to form ramp base and inkjet printing silver nanoparticle (SNP) ink for conductive interconnects to build the connection between the die and microstrip lines. The fabricated sample exhibits a superior $S_{21}$ performance with less than 1.16-dB insertion loss per interconnect throughout the whole operation range from 20 to 40 GHz. Monotonic bending tests are conducted over mandrels of various radii ranging from 50 to 10 mm, and the designed ramp interconnects are able to maintain robust transmission with a minimum variation of less than 0.15-dB insertion loss per interconnect. Moreover, the fabricated samples are able to survive over 20 000 times of cyclic bending tests over the mandrel of 10-mm radius, with less than 0.2-dB additional loss from each interconnect. The proposed design takes advantage of a low-cost, on-demand additive manufacturing method by selectively depositing SU8 ink layer by layer with varying dimensions to enable rugged ramp structures for curved mounting platforms. The results reported in this article could enable rapid production of high-performance and reliable flexible system-on-package (SoP) and multichip module (MCM) designs and build the foundation of next-generation 5G mmWave flexible hybrid electronics (FHE) technologies for various applications.
本文首次对完全喷墨打印的三维 "斜坡 "互连器件的电气和机械性能进行了最全面的设计、制造和可靠性评估。喷墨打印互连具有卓越的射频性能和更好的机械可靠性,可用于 5G 毫米波柔性电子封装的异构集成。在保形应用中,封装系统需要在大量的循环弯曲过程中经受住各种弯曲条件。在这项工作中,为 20-40-GHz 频段的柔性封装设计了性能卓越、可靠的斜坡互连器件。使用的测试载体是放置在两条微带线中间的单片微波集成电路(MMIC)衰减器芯片,通过喷墨打印 SU8 介电油墨形成斜坡基底,喷墨打印银纳米粒子(SNP)油墨形成导电互连,从而在芯片和微带线之间建立连接。制造出的样品具有卓越的 $S_{21}$ 性能,在 20 至 40 GHz 的整个工作范围内,每个互连器件的插入损耗小于 1.16 分贝。在 50 至 10 毫米不同半径的心轴上进行了单调弯曲测试,所设计的斜坡互连能够保持稳健的传输,每个互连的插入损耗最小变化小于 0.15 分贝。此外,制作的样品能够在半径为 10 毫米的心轴上经受超过 20 000 次的循环弯曲测试,每个互连器件的额外损耗小于 0.2 分贝。所提出的设计利用了一种低成本、按需增材制造方法,通过选择性地逐层沉积不同尺寸的 SU8 油墨,实现了用于弯曲安装平台的坚固斜坡结构。本文所报告的成果可实现高性能、可靠的柔性系统级封装(SoP)和多芯片模块(MCM)设计的快速生产,并为各种应用领域的下一代 5G 毫米波柔性混合电子(FHE)技术奠定基础。
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引用次数: 0
Rapid Design of Litz Wire Using Surrogate Assisted Optimization Embedding Adjacent Trust Region 利用嵌入相邻信任区域的代用辅助优化技术快速设计利兹导线
IF 2.2 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-04 DOI: 10.1109/tcpmt.2024.3423003
Jiahua Lyu, Hong Cai Chen, Qingsha S. Cheng, Yang Zhang, Yaping Du
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information 电气和电子工程师学会《元件、封装和制造技术》学会信息
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-01 DOI: 10.1109/TCPMT.2024.3428277
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引用次数: 0
Blank Page 空白页
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-01 DOI: 10.1109/TCPMT.2024.3439190
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引用次数: 0
Modeling-Based Improvement of Microscale Liquid Jet Impingement Cooling 基于建模的微尺度液体喷射撞击冷却技术改进
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-01 DOI: 10.1109/TCPMT.2024.3421585
Georg Elsinger;Herman Oprins;Vladimir Cherman;Geert Van der Plas;Eric Beyne;Ingrid De Wolf
As high-power electronics cooling for high heat fluxes above 100 W/cm $^{mathbf {2}}$ continues to become a more and more pressing matter, work to provide an efficient and effective cooling solution in turn also continues. In the ecosystem of active liquid cooling solutions, it is the cooling performance that is provided within a given flow rate and pressure drop budget that determines efficiency. Liquid jet impingement on the bare die has been proven to provide good cooling performance that is not impeded by the thermal resistance of thermal interface materials. However, system optimizations are also necessary to provide the desired cooling performance within the restrictions of flow rate and pressure drop. A modeling study and experimental demonstrations were done in this work to showcase improvement options within restricted operating conditions. The modeling study shows that the adjustment of inlet- and outlet-nozzle diameter, nozzle-to-target spacing, and nozzle pitch allows for optimizing the achieved heat transfer coefficient at given operating conditions. Based on this modeling study, a reference cooler and different improved demonstrators were built, and within the same budget for coolant flow rate and driving pressure drop, an improvement of effective heat transfer coefficient by 122% from 4.9 to 10.4 W/cm $^{mathbf {2}}cdot $ K was achieved.
随着大功率电子设备在 100 W/cm 以上的高热流量下的冷却问题日益紧迫,提供高效的冷却解决方案的工作也在不断进行。在主动液体冷却解决方案的生态系统中,决定效率的是在给定流速和压降预算范围内提供的冷却性能。事实证明,液体喷射撞击裸芯片可提供良好的冷却性能,而且不会受到热界面材料热阻的影响。然而,为了在流速和压降的限制范围内提供理想的冷却性能,系统优化也是必要的。本研究通过建模研究和实验演示,展示了在受限运行条件下的改进方案。建模研究表明,通过调整入口和出口喷嘴直径、喷嘴与目标之间的间距以及喷嘴间距,可以优化给定工作条件下实现的传热系数。基于这项建模研究,我们建造了一个参考冷却器和不同的改进型演示器,在冷却剂流速和驱动压降预算相同的情况下,有效传热系数提高了 122%,从 4.9 W/cm $^{mathbf {2}cdot $ K 提高到 10.4 W/cm。
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors IEEE 《部件、封装和制造技术》期刊 为作者提供的信息
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-01 DOI: 10.1109/TCPMT.2024.3428275
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information 电气和电子工程师学会《部件、封装和制造技术》期刊 出版信息
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-01 DOI: 10.1109/TCPMT.2024.3428271
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IEEE Transactions on Components, Packaging and Manufacturing Technology
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