Understanding and mitigation of substrate RF losses and signal distortion are critical to enable high-performance GaN-on-Si front-end-modules. While the origin of RF losses and consequently a decreased effective substrate resistivity $({rho }_{eff})$ in GaN-on-Si substrates is now understood to be diffusion of Al and Ga atoms into the silicon substrate during III-N growth, the effect of upper III-N buffer layers on the ${rho }_{eff}$ degradation under stressed conditions remains unclear. In this paper, we show that up to 50% variation in ${rho }_{eff}$ at 2 GHz can take place over more than 1,000 s when the substrate is stressed at 50 V. Additionally, Coplanar Wave Guide (CPW) large-signal measurements under the same experimental conditions show a variation of $2^{mathrm{ nd}}$ harmonic power of up to 5dB. A thermally activated stress and relaxation behavior shows the signature of traps which are present in the C-doped layers. With the help of a simplified TCAD model of the GaN-on-Si stack, we link this behavior to slow charge redistribution in the C-doped buffer continuously modifying the flat-band voltage ( $text{V}_{text {FB}}$ ) of the Metal-Insulator-Semiconductor (MIS) structure. Free carrier transport across the buffer is shown to have the greatest contribution on the large time constants, highlighting the importance of vertical transport paths in GaN-on-Si stacks.
要实现高性能硅基氮化镓前端模块，了解并减少基底射频损耗和信号失真至关重要。虽然硅基氮化镓衬底的射频损耗以及由此导致的有效衬底电阻率$({rho }_{eff})$下降的原因现在已被理解为在III-N生长过程中铝和镓原子向硅衬底的扩散，但上层III-N缓冲层对受压条件下${rho }_{eff}$退化的影响仍不清楚。本文表明，当衬底在 50 V 下受压时，2 GHz 频率下的 ${rho }_{eff}$ 在 1,000 秒内会发生高达 50%的变化。此外，在相同实验条件下进行的共面波导 (CPW) 大信号测量显示，2^{mathrm{nd}}$谐波功率的变化高达 5dB。热激活应力和弛豫行为显示了掺杂 C 的层中存在陷阱的特征。借助简化的硅基氮化镓（GaN-on-Si）堆栈 TCAD 模型，我们将这种行为与掺杂 C 的缓冲器中缓慢的电荷再分布联系起来，这种再分布会持续改变金属-绝缘体-半导体（MIS）结构的平带电压（${V}_{text {FB}}$）。跨缓冲器的自由载流子传输对大时间常数的贡献最大，这突出了硅基氮化镓叠层中垂直传输路径的重要性。
{"title":"Effect of Buffer Charge Redistribution on RF Losses and Harmonic Distortion in GaN-on-Si Substrates","authors":"Pieter Cardinael;Sachin Yadav;Bertrand Parvais;Jean-Pierre Raskin","doi":"10.1109/JEDS.2024.3386170","DOIUrl":"10.1109/JEDS.2024.3386170","url":null,"abstract":"Understanding and mitigation of substrate RF losses and signal distortion are critical to enable high-performance GaN-on-Si front-end-modules. While the origin of RF losses and consequently a decreased effective substrate resistivity \u0000<inline-formula> <tex-math>$({rho }_{eff})$ </tex-math></inline-formula>\u0000 in GaN-on-Si substrates is now understood to be diffusion of Al and Ga atoms into the silicon substrate during III-N growth, the effect of upper III-N buffer layers on the \u0000<inline-formula> <tex-math>${rho }_{eff}$ </tex-math></inline-formula>\u0000 degradation under stressed conditions remains unclear. In this paper, we show that up to 50% variation in \u0000<inline-formula> <tex-math>${rho }_{eff}$ </tex-math></inline-formula>\u0000 at 2 GHz can take place over more than 1,000 s when the substrate is stressed at 50 V. Additionally, Coplanar Wave Guide (CPW) large-signal measurements under the same experimental conditions show a variation of \u0000<inline-formula> <tex-math>$2^{mathrm{ nd}}$ </tex-math></inline-formula>\u0000 harmonic power of up to 5dB. A thermally activated stress and relaxation behavior shows the signature of traps which are present in the C-doped layers. With the help of a simplified TCAD model of the GaN-on-Si stack, we link this behavior to slow charge redistribution in the C-doped buffer continuously modifying the flat-band voltage (\u0000<inline-formula> <tex-math>$text{V}_{text {FB}}$ </tex-math></inline-formula>\u0000) of the Metal-Insulator-Semiconductor (MIS) structure. Free carrier transport across the buffer is shown to have the greatest contribution on the large time constants, highlighting the importance of vertical transport paths in GaN-on-Si stacks.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10495002","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140582740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-08DOI: 10.1109/JEDS.2024.3386113
Maximilian Reuter;Johannes Wilm;Andreas Kramer;Niladri Bhattacharjee;Christoph Beyer;Jens Trommer;Thomas Mikolajick;Klaus Hofmann
In integrated circuit design compact models are the abstraction layer which connects semiconductor physics and circuit simulation. Established compact models like BSIM provide a powerful platform for many kinds of conventional MOSFETs. However, novel device concepts like reconfigurable FETs (RFETs) come with a higher expressiveness. Due to their altered transport physics as compared to classical inversion mode MOSFETs those devices are hard to describe in a closed form expression by classical compact models. Table models bridge this gap for devices with novel features or materials, but circuit simulation becomes slow and inaccurate due to interpolation and convergence difficulties. Table model data can, however, be translated to closed form expressions, providing equation based models without the need for interpolation during simulation time. This work shows data driven approaches to generate compact models from biasing tables without physical analysis of the device behavior. Two automated modeling techniques are applied to a recently emerged RFET, forming a Verilog-A compact model for DC and transient simulation in Cadence Virtuoso. Drive current is implemented as a neural network, large enough to accurately predict behavior of a multi-gate device. The high dynamic range from $mA$ to $pA$ is covered by combining a linear model for high currents and a logarithmic model for low currents. For transient simulation precise models for electrode charges are essential. Here, symbolic regression provides human-readable closed form expressions which allow direct implementation in Verilog-A. The compact model approach is demonstrated with device data generated from a structural technology model (TCAD). However, the entire modeling flow can directly be used on real device measurements, if a technology model is unavailable or unpractical. We show that the presented machine learning based compact models show better convergence, more accurate predictions and faster simulation $(82$ to 308 times) in Cadence SPECTRE than simple table models generated from the same device.
{"title":"Machine Learning-Based Compact Model Design for Reconfigurable FETs","authors":"Maximilian Reuter;Johannes Wilm;Andreas Kramer;Niladri Bhattacharjee;Christoph Beyer;Jens Trommer;Thomas Mikolajick;Klaus Hofmann","doi":"10.1109/JEDS.2024.3386113","DOIUrl":"10.1109/JEDS.2024.3386113","url":null,"abstract":"In integrated circuit design compact models are the abstraction layer which connects semiconductor physics and circuit simulation. Established compact models like BSIM provide a powerful platform for many kinds of conventional MOSFETs. However, novel device concepts like reconfigurable FETs (RFETs) come with a higher expressiveness. Due to their altered transport physics as compared to classical inversion mode MOSFETs those devices are hard to describe in a closed form expression by classical compact models. Table models bridge this gap for devices with novel features or materials, but circuit simulation becomes slow and inaccurate due to interpolation and convergence difficulties. Table model data can, however, be translated to closed form expressions, providing equation based models without the need for interpolation during simulation time. This work shows data driven approaches to generate compact models from biasing tables without physical analysis of the device behavior. Two automated modeling techniques are applied to a recently emerged RFET, forming a Verilog-A compact model for DC and transient simulation in Cadence Virtuoso. Drive current is implemented as a neural network, large enough to accurately predict behavior of a multi-gate device. The high dynamic range from \u0000<inline-formula> <tex-math>$mA$ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$pA$ </tex-math></inline-formula>\u0000 is covered by combining a linear model for high currents and a logarithmic model for low currents. For transient simulation precise models for electrode charges are essential. Here, symbolic regression provides human-readable closed form expressions which allow direct implementation in Verilog-A. The compact model approach is demonstrated with device data generated from a structural technology model (TCAD). However, the entire modeling flow can directly be used on real device measurements, if a technology model is unavailable or unpractical. We show that the presented machine learning based compact models show better convergence, more accurate predictions and faster simulation \u0000<inline-formula> <tex-math>$(82$ </tex-math></inline-formula>\u0000 to 308 times) in Cadence SPECTRE than simple table models generated from the same device.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10494540","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140582931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.
{"title":"Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs","authors":"Anirban Kar;Shivendra Singh Parihar;Jun Z. Huang;Huilong Zhang;Weike Wang;Kimihiko Imura;Yogesh Singh Chauhan","doi":"10.1109/JEDS.2024.3384008","DOIUrl":"10.1109/JEDS.2024.3384008","url":null,"abstract":"Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10488034","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140582831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-29DOI: 10.1109/JEDS.2024.3406676
Muhammad Aslam;Shu-Wei Chang;Yi-Ho Chen;Yao-Jen Lee;Yiming Li;Wen-Hsi Lee
ABSTRACT Amorphous indium gallium zinc oxide (a-IGZO)-based thin film transistors (TFTs) are increasingly becoming popular because of their potential in futuristic applications, including CMOS technology. Given the demand for CMOS-compatible, ultra-scaled, reliable, and high-performing devices, we fabricate and analyze scaled-channel a-IGZO-TFTs with an optimal double-gate structure, a thin nanosheet-based channel, and an effective high- $kappa$ dielectric namely HfO2. The reliably reported double gate IGZO nanosheet TFTs (DG-IGZO-NS-TFTs) are tested under positive and negative bias stress at variant temperatures, and the resulting modulations are analyzed critically. The reported DG-IGZO-NSTFTs exhibit a negative side threshold voltage shift ( $Delta$ Vth) accompanied by an increase in Ion/Ion(0) under negative bias temperature stress (NBTS) at elevated temperatures, which indicates the presence of additional charges. An anomalous negative side shifting of the Vth is observed under positive bias temperature stress (PBTS), where diffused hydrogen atoms are identified as introducing excess n-type carriers into the channel and causing the observed $Delta$ Vth. The spectroscopic analysis is performed to establish evidence for the assumed mechanisms, and the role of individual gates is investigated in the context of performance variance under temperature-bias stress. Moreover, the partial reversibility of the stress-induced degradation is experimentally established and methodically discussed. Overall, the reported results offer a comprehensive understanding of scaled-channel DG-NS-IGZO-TFTs, which help shape performance-enhancement strategies, control degradation mechanisms, and define appropriate application scenarios.
{"title":"Mechanism of Threshold Voltage Instability in Double Gate α-IGZO Nanosheet TFT Under Bias and Temperature Stress","authors":"Muhammad Aslam;Shu-Wei Chang;Yi-Ho Chen;Yao-Jen Lee;Yiming Li;Wen-Hsi Lee","doi":"10.1109/JEDS.2024.3406676","DOIUrl":"10.1109/JEDS.2024.3406676","url":null,"abstract":"ABSTRACT Amorphous indium gallium zinc oxide (a-IGZO)-based thin film transistors (TFTs) are increasingly becoming popular because of their potential in futuristic applications, including CMOS technology. Given the demand for CMOS-compatible, ultra-scaled, reliable, and high-performing devices, we fabricate and analyze scaled-channel a-IGZO-TFTs with an optimal double-gate structure, a thin nanosheet-based channel, and an effective high- \u0000<inline-formula> <tex-math>$kappa$ </tex-math></inline-formula>\u0000 dielectric namely HfO2. The reliably reported double gate IGZO nanosheet TFTs (DG-IGZO-NS-TFTs) are tested under positive and negative bias stress at variant temperatures, and the resulting modulations are analyzed critically. The reported DG-IGZO-NSTFTs exhibit a negative side threshold voltage shift (\u0000<inline-formula> <tex-math>$Delta$ </tex-math></inline-formula>\u0000Vth) accompanied by an increase in Ion/Ion(0) under negative bias temperature stress (NBTS) at elevated temperatures, which indicates the presence of additional charges. An anomalous negative side shifting of the Vth is observed under positive bias temperature stress (PBTS), where diffused hydrogen atoms are identified as introducing excess n-type carriers into the channel and causing the observed \u0000<inline-formula> <tex-math>$Delta$ </tex-math></inline-formula>\u0000Vth. The spectroscopic analysis is performed to establish evidence for the assumed mechanisms, and the role of individual gates is investigated in the context of performance variance under temperature-bias stress. Moreover, the partial reversibility of the stress-induced degradation is experimentally established and methodically discussed. Overall, the reported results offer a comprehensive understanding of scaled-channel DG-NS-IGZO-TFTs, which help shape performance-enhancement strategies, control degradation mechanisms, and define appropriate application scenarios.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10540482","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141188932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-28DOI: 10.1109/JEDS.2024.3382874
Haomin Chen;Qunying Zeng;Yangbin Zhu;Tuo Wu;Yijie Fan;Tailiang Guo;Hailong Hu;Fushan Li
Zinc oxidenanoparticles (ZnO NPs) is widely used as electron transport layer material in quantum dot light-emitting diodes (QLED) due to its high carrier mobility, unique photoelectric properties and good stability. However, because ZnO has higher electron mobility than organic hole transport materials, the carrier transport is unbalanced. In addition, ZnO NPs has many surface defects, which is easy to capture electrons or holes, increasing the probability of non-radiative recombination. To solve these problems, we carefully selected an organic compound diallylamine (DAA) doping method to modify the surface of ZnO. DAA is found to not only reduce the quenching at the interface between ZnO and QD, but also regulate the energy level position to promote the carrier injection balance of QLED devices. Compared with control ZnO QLED, the external quantum efficiency (EQE) of the red QLED with DAA-modified ZnO NPs is significantly improved, the peakEQE of the devices increased by 21% from 18.8% to 23.6%. respectively. It is a simple and economical solution for manufacturing high-performance QLED.
{"title":"Efficient Quantum Dot Light-Emitting Diodes With DAA Doped Electron Transport Layer","authors":"Haomin Chen;Qunying Zeng;Yangbin Zhu;Tuo Wu;Yijie Fan;Tailiang Guo;Hailong Hu;Fushan Li","doi":"10.1109/JEDS.2024.3382874","DOIUrl":"10.1109/JEDS.2024.3382874","url":null,"abstract":"Zinc oxidenanoparticles (ZnO NPs) is widely used as electron transport layer material in quantum dot light-emitting diodes (QLED) due to its high carrier mobility, unique photoelectric properties and good stability. However, because ZnO has higher electron mobility than organic hole transport materials, the carrier transport is unbalanced. In addition, ZnO NPs has many surface defects, which is easy to capture electrons or holes, increasing the probability of non-radiative recombination. To solve these problems, we carefully selected an organic compound diallylamine (DAA) doping method to modify the surface of ZnO. DAA is found to not only reduce the quenching at the interface between ZnO and QD, but also regulate the energy level position to promote the carrier injection balance of QLED devices. Compared with control ZnO QLED, the external quantum efficiency (EQE) of the red QLED with DAA-modified ZnO NPs is significantly improved, the peakEQE of the devices increased by 21% from 18.8% to 23.6%. respectively. It is a simple and economical solution for manufacturing high-performance QLED.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10485228","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140324058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-22DOI: 10.1109/JEDS.2024.3381030
Howie Tseng;Yueh-Chin Lin;Chieh Cheng;Po-Wei Chen;Heng-Tung Hsu;Yi-Fan Tsao;Edward Yi Chang
In this study, AlGaN/GaN high-electron-mobility-transistor (HEMT) with thick Cu metallization is investigated, and the Radio Frequency (RF) performance and the reliability are analyzed. By applying thick Cu metallization of $6.0 ~mu text{m}$ as interconnect, the cut-off frequency (fT), the maximum oscillation frequency (fmax), and the power performance can be improved. Besides, the thick-Cu-metallized device exhibits reduced minimum noise figure (NFmin) of 0.7, 1.0, 2.2 and 2.8 dB at 12, 14, 28 and 38 GHz, respectively, which can be attributed to the reduction of the source and drain resistance caused by thick Cu metallization. Furthermore, for stress test under high drain-to-source voltage (VDS) and high temperature, the proposed device exhibits good stability. The results show that the thick Cu metallization technology has great potential to be applied in satellite communication system.
{"title":"Improvement of AlGaN/GaN HEMT Noise Figure Using Thick Cu Metallization for Satellite Communication Applications","authors":"Howie Tseng;Yueh-Chin Lin;Chieh Cheng;Po-Wei Chen;Heng-Tung Hsu;Yi-Fan Tsao;Edward Yi Chang","doi":"10.1109/JEDS.2024.3381030","DOIUrl":"10.1109/JEDS.2024.3381030","url":null,"abstract":"In this study, AlGaN/GaN high-electron-mobility-transistor (HEMT) with thick Cu metallization is investigated, and the Radio Frequency (RF) performance and the reliability are analyzed. By applying thick Cu metallization of \u0000<inline-formula> <tex-math>$6.0 ~mu text{m}$ </tex-math></inline-formula>\u0000 as interconnect, the cut-off frequency (fT), the maximum oscillation frequency (fmax), and the power performance can be improved. Besides, the thick-Cu-metallized device exhibits reduced minimum noise figure (NFmin) of 0.7, 1.0, 2.2 and 2.8 dB at 12, 14, 28 and 38 GHz, respectively, which can be attributed to the reduction of the source and drain resistance caused by thick Cu metallization. Furthermore, for stress test under high drain-to-source voltage (VDS) and high temperature, the proposed device exhibits good stability. The results show that the thick Cu metallization technology has great potential to be applied in satellite communication system.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10478115","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140197315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-21DOI: 10.1109/JEDS.2024.3403649
Yuta Watanabe;Takaya Sugiura;Nobuhiko Nakano
Energy harvesters, such as photovoltaic cells, generate carriers in the deep substrate regions; these carriers can affect MOSFETs and deteriorate their performance or even cause malfunctioning. In this study, we discussed the effects of bulk carrier contamination on integrated MOSFETs in the context of energy-harvesting devices. We confirmed that the close integration of MOSFET circuits in a photovoltaic cell causes malfunctioning under strong light illumination. Moreover, numerical simulations revealed that PMOS is highly sensitive to carrier contamination as a forward pn-junction from the bulk-side storage carriers into the NWell region. Furthermore, increasing the distance from the illumination window was not an effective countermeasure, and alternative methods, such as the silicon-on-insulator substrate, n−-substrate, or NMOS logic, should be implemented for such large-scale integration.
{"title":"Bulk Carrier Contaminations and Their Effects on MOSFETs Under Energy Harvesting Systems","authors":"Yuta Watanabe;Takaya Sugiura;Nobuhiko Nakano","doi":"10.1109/JEDS.2024.3403649","DOIUrl":"10.1109/JEDS.2024.3403649","url":null,"abstract":"Energy harvesters, such as photovoltaic cells, generate carriers in the deep substrate regions; these carriers can affect MOSFETs and deteriorate their performance or even cause malfunctioning. In this study, we discussed the effects of bulk carrier contamination on integrated MOSFETs in the context of energy-harvesting devices. We confirmed that the close integration of MOSFET circuits in a photovoltaic cell causes malfunctioning under strong light illumination. Moreover, numerical simulations revealed that PMOS is highly sensitive to carrier contamination as a forward pn-junction from the bulk-side storage carriers into the NWell region. Furthermore, increasing the distance from the illumination window was not an effective countermeasure, and alternative methods, such as the silicon-on-insulator substrate, n−-substrate, or NMOS logic, should be implemented for such large-scale integration.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10536006","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141150325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a machine-learning-based approach for the degradation modeling of hot carrier injection in metal-oxide-semiconductor field-effect transistors (MOSFETs). Stress measurement data have been employed at various stress conditions of both n- and p-MOSFETs with different channel geometries. Gaussian process regression algorithm is preferred to model the post-stress characteristics of the drain-source current, the threshold voltage, and the drain-source conductance. The model outcomes have been compared with the actual measurements, and the accuracy of the generated models has been demonstrated across the test data by providing the appropriate statistics metrics. Finally, case studies of degradation estimation have been considered involving the usage of machine-learning-based models on transistors with different channel geometries or subjected to distinct stress conditions. The outcomes of this analysis reveal that the established models yield high accuracy in such contexts.
本文介绍了一种基于机器学习的方法，用于对金属氧化物半导体场效应晶体管（MOSFET）中的热载流子注入进行降解建模。采用了具有不同沟道几何形状的 n 型和 p 型 MOSFET 在各种应力条件下的应力测量数据。采用高斯过程回归算法对漏极-源极电流、阈值电压和漏极-源极电导的应力后特性进行建模。模型结果与实际测量结果进行了比较，并通过提供适当的统计指标证明了所生成模型在整个测试数据中的准确性。最后，还考虑了退化估计的案例研究，包括在具有不同沟道几何结构或处于不同应力条件下的晶体管上使用基于机器学习的模型。分析结果表明，已建立的模型在这种情况下具有很高的准确性。
{"title":"Machine Learning-Based Modeling of Hot Carrier Injection in 40 nm CMOS Transistors","authors":"Xhesila Xhafa;Ali Doğuş Güngördü;Mustafa Berke Yelten","doi":"10.1109/JEDS.2024.3380572","DOIUrl":"10.1109/JEDS.2024.3380572","url":null,"abstract":"This paper presents a machine-learning-based approach for the degradation modeling of hot carrier injection in metal-oxide-semiconductor field-effect transistors (MOSFETs). Stress measurement data have been employed at various stress conditions of both n- and p-MOSFETs with different channel geometries. Gaussian process regression algorithm is preferred to model the post-stress characteristics of the drain-source current, the threshold voltage, and the drain-source conductance. The model outcomes have been compared with the actual measurements, and the accuracy of the generated models has been demonstrated across the test data by providing the appropriate statistics metrics. Finally, case studies of degradation estimation have been considered involving the usage of machine-learning-based models on transistors with different channel geometries or subjected to distinct stress conditions. The outcomes of this analysis reveal that the established models yield high accuracy in such contexts.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10477498","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140197150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-19DOI: 10.1109/JEDS.2024.3379328
Michael I. Current;Takuya Sakaguchi;Yoji Kawasaki;Viktor Samu;Anita Pongracz;Luca Sinko;Árpád Kerekes;Zsolt Durkó
This study uses photoluminescence (PL) and other carrier-recombination sensitive probes in combination with spreading resistance profiling (SRP), SIMS and IMSIL MC-calculations to monitor the ion range and damage levels in highly-channeled and random beam orientation 7.5 MeV B and 10 MeV P and As profiles and various combinations of co-implants with 50 keV Phosphorus implants in Silicon(100). The effects of annealing on the 10 MeV profiles showed the strong shifts in PL data from implant damage in the as-implanted and annealed samples. Curious “intermittencies” were seen in the PL signals from MeV implant defect centers.
本研究使用光致发光（PL）和其他载流子重配敏感探针，结合扩散电阻曲线（SRP）、SIMS 和 IMSIL MC 计算，监测硅（100）中高通道和随机束向 7.5 MeV B 和 10 MeV P 和 As 曲线中的离子范围和损伤程度，以及 50 keV 磷植入物的各种共植入物组合。退火对 10 MeV 曲线的影响表明，在植入和退火样品中，由于植入损伤，PL 数据发生了强烈偏移。在来自 MeV 植入缺陷中心的 PL 信号中出现了奇怪的 "间歇 "现象。
{"title":"Effects of Ion Channeling and Co-Implants on Ion Ranges and Damage in Si: Studies With PL, SRP, SIMS and MC Models","authors":"Michael I. Current;Takuya Sakaguchi;Yoji Kawasaki;Viktor Samu;Anita Pongracz;Luca Sinko;Árpád Kerekes;Zsolt Durkó","doi":"10.1109/JEDS.2024.3379328","DOIUrl":"10.1109/JEDS.2024.3379328","url":null,"abstract":"This study uses photoluminescence (PL) and other carrier-recombination sensitive probes in combination with spreading resistance profiling (SRP), SIMS and IMSIL MC-calculations to monitor the ion range and damage levels in highly-channeled and random beam orientation 7.5 MeV B and 10 MeV P and As profiles and various combinations of co-implants with 50 keV Phosphorus implants in Silicon(100). The effects of annealing on the 10 MeV profiles showed the strong shifts in PL data from implant damage in the as-implanted and annealed samples. Curious “intermittencies” were seen in the PL signals from MeV implant defect centers.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10475707","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140171963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The conductivity of tungsten disulfide (WS2) films using sputtering, which is a physical vapor deposition (PVD), was enhanced using a chlorine (Cl2)-plasma treatment and sulfur-vapor annealing (SVA). For WS2 films to be used in thermoelectric devices, its carrier concentration must be controlled. Therefore, we exposed WS2 films to Cl2-plasma as a doping method. In addition, SVA was performed to improve the crystallinity of the film and potentially introduce activating dopants. Consequently, the conductivity of the Cl2-plasma-treated PVD-WS2 films (0.440 S/m) more than doubled compared with that of an untreated PVD-WS2 film (0.201 S/m). The doping type in this experiment is considered to be n-type on the basis of a positive peak shift observed in the X-ray photoelectron spectra.
二硫化钨（WS2）薄膜是一种物理气相沉积（PVD）技术，采用溅射法（即物理气相沉积），通过氯（Cl2）等离子体处理和硫气退火（SVA）增强了其导电性。要将 WS2 薄膜用于热电设备，必须控制其载流子浓度。因此，我们将 WS2 薄膜暴露在 Cl2-等离子体中，作为一种掺杂方法。此外，还进行了 SVA 处理，以提高薄膜的结晶度，并可能引入活化掺杂剂。结果，经 Cl2- 等离子体处理的 PVD-WS2 薄膜的电导率（0.440 S/m）比未经处理的 PVD-WS2 薄膜的电导率（0.201 S/m）提高了一倍多。根据 X 射线光电子能谱中观察到的正峰值移动，本实验中的掺杂类型被认为是 n 型。
{"title":"Conductivity Enhancement of PVD-WS2 Films Using Cl2-Plasma Treatment Followed by Sulfur-Vapor Annealing","authors":"Keita Kurohara;Shinya Imai;Takuya Hamada;Tetsuya Tatsumi;Shigetaka Tomiya;Kuniyuki Kakushima;Kazuo Tsutsui;Hitoshi Wakabayashi","doi":"10.1109/JEDS.2024.3378745","DOIUrl":"10.1109/JEDS.2024.3378745","url":null,"abstract":"The conductivity of tungsten disulfide (WS2) films using sputtering, which is a physical vapor deposition (PVD), was enhanced using a chlorine (Cl2)-plasma treatment and sulfur-vapor annealing (SVA). For WS2 films to be used in thermoelectric devices, its carrier concentration must be controlled. Therefore, we exposed WS2 films to Cl2-plasma as a doping method. In addition, SVA was performed to improve the crystallinity of the film and potentially introduce activating dopants. Consequently, the conductivity of the Cl2-plasma-treated PVD-WS2 films (0.440 S/m) more than doubled compared with that of an untreated PVD-WS2 film (0.201 S/m). The doping type in this experiment is considered to be n-type on the basis of a positive peak shift observed in the X-ray photoelectron spectra.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10475166","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140171957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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