Pub Date : 2024-07-18DOI: 10.1109/JEDS.2024.3431289
Jie Luo;Yanyu Yang;Gangping Yan;Chuqiao Niu;Yunjiao Bao;Yupeng Lu;Zhengying Jiao;Jinjuan Xiang;Guilei Wang;Gaobo Xu;Huaxiang Yin;Chao Zhao;Jun Luo
Amorphous oxide semiconductor-thin film transistors (AOS-TFTs) have attracted considerable attention due to their impressive performance in various applications. However, there is a limited amount of study available on the reliability of AOS-TFTs. This work investigates the endurance and reliability mechanisms of Indium Gallium Zinc Oxide (IGZO) and Indium Tin Oxide (ITO) TFTs. The devices underwent a range of test conditions to evaluate their endurance properties. The study utilized Zero-Bias Endurance Tests (ZBET) to examine the fluctuating behaviors of threshold voltage, revealing valuable insights into the causes of electrical instability. The study highlights the crucial importance of electron depletion and restoration dynamics in affecting the reliability of TFTs. Additionally, the study found differences in the performance of IGZO-TFTs and ITO-TFTs, suggesting that the differing features of the materials have a significant impact on the endurance and reliability of TFTs.
{"title":"The Endurance and Reliability Mechanisms Investigation of InGaZnO and InSnO Thin Film Transistors","authors":"Jie Luo;Yanyu Yang;Gangping Yan;Chuqiao Niu;Yunjiao Bao;Yupeng Lu;Zhengying Jiao;Jinjuan Xiang;Guilei Wang;Gaobo Xu;Huaxiang Yin;Chao Zhao;Jun Luo","doi":"10.1109/JEDS.2024.3431289","DOIUrl":"10.1109/JEDS.2024.3431289","url":null,"abstract":"Amorphous oxide semiconductor-thin film transistors (AOS-TFTs) have attracted considerable attention due to their impressive performance in various applications. However, there is a limited amount of study available on the reliability of AOS-TFTs. This work investigates the endurance and reliability mechanisms of Indium Gallium Zinc Oxide (IGZO) and Indium Tin Oxide (ITO) TFTs. The devices underwent a range of test conditions to evaluate their endurance properties. The study utilized Zero-Bias Endurance Tests (ZBET) to examine the fluctuating behaviors of threshold voltage, revealing valuable insights into the causes of electrical instability. The study highlights the crucial importance of electron depletion and restoration dynamics in affecting the reliability of TFTs. Additionally, the study found differences in the performance of IGZO-TFTs and ITO-TFTs, suggesting that the differing features of the materials have a significant impact on the endurance and reliability of TFTs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"613-618"},"PeriodicalIF":2.0,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10604821","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141738247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The impacts of retrograde counter doping (RCD) profiles on low frequency noise (LFN) of buried channel (BC) PMOSFETs were investigated. RCD profiles were formed using heavy ion implantation. The RCD profile reduced LFN by more than 50%. The origin of LFN reduction in the RCD device was investigated using TCAD simulation. It was found that both RCD profile itself and the polarity of Si surface contributed to the deeper channel position and larger energy barrier between Si surface and channel position.
{"title":"Reduction of Low Frequency Noise of Buried Channel PMOSFETs With Retrograde Counter Doping Profiles","authors":"Shuntaro Fujii;Toshiro Sakamoto;Soichi Morita;Tsutomu Miyazaki","doi":"10.1109/JEDS.2024.3430308","DOIUrl":"10.1109/JEDS.2024.3430308","url":null,"abstract":"The impacts of retrograde counter doping (RCD) profiles on low frequency noise (LFN) of buried channel (BC) PMOSFETs were investigated. RCD profiles were formed using heavy ion implantation. The RCD profile reduced LFN by more than 50%. The origin of LFN reduction in the RCD device was investigated using TCAD simulation. It was found that both RCD profile itself and the polarity of Si surface contributed to the deeper channel position and larger energy barrier between Si surface and channel position.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"534-540"},"PeriodicalIF":2.0,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10601688","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141738342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-15DOI: 10.1109/JEDS.2024.3428969
Yatexu Patel;Pouya Valizadeh
In this manuscript, we have investigated the impact of the scaling of the gate-source length (LGS) and gate length (LG) on the output characterises and gate-transconductance (Gm) linearity of metallic-face InAlN/AlN/GaN heterostructure field effect transistors (HFETs) having fin structures only under the gate and those having them stretched from source to drain. Evidence for both device types suggests that the downscaling of LGS and LG augments the electron velocity in the source-access region, as a result of which the higher carrier density under the gated-channel improves the maximum drain-current density but not necessarily the $G_{m}$ linearity of the device. It is shown that the devices having a planar and longer source access region are exhibiting relatively improved gate-transconductance linearity. This is suggested to be due to their almost constant source access resistance (Rs). In addition, the downscaling of the LG is observed to have a positive influence on device linearity. This observation could be due to the larger exposure to the drain-induced barrier lowering (DIBL) and the resulting rush of the carriers from the source access region to the gated-channel, leading to the suppression of the increasing $R_{s}$ at higher drain currents.
在本手稿中，我们研究了栅源长度（LGS）和栅极长度（LG）的缩放对仅在栅极下具有鳍状结构的金属面 InAlN/AlN/GaN 异质结构场效应晶体管（HFET）的输出特性和栅极电感（Gm）线性的影响。这两种器件类型的证据表明，LGS 和 LG 的缩减提高了源极接入区的电子速度，因此栅极沟道下更高的载流子密度提高了器件的最大漏极电流密度，但不一定提高了器件的 $G_{m}$ 线性度。研究表明，具有平面和较长源接入区的器件的栅极-电导线性度相对较高。这是因为它们的源接入电阻 (Rs) 几乎恒定。此外，还观察到 LG 的缩小对器件线性度产生了积极影响。这一现象可能是由于更大程度地暴露于漏极致势垒降低（DIBL），以及由此导致的载流子从源极接入区涌向栅极沟道，从而抑制了在更高漏极电流下不断增加的 $R_{s}$。
{"title":"Investigation of the DC Performance and Linearity of InAlN/GaN HFETs via Studying the Impact of the Scaling of LGS and LG on the Source Access Resistance","authors":"Yatexu Patel;Pouya Valizadeh","doi":"10.1109/JEDS.2024.3428969","DOIUrl":"10.1109/JEDS.2024.3428969","url":null,"abstract":"In this manuscript, we have investigated the impact of the scaling of the gate-source length (LGS) and gate length (LG) on the output characterises and gate-transconductance (Gm) linearity of metallic-face InAlN/AlN/GaN heterostructure field effect transistors (HFETs) having fin structures only under the gate and those having them stretched from source to drain. Evidence for both device types suggests that the downscaling of LGS and LG augments the electron velocity in the source-access region, as a result of which the higher carrier density under the gated-channel improves the maximum drain-current density but not necessarily the \u0000<inline-formula> <tex-math>$G_{m}$ </tex-math></inline-formula>\u0000 linearity of the device. It is shown that the devices having a planar and longer source access region are exhibiting relatively improved gate-transconductance linearity. This is suggested to be due to their almost constant source access resistance (Rs). In addition, the downscaling of the LG is observed to have a positive influence on device linearity. This observation could be due to the larger exposure to the drain-induced barrier lowering (DIBL) and the resulting rush of the carriers from the source access region to the gated-channel, leading to the suppression of the increasing \u0000<inline-formula> <tex-math>$R_{s}$ </tex-math></inline-formula>\u0000 at higher drain currents.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"525-533"},"PeriodicalIF":2.0,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10599155","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141718883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-11DOI: 10.1109/JEDS.2024.3425989
{"title":"Bridging the Data Gap in Photovoltaics with Synthetic Data Generation","authors":"","doi":"10.1109/JEDS.2024.3425989","DOIUrl":"10.1109/JEDS.2024.3425989","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"704-705"},"PeriodicalIF":2.0,"publicationDate":"2024-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10596105","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141608881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-05DOI: 10.1109/JEDS.2024.3424545
Wenyang Zhang;Li Lu;Chenfei Li;Weijie Jiang;Wenzhao Wang;Xingqiang Liu;Ablat Abliz;Da Wan
Herein, highly stable nitrogen (N) doped amorphous indium gallium tin oxide (a-IGTO) thinfilm transistors (TFTs) are prepared and the effects of N-doping are investigated. Compared with undoped a-IGTO TFTs, a-IGTO TFTs with 6 min N plasma treatment exhibit superior bias stress stability and a threshold voltages ( $V_{mathrm {th}}$ ) closer to 0 V with almost no decline in mobility. In particular, the positive/negative bias stress threshold shift of N-doped a-IGTO TFTs is substantially reduced in both dark and light environment. The X-ray photoelectron spectroscopy analysis (XPS) and low frequency noise (LFN) are employed to study the mechanism of N-doping in a-IGTO TFTs. The XPS results indicate that appropriate amount of N-doping could enhance the bias stress stability and control the $V_{mathrm {th}}$ efficiently by passivating the defects such as oxygen vacancy in a-IGTO films. The LFN results illustrate that the average interfacial trap density could be reduced by N-doping. Overall, the strategy presented here is effective for preparing a-IGTO TFTs with enhanced stability for potential applications in future optoelectronic displays.
本文制备了高度稳定的氮（N）掺杂非晶铟镓锡氧化物（a-IGTO）薄膜晶体管（TFT），并研究了氮掺杂的影响。与未掺杂的 a-IGTO TFT 相比，经过 6 分钟 N 等离子体处理的 a-IGTO TFT 具有优异的偏压稳定性，阈值电压（$V_{mathrm {th}}$ ）接近 0 V，且迁移率几乎没有下降。特别是，掺杂 N 的 a-IGTO TFT 的正/负偏压阈值偏移在黑暗和光明环境中都大幅降低。X 射线光电子能谱分析（XPS）和低频噪声（LFN）被用来研究 a-IGTO TFT 中 N 掺杂的机理。XPS 结果表明，通过钝化 a-IGTO 薄膜中的氧空位等缺陷，适量的 N 掺杂可以增强偏压稳定性并有效控制 $V_{mmathrm {th}}$。LFN 结果表明，N 掺杂可以降低平均界面陷阱密度。总之，本文介绍的策略能有效制备出稳定性更强的 a-IGTO TFT，有望应用于未来的光电显示领域。
{"title":"Study of Highly Stable Nitrogen-Doped a-InGaSnO Thin-Film Transistors","authors":"Wenyang Zhang;Li Lu;Chenfei Li;Weijie Jiang;Wenzhao Wang;Xingqiang Liu;Ablat Abliz;Da Wan","doi":"10.1109/JEDS.2024.3424545","DOIUrl":"10.1109/JEDS.2024.3424545","url":null,"abstract":"Herein, highly stable nitrogen (N) doped amorphous indium gallium tin oxide (a-IGTO) thinfilm transistors (TFTs) are prepared and the effects of N-doping are investigated. Compared with undoped a-IGTO TFTs, a-IGTO TFTs with 6 min N plasma treatment exhibit superior bias stress stability and a threshold voltages (\u0000<inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula>\u0000) closer to 0 V with almost no decline in mobility. In particular, the positive/negative bias stress threshold shift of N-doped a-IGTO TFTs is substantially reduced in both dark and light environment. The X-ray photoelectron spectroscopy analysis (XPS) and low frequency noise (LFN) are employed to study the mechanism of N-doping in a-IGTO TFTs. The XPS results indicate that appropriate amount of N-doping could enhance the bias stress stability and control the \u0000<inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula>\u0000 efficiently by passivating the defects such as oxygen vacancy in a-IGTO films. The LFN results illustrate that the average interfacial trap density could be reduced by N-doping. Overall, the strategy presented here is effective for preparing a-IGTO TFTs with enhanced stability for potential applications in future optoelectronic displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"502-507"},"PeriodicalIF":2.0,"publicationDate":"2024-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10587190","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141572389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Flexible photodetector is crucial for the intelligent industrial applications. However, the optical-sensitive materials are usually grown in a high temperature and then transferred onto the flexible substrate. This paper reported a directly fabricated flexible photodetector based on TiO2-doped Graphene Nanosheets Embedded Carbon (GNEC)film. An Electron Cyclotron Resonance (ECR) system was employed to in-situ deposit TiO2-doped GNEC film on a polyimide substrate, which were subsequently sensitized with N719 dye to fabricate the TiO2@GNEC photodetector. The GNEC film contains vertically aligned Graphene Nanosheets (GNs), which exhibit high-density edge states. The edge states suppress the recombination rate of photo-generated electron-hole pairs, thereby significantly enhancing the photo-responsive performance. The photodetector demonstrates a high photo responsivity of 0.82 mA/W and a response time of 1.93 seconds. Due to the in-situ manufacturing capabilities of the ECR system, which avoids defects from secondary material transfers, the photodetector array exhibits excellent consistency and achieves clear recognition of light patterns in both flat and bent states.
{"title":"Directly Fabricated Flexible Photodetector Based on TiO₂-Doped Carbon Nanosheets Film","authors":"Yunlong Zhang;Xiaolin Li;Zhipeng Cao;Qiang Wu;Gong Chen;Bo Wen;Dongfeng Diao;Xi Zhang","doi":"10.1109/JEDS.2024.3422292","DOIUrl":"10.1109/JEDS.2024.3422292","url":null,"abstract":"Flexible photodetector is crucial for the intelligent industrial applications. However, the optical-sensitive materials are usually grown in a high temperature and then transferred onto the flexible substrate. This paper reported a directly fabricated flexible photodetector based on TiO2-doped Graphene Nanosheets Embedded Carbon (GNEC)film. An Electron Cyclotron Resonance (ECR) system was employed to in-situ deposit TiO2-doped GNEC film on a polyimide substrate, which were subsequently sensitized with N719 dye to fabricate the TiO2@GNEC photodetector. The GNEC film contains vertically aligned Graphene Nanosheets (GNs), which exhibit high-density edge states. The edge states suppress the recombination rate of photo-generated electron-hole pairs, thereby significantly enhancing the photo-responsive performance. The photodetector demonstrates a high photo responsivity of 0.82 mA/W and a response time of 1.93 seconds. Due to the in-situ manufacturing capabilities of the ECR system, which avoids defects from secondary material transfers, the photodetector array exhibits excellent consistency and achieves clear recognition of light patterns in both flat and bent states.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"677-681"},"PeriodicalIF":2.0,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10580991","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141511541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-01DOI: 10.1109/JEDS.2024.3421612
Shuxin Lin;Emad Iranmanesh;Lin Zhao;Weiwei Li;Haris Doumanidis;Hang Zhou;Kai Wang
This paper reports on an all-oxide thin film piezotronic P-N heterojunction diode incorporating vertically-stacked structure of N+-ITO/P-type nickel oxide/N-type zinc oxide as a flexible energy scavenger and its diode characteristics on signal regulation which simplifies an essential element for harvesting which is signal rectification circuitry. An energy band diagram, theoretical modeling and equivalent small-signal circuit elaborate its working principle and device physics. Signal amplification due to introduction of in-series capacitances related to junction formation has also been addressed. A preliminary experimental study demonstrates applicability of such a flexible energy scavenger in various gratis non-stop thrusts originating from human body motions such as: simple tapping (as in typing) and walking actions for generating $mu $ W-range power. Moreover, focusing on a simple power management system along with analysis of voltage waveforms in response to both resistive and capacitive loads unveils that the device is capable of quickly charging a capacitor and discharging it slowly allowing for possible energy storage. The estimation on generated power by a pixelated array that is obtainable due to ease of large-area fabrication processes and a single-pixel strip-based device exabits its feasibility as an energy source to power up some IoT nodes.
本文介绍了一种全氧化物薄膜压电 P-N 异质结二极管，它采用 N+-ITO/P 型氧化镍/N 型氧化锌的垂直叠层结构作为柔性能量清除器，其二极管在信号调节方面的特性简化了信号整流电路这一采集的基本要素。能带图、理论建模和等效小信号电路阐述了其工作原理和器件物理特性。此外，还讨论了由于引入与结形成相关的串联电容而导致的信号放大。初步实验研究表明，这种柔性能量清除器适用于源于人体运动的各种无偿不间断推力，例如：简单的敲击（如打字）和行走动作，以产生 $mu $ W 范围的功率。此外，对简单电源管理系统的关注，以及对响应电阻和电容负载的电压波形的分析，揭示了该设备能够对电容器快速充电和缓慢放电，从而实现可能的能量存储。由于大面积制造工艺和基于单像素条带的设备非常容易实现，因此对像素阵列产生的功率进行了估算，从而证明了其作为一种能源为某些物联网节点供电的可行性。
{"title":"Piezotronic N+ -ITO/P-NiO/N-ZnO Heterojunction Thin-Film Diode as a Flexible Energy Scavenger","authors":"Shuxin Lin;Emad Iranmanesh;Lin Zhao;Weiwei Li;Haris Doumanidis;Hang Zhou;Kai Wang","doi":"10.1109/JEDS.2024.3421612","DOIUrl":"10.1109/JEDS.2024.3421612","url":null,"abstract":"This paper reports on an all-oxide thin film piezotronic P-N heterojunction diode incorporating vertically-stacked structure of N+-ITO/P-type nickel oxide/N-type zinc oxide as a flexible energy scavenger and its diode characteristics on signal regulation which simplifies an essential element for harvesting which is signal rectification circuitry. An energy band diagram, theoretical modeling and equivalent small-signal circuit elaborate its working principle and device physics. Signal amplification due to introduction of in-series capacitances related to junction formation has also been addressed. A preliminary experimental study demonstrates applicability of such a flexible energy scavenger in various gratis non-stop thrusts originating from human body motions such as: simple tapping (as in typing) and walking actions for generating \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 W-range power. Moreover, focusing on a simple power management system along with analysis of voltage waveforms in response to both resistive and capacitive loads unveils that the device is capable of quickly charging a capacitor and discharging it slowly allowing for possible energy storage. The estimation on generated power by a pixelated array that is obtainable due to ease of large-area fabrication processes and a single-pixel strip-based device exabits its feasibility as an energy source to power up some IoT nodes.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"555-563"},"PeriodicalIF":2.0,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579821","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141511542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-24DOI: 10.1109/JEDS.2024.3417994
Ji-Hwan Park;Kyeong-Soo Kang;Chanjin Park;Soo-Yeon Lee
In this paper, we proposed a new low-temperature polycrystalline oxide (LTPO) thin-film transistor (TFT) pixel circuit for micro light-emitting diode (μ LED) displays that produces a highly stable and uniform driving current. The proposed pixel circuit suppresses the current level change along with the sweep signal due to the parasitic capacitances and compensates for the TFT's threshold voltage (VTH) variation-induced current error, including even falling shape. In addition, the proposed circuit produces a constant current regardless of the data voltage. As a result, a relative current error rate of less than 2% was achieved across all gray levels under the ±0.5 V VTH fluctuation. The proposed circuit was verified using HSPICE with a low-temperature polycrystalline silicon (LTPS) TFT and amorphous indium-galliumzinc- oxide (a-IGZO) TFT model based on the measured data. The simulation analysis confirmed that the optimal sweep signal input position and pulse width modulation (PWM) and constant current generation (CCG) parts connecting method were key design points for stable and uniform performance.
{"title":"A New 13T4C LTPO MicroLED Pixel Circuit Producing Highly Stable Driving Current by Minimizing Effect of Parasitic Capacitors and Stabilizing Capacitor Nodes","authors":"Ji-Hwan Park;Kyeong-Soo Kang;Chanjin Park;Soo-Yeon Lee","doi":"10.1109/JEDS.2024.3417994","DOIUrl":"10.1109/JEDS.2024.3417994","url":null,"abstract":"In this paper, we proposed a new low-temperature polycrystalline oxide (LTPO) thin-film transistor (TFT) pixel circuit for micro light-emitting diode (μ LED) displays that produces a highly stable and uniform driving current. The proposed pixel circuit suppresses the current level change along with the sweep signal due to the parasitic capacitances and compensates for the TFT's threshold voltage (VTH) variation-induced current error, including even falling shape. In addition, the proposed circuit produces a constant current regardless of the data voltage. As a result, a relative current error rate of less than 2% was achieved across all gray levels under the ±0.5 V VTH fluctuation. The proposed circuit was verified using HSPICE with a low-temperature polycrystalline silicon (LTPS) TFT and amorphous indium-galliumzinc- oxide (a-IGZO) TFT model based on the measured data. The simulation analysis confirmed that the optimal sweep signal input position and pulse width modulation (PWM) and constant current generation (CCG) parts connecting method were key design points for stable and uniform performance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"472-478"},"PeriodicalIF":2.0,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10568954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141608753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Using a 3-D monolithic stacking memory technology of crystalline oxide semiconductor (OS) transistors, we fabricated a test chip having AI accelerator (ACC) memory for weight data of a neural network (NN), backup memory of flip-flops (FF), and CPU memory storing instructions and data. These memories are composed of two-layer OS transistors on Si CMOS, where memories in each layer correspond to a bank. In this structure, bank switching of the ACC memory and the FF backup memory work together, and thus inference of different NNs is switched with low latency and low power so that the power gating standby time can be extended. Consequently, a 92% reduction in power consumption is achieved in inference at a frame rate of 60 fps as compared with a chip using static random access memory (SRAM) as the ACC memory.
利用晶体氧化物半导体（OS）晶体管的三维单片堆叠存储器技术，我们制造出了一款测试芯片，其中包括用于神经网络（NN）权重数据的人工智能加速器（ACC）存储器、触发器（FF）备份存储器以及存储指令和数据的 CPU 存储器。这些存储器由 Si CMOS 上的两层 OS 晶体管组成，每一层的存储器对应一个组。在这种结构中，ACC 存储器和 FF 备用存储器的组切换是协同工作的，因此不同 NN 的推理切换具有低延迟和低功耗的特点，从而延长了电源门控的待机时间。因此，与使用静态随机存取存储器（SRAM）作为 ACC 存储器的芯片相比，在帧速率为 60 fps 的推理过程中，功耗降低了 92%。
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Pub Date : 2024-06-24DOI: 10.1109/JEDS.2024.3418212
Eunyoung Park;Hyun-Yong Yu
Recently, a new structure called PUC has been introduced, in which the periphery is located below the NAND cell to reduce chip area. However, as the SiN-based cell alloy process progresses during the NAND manufacturing process, there is a problem in that excess hydrogen is injected into the peripheral transistor, resulting in degradation of reliability. Therefore, we propose the hydrogen diffusion model in PUC to investigate the degradation of peripheral transistor by excess hydrogen using Sentaurus 3D technology Computer-Aided Design (TCAD) and suggest an optimal process to improve reliability. As a result, by applying the bonding process and adjusting the cell alloy process sequence, the amount of excess hydrogen injection is reduced by 87% and the NBTI lifetime showed about 8.3 times greater result and TDDB breakdown time improved more than 9.1 times compared to the PUC structure made through a sequential process. Additionally, this process effectively alleviates excess hydrogen injection in the NAND cell with an increased number of WL. These results could provide critical insight for designing a PUC that ensures the reliability of peripheral transistor.
{"title":"Effective Reduction of Hydrogen Diffusion and Reliability Degradation in Peripheral Transistor of Peripheral-Under-Cell (PUC) NAND Flash Memory","authors":"Eunyoung Park;Hyun-Yong Yu","doi":"10.1109/JEDS.2024.3418212","DOIUrl":"10.1109/JEDS.2024.3418212","url":null,"abstract":"Recently, a new structure called PUC has been introduced, in which the periphery is located below the NAND cell to reduce chip area. However, as the SiN-based cell alloy process progresses during the NAND manufacturing process, there is a problem in that excess hydrogen is injected into the peripheral transistor, resulting in degradation of reliability. Therefore, we propose the hydrogen diffusion model in PUC to investigate the degradation of peripheral transistor by excess hydrogen using Sentaurus 3D technology Computer-Aided Design (TCAD) and suggest an optimal process to improve reliability. As a result, by applying the bonding process and adjusting the cell alloy process sequence, the amount of excess hydrogen injection is reduced by 87% and the NBTI lifetime showed about 8.3 times greater result and TDDB breakdown time improved more than 9.1 times compared to the PUC structure made through a sequential process. Additionally, this process effectively alleviates excess hydrogen injection in the NAND cell with an increased number of WL. These results could provide critical insight for designing a PUC that ensures the reliability of peripheral transistor.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"752-759"},"PeriodicalIF":2.0,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10568956","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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