Pub Date : 2025-06-02DOI: 10.1109/JEDS.2025.3575706
Martin Ćalasan;Snežana Vujošević;Kristina Bakić
This paper highlights significant advancements in the creation and enhancement of equivalent circuit models for solar cells. First, two novel configurations are proposed to enhance the classic single-diode model: one adds a diode between the terminal connections, while the other inserts a diode and resistor in series between the same terminals. Second, original analytical expressions for the current-voltage (I-V) characteristics of each proposed circuit are derived using the Lambert W function. Third, the performance of these models is rigorously evaluated on a variety of solar cells under diverse environmental conditions. Results demonstrated the models’ accuracy and robustness, with Root Mean Square Error (RMSE) analysis showing superior alignment between simulated and experimental I-V curves compared to existing single-, double-, and triple-diode solar cell models from the literature. Finally, the proposed approach enhances the mathematical precision in modeling solar cell behavior and provides a reliable framework for optimizing solar energy systems, contributing to improved performance and efficiency in practical applications.
{"title":"Enhanced Single-Diode Solar Cell Model: Analytical Solutions Using Lambert W Function and Circuit Innovations","authors":"Martin Ćalasan;Snežana Vujošević;Kristina Bakić","doi":"10.1109/JEDS.2025.3575706","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3575706","url":null,"abstract":"This paper highlights significant advancements in the creation and enhancement of equivalent circuit models for solar cells. First, two novel configurations are proposed to enhance the classic single-diode model: one adds a diode between the terminal connections, while the other inserts a diode and resistor in series between the same terminals. Second, original analytical expressions for the current-voltage (I-V) characteristics of each proposed circuit are derived using the Lambert W function. Third, the performance of these models is rigorously evaluated on a variety of solar cells under diverse environmental conditions. Results demonstrated the models’ accuracy and robustness, with Root Mean Square Error (RMSE) analysis showing superior alignment between simulated and experimental I-V curves compared to existing single-, double-, and triple-diode solar cell models from the literature. Finally, the proposed approach enhances the mathematical precision in modeling solar cell behavior and provides a reliable framework for optimizing solar energy systems, contributing to improved performance and efficiency in practical applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"501-509"},"PeriodicalIF":2.0,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11020651","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-cell is discharging process from storage node (SN) to bit line, achieving in-cell threshold voltage (VTH) compensation without sacrificing bit-cell layout. VTH modulation derived from the top gate of read transistor makes noticeable $Delta $ VSN boosting, with a record-high ratio ($Delta $ VSN/$Delta $ VDATA) of 1.46, which improves the headroom for multi-bit storage. Moreover, the optimized transistors with positive VTH and high ON-state current enable long retention time (>1500 s) and ultra-fast writing speed (< 10 ns). Under the synergistic effect of VTH compensation and $Delta $ VSN boosting, non-overlap 3-bit storage operation among 25 cells is achieved with one order reduction of standard deviation. This study establishes a critical foundation for implementing multi-bit storage applications of IGZO 2T0C DRAM in large-scale array.
{"title":"IGZO 2T0C DRAM With VTH Compensation Technique for Multi-Bit Applications","authors":"Kaifei Chen;Wendong Lu;Jiebin Niu;Menggan Liu;Fuxi Liao;Xuanming Zhang;Zihan Li;Naide Mao;Kaiping Zhang;Congyan Lu;Bok-Moon Kang;Jiawei Wang;Di Geng;Nianduan Lu;Guilei Wang;Zhengyong Zhu;Guanhua Yang;Chao Zhao;Arokia Nathan;Ling Li;Ming Liu","doi":"10.1109/JEDS.2025.3565658","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3565658","url":null,"abstract":"In this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-cell is discharging process from storage node (SN) to bit line, achieving in-cell threshold voltage (VTH) compensation without sacrificing bit-cell layout. VTH modulation derived from the top gate of read transistor makes noticeable <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VSN boosting, with a record-high ratio (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VSN/<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VDATA) of 1.46, which improves the headroom for multi-bit storage. Moreover, the optimized transistors with positive VTH and high ON-state current enable long retention time (>1500 s) and ultra-fast writing speed (< 10 ns). Under the synergistic effect of VTH compensation and <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VSN boosting, non-overlap 3-bit storage operation among 25 cells is achieved with one order reduction of standard deviation. This study establishes a critical foundation for implementing multi-bit storage applications of IGZO 2T0C DRAM in large-scale array.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"439-443"},"PeriodicalIF":2.0,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10979978","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144090732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-28DOI: 10.1109/JEDS.2025.3562252
{"title":"Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/JEDS.2025.3562252","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562252","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1078-1079"},"PeriodicalIF":2.0,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10978963","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-25DOI: 10.1109/JEDS.2025.3564212
Muhammad Mainul Islam;Mohammad Adnaan;Sou-Chi Chang;Hai Li;Ian A. Young;Azad Naeemi
Here, we present a compact model based on multidomain phase-field approach that can capture the hysteresis loop and the transient negative capacitance (NC) regions in Metal-Antiferroelectric-Metal structures. The model solves time-dependent Ginzburg-Landau (TDGL) and Poisson equation self-consistently to evaluate the polarization and potential distribution, respectively. We also discuss the significance of a dynamic kinetic coefficient to accurately capture the NC effect in antiferroelectric (AFE) capacitors. The proposed model adeptly captures all four transient NC regions (two antiferroelectric to ferroelectric transitions and two ferroelectric to antiferroelectric transitions) observed during a full switching cycle of an antiferroelectric capacitor.
{"title":"Investigating the Switching Dynamics of Antiferroelectric Capacitor Using Multidomain Phase-Field Approach","authors":"Muhammad Mainul Islam;Mohammad Adnaan;Sou-Chi Chang;Hai Li;Ian A. Young;Azad Naeemi","doi":"10.1109/JEDS.2025.3564212","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3564212","url":null,"abstract":"Here, we present a compact model based on multidomain phase-field approach that can capture the hysteresis loop and the transient negative capacitance (NC) regions in Metal-Antiferroelectric-Metal structures. The model solves time-dependent Ginzburg-Landau (TDGL) and Poisson equation self-consistently to evaluate the polarization and potential distribution, respectively. We also discuss the significance of a dynamic kinetic coefficient to accurately capture the NC effect in antiferroelectric (AFE) capacitors. The proposed model adeptly captures all four transient NC regions (two antiferroelectric to ferroelectric transitions and two ferroelectric to antiferroelectric transitions) observed during a full switching cycle of an antiferroelectric capacitor.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"422-426"},"PeriodicalIF":2.0,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10977732","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143943783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-24DOI: 10.1109/JEDS.2025.3563981
K. Murawski;K. Majkowycz;K. Michalczewski;J. Jureńczyk;Ł. Kubiszyn;T. Manyk;M. Kopytko;B. Seredyński;P. Martyniuk
The paper presents an analysis of the miniband transitions of long- infrared (LWIR) interband cascade photodetectors (ICIP), with type-II superlattices (T2SLs), gallium-free (“Ga-free”) InAs/InAsSb (xSb ${=}0.39$ ) absorber, grown by molecular beam epitaxy (MBE) on a GaAs (001) substrate. The results collected based on the photoluminescence (PL) and spectral response (SR) measurements were combined with theoretical calculations using the ($8times 8$ Hamiltonian) k$cdot $ p model for both strained and strain-free structure. The temperature dependence of HH${_{{1}}} rightarrow $ C1, LH${_{{1}}} rightarrow $ C1, SO$rightarrow $ C1 and HH${_{{1}}} rightarrow $ C1 was determined. Their respective 300 K energies were 114 meV, 195 meV, 290 meV and 380 meV, respectively. Moreover, the Varshni parameters were determined. For the PL results, 85 meV was observed across the entire temperature range. Remarkably, at cryogenic temperatures additional blue-shifted 5 meV and 14 meV transitions within the energy gap (Eg) occurred, respectively.
{"title":"Analysis of InAs/InAsSb Superlattice Miniband Positions for a Cascade LWIR Detector","authors":"K. Murawski;K. Majkowycz;K. Michalczewski;J. Jureńczyk;Ł. Kubiszyn;T. Manyk;M. Kopytko;B. Seredyński;P. Martyniuk","doi":"10.1109/JEDS.2025.3563981","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3563981","url":null,"abstract":"The paper presents an analysis of the miniband transitions of long- infrared (LWIR) interband cascade photodetectors (ICIP), with type-II superlattices (T2SLs), gallium-free (“Ga-free”) InAs/InAsSb (xSb <inline-formula> <tex-math>${=}0.39$ </tex-math></inline-formula>) absorber, grown by molecular beam epitaxy (MBE) on a GaAs (001) substrate. The results collected based on the photoluminescence (PL) and spectral response (SR) measurements were combined with theoretical calculations using the (<inline-formula> <tex-math>$8times 8$ </tex-math></inline-formula> Hamiltonian) k<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>p model for both strained and strain-free structure. The temperature dependence of HH<inline-formula> <tex-math>${_{{1}}} rightarrow $ </tex-math></inline-formula>C1, LH<inline-formula> <tex-math>${_{{1}}} rightarrow $ </tex-math></inline-formula>C1, SO<inline-formula> <tex-math>$rightarrow $ </tex-math></inline-formula>C1 and HH<inline-formula> <tex-math>${_{{1}}} rightarrow $ </tex-math></inline-formula>C1 was determined. Their respective 300 K energies were 114 meV, 195 meV, 290 meV and 380 meV, respectively. Moreover, the Varshni parameters were determined. For the PL results, 85 meV was observed across the entire temperature range. Remarkably, at cryogenic temperatures additional blue-shifted 5 meV and 14 meV transitions within the energy gap (Eg) occurred, respectively.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"390-395"},"PeriodicalIF":2.0,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10975787","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143913400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-23DOI: 10.1109/JEDS.2025.3563644
Xiaotian Tang;Qimeng Jiang;Sen Huang;Xinhua Wang;Xinyu Liu
The lossless and accurate current sensing technology is highly desirable for feedback control, fast over-current protection, and diagnostics-prognostics development for high-frequency and high-efficiency power systems. The SenseFET technology, where a current sensor is monolithically integrated with a power transistor, has been widely used in power ICs due to its high precision and low cost. However, for a gallium nitride (GaN) lateral power device in multi-finger configurations, the non-uniform temperature distribution hinders its application in high-precision scenarios. This paper aims to address this issue through a design method of SenseFETs based on a lumped parameter electro-thermal network (LPETN) model. Based on the proposed model, the time-dependent temperature and conduction current distribution are obtained, and the optimized finger selection for the accurate current sense is performed. The thermal network part of the model is validated by the finite element method (FEM) results, and the electrical part is validated through LTSPICE simulation. Finally, taking a 50-finger GaN high electron mobility transistor (HEMT) device as an example, this model is used to select the fingers of a SenseFET for current sensing. Compared with the traditional method, the proposed approach significantly improves the accuracy of the SenseFET, which demonstrates its effectiveness.
{"title":"High-Precision GaN-Based-SenseFET Design Based on a Lumped Parameter Electro-Thermal Network Model","authors":"Xiaotian Tang;Qimeng Jiang;Sen Huang;Xinhua Wang;Xinyu Liu","doi":"10.1109/JEDS.2025.3563644","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3563644","url":null,"abstract":"The lossless and accurate current sensing technology is highly desirable for feedback control, fast over-current protection, and diagnostics-prognostics development for high-frequency and high-efficiency power systems. The SenseFET technology, where a current sensor is monolithically integrated with a power transistor, has been widely used in power ICs due to its high precision and low cost. However, for a gallium nitride (GaN) lateral power device in multi-finger configurations, the non-uniform temperature distribution hinders its application in high-precision scenarios. This paper aims to address this issue through a design method of SenseFETs based on a lumped parameter electro-thermal network (LPETN) model. Based on the proposed model, the time-dependent temperature and conduction current distribution are obtained, and the optimized finger selection for the accurate current sense is performed. The thermal network part of the model is validated by the finite element method (FEM) results, and the electrical part is validated through LTSPICE simulation. Finally, taking a 50-finger GaN high electron mobility transistor (HEMT) device as an example, this model is used to select the fingers of a SenseFET for current sensing. Compared with the traditional method, the proposed approach significantly improves the accuracy of the SenseFET, which demonstrates its effectiveness.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"414-421"},"PeriodicalIF":2.0,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10974612","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-21DOI: 10.1109/JEDS.2025.3562752
Hung-Chi Han;Edoardo Charbon;Christian Enz
Radio-frequency (RF) circuits are crucial to qubit manipulation, for which transistor self-heating effects may influence performance and possibly change the quantum state. This paper presents an analytical RF model of FDSOI MOSFETs considering dynamic self-heating effects down to 3.3 K for the first time. Parameter extraction involves analytical calculation and optimization using the iteratively re-weighted least squares (IRLS) and Monte Carlo methods. The temperature rise is estimated by capturing the correlation between thermal resistance and device temperature. This work provides a method for modeling FDSOI RF performance and for analyzing dynamic self-heating effects at cryogenic temperatures.
{"title":"Self-Heating Effects in RF Region of FDSOI MOSFETs at Cryogenic Temperatures","authors":"Hung-Chi Han;Edoardo Charbon;Christian Enz","doi":"10.1109/JEDS.2025.3562752","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562752","url":null,"abstract":"Radio-frequency (RF) circuits are crucial to qubit manipulation, for which transistor self-heating effects may influence performance and possibly change the quantum state. This paper presents an analytical RF model of FDSOI MOSFETs considering dynamic self-heating effects down to 3.3 K for the first time. Parameter extraction involves analytical calculation and optimization using the iteratively re-weighted least squares (IRLS) and Monte Carlo methods. The temperature rise is estimated by capturing the correlation between thermal resistance and device temperature. This work provides a method for modeling FDSOI RF performance and for analyzing dynamic self-heating effects at cryogenic temperatures.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"396-405"},"PeriodicalIF":2.0,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10970722","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143913348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There is increasing interest in affordable and flexible electronics, driven by the need for displays, conformable body sensors, and Internet-of-Things (IoT) gadgets. Amorphous silicon (a-Si:H), transition metal oxides, and organic thin-film transistors (TFTs) have demonstrated cost-effective large-scale production. As TFTs are typically unipolar in nature, they pose challenges for implementing CMOS-like circuits. Conventional methods to realize circuits in these technologies often lead to restricted voltage swing and excessive direct path current. While several methods have been proposed to counter the voltage swing issue, these methods fail to address the direct path current problem. This article presents low static-power D flip-flops (DFFs) using unipolar TFTs, which significantly reduces the direct path current. The proposed and conventional DFF designs were fabricated on a glass and flexible substrate using a-Si:H TFTs. Additionally, the impact of bending the flexible substrates was examined to assess the robustness and performance of the DFFs under mechanical strain. The measurement results show that the proposed design based DFF saves average total power by 79.8% compared to conventional design.
{"title":"A Low Static-Power D Flip-Flop With Unipolar Thin Film Transistors on a Flexible Substrate","authors":"Shubham Ranjan;Sparsh Kapar;Czang-Ho Lee;William Wong;Manoj Sachdev","doi":"10.1109/JEDS.2025.3562575","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562575","url":null,"abstract":"There is increasing interest in affordable and flexible electronics, driven by the need for displays, conformable body sensors, and Internet-of-Things (IoT) gadgets. Amorphous silicon (a-Si:H), transition metal oxides, and organic thin-film transistors (TFTs) have demonstrated cost-effective large-scale production. As TFTs are typically unipolar in nature, they pose challenges for implementing CMOS-like circuits. Conventional methods to realize circuits in these technologies often lead to restricted voltage swing and excessive direct path current. While several methods have been proposed to counter the voltage swing issue, these methods fail to address the direct path current problem. This article presents low static-power D flip-flops (DFFs) using unipolar TFTs, which significantly reduces the direct path current. The proposed and conventional DFF designs were fabricated on a glass and flexible substrate using a-Si:H TFTs. Additionally, the impact of bending the flexible substrates was examined to assess the robustness and performance of the DFFs under mechanical strain. The measurement results show that the proposed design based DFF saves average total power by 79.8% compared to conventional design.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"406-413"},"PeriodicalIF":2.0,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10970726","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143913349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a reliable multistate RRAM device based on a Cu/Ta2O5/WO${}_{text {3-x}}$ /Pt structure, utilizing fully CMOS-compatible materials. The device demonstrates four distinct resistive states under varying switching voltages, achieving a swift response time of 25 ns and an on/off ratio exceeding $10{^{{4}}}$ . Additionally, it demonstrates a robust data retention time exceeding $10^{6}$ seconds and endures more than $10^{4}$ pulses in endurance tests. Statistical analysis conducted over 100 cycles across ten devices reveals consistent resistance characteristics, with variations maintained below 10%. Leveraging these advantages, the RRAM devices were integrated with MOS transistors to construct a 4T2R unit-based array, enabling reconfigurable applications such as analog voltage-based content-addressable memory (CAM) and in-memory computing (IMC) accelerators. Notably, the proposed solution reduces energy consumption by over 20% in CAM applications and significantly enhances energy efficiency for fingerprint recognition tasks through convolution operations, achieving more than three times the energy efficiency compared to conventional GPU and CPU systems while maintaining an accuracy of 98%.
{"title":"Reliable Multistate RRAM Devices for Reconfigurable CAM and IMC Applications","authors":"Shengpeng Xing;Zijian Wang;Zhen Wang;Pengtao Li;Xuemeng Fan;Ziyang Zhang;Guobin Zhang;Jianhao Kan;Qi Luo;Shuai Zhong;Yishu Zhang","doi":"10.1109/JEDS.2025.3562399","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562399","url":null,"abstract":"This work presents a reliable multistate RRAM device based on a Cu/Ta2O5/WO<inline-formula> <tex-math>${}_{text {3-x}}$ </tex-math></inline-formula>/Pt structure, utilizing fully CMOS-compatible materials. The device demonstrates four distinct resistive states under varying switching voltages, achieving a swift response time of 25 ns and an on/off ratio exceeding <inline-formula> <tex-math>$10{^{{4}}}$ </tex-math></inline-formula>. Additionally, it demonstrates a robust data retention time exceeding <inline-formula> <tex-math>$10^{6}$ </tex-math></inline-formula> seconds and endures more than <inline-formula> <tex-math>$10^{4}$ </tex-math></inline-formula> pulses in endurance tests. Statistical analysis conducted over 100 cycles across ten devices reveals consistent resistance characteristics, with variations maintained below 10%. Leveraging these advantages, the RRAM devices were integrated with MOS transistors to construct a 4T2R unit-based array, enabling reconfigurable applications such as analog voltage-based content-addressable memory (CAM) and in-memory computing (IMC) accelerators. Notably, the proposed solution reduces energy consumption by over 20% in CAM applications and significantly enhances energy efficiency for fingerprint recognition tasks through convolution operations, achieving more than three times the energy efficiency compared to conventional GPU and CPU systems while maintaining an accuracy of 98%.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"383-389"},"PeriodicalIF":2.0,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10969850","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work demonstrates high-performance vertical NiO/Ga2O3 heterojunction diodes (HJDs) with a 2-step space-modulated junction termination extension. Distinct from the current state-of-the-art Ga2O3 HJDs, we achieve breakdown voltage exceeding 3 kV with a low turn on voltage (VON) of 0.8V, estimated at a forward current density (IF) of 1 $A-cm^{text {-2}}$ . The measured devices exhibit excellent turn-on characteristics achieving 100 $A-cm^{text {-2}}$ current density at a forward bias of 1.5V along with a low differential specific on-resistance (Ron,sp) of 4.4 m$Omega $ -cm2. The SM-JTE was realized using concentric NiO rings with varying widths and spacing that approximates a gradual reduction in JTE charge. The unipolar figure of merit (FOM) calculated exceeds 2 GW-cm2 and is among the best reported for devices with a sub-1V turn-on. The fabricated devices also displayed minimal change in forward I-V characteristics post reverse bias stress of 3 kV applied during breakdown voltage testing.
这项工作展示了高性能的垂直NiO/Ga2O3异质结二极管（HJDs），具有两步空间调制结终端扩展。与目前最先进的Ga2O3 HJDs不同，我们以0.8V的低导通电压（VON）实现了超过3kv的击穿电压，估计正向电流密度（IF）为1 $ a -cm^{text{-2}}$。所测器件具有优异的导通特性，在正向偏置1.5V下实现100 $ a -cm^{text{-2}}$电流密度，并具有4.4 m $Omega $ -cm2的低差分比导通电阻（Ron,sp）。SM-JTE采用不同宽度和间距的同心NiO环来实现，近似于逐渐减少JTE电荷。计算出的单极性能值（FOM）超过2 GW-cm2，是具有sub-1V导通的器件的最佳报告之一。在击穿电压测试中施加3kv反向偏置应力后，制备的器件也显示出最小的正向I-V特性变化。
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