Pub Date : 2025-07-11DOI: 10.1109/JEDS.2025.3588210
Pingyu Cao;Kepeng Zhao;Yihao Xu;Harm Van Zalinge;Sang Lam;Ping Zhang;Miao Cui;Fei Xue
A monolithically integrated voltage reference based on p-GaN HEMT technology is demonstrated in this work. The proposed two-stage structure can improve the stability of the generated reference voltage over a wide range of the supply voltage and temperature. The static and dynamic performance was measured at various temperatures. Experimental results indicate that the output voltage is stable at 1.3 V when the supply voltage rises from 2.8 V to 40 V, with a line sensitivity of 0.035%/V at room temperature. When the measurement temperature increases to $250~{^{circ }}$ C, the generated reference voltage slightly decreases to 1.25 V with a temperature coefficient of −22.1 ppm/°C. The power supply rejection ratio of this work is competitive, as the power supply rejection ratio changes from −46.64 dB to −56.2 dB, in which the noise frequency varies from 10 Hz to 5 MHz. The voltage variation of the generated reference voltage is relatively small when the frequency exceeds 5 MHz. The results show that the proposed work is particularly suitable for all-GaN monolithic integration circuits that require thermally stable bias voltages with high immunity to the supply voltage variation.
{"title":"A p-GaN HEMT Voltage Reference With High Line Sensitivity and Power Supply Rejection Ratio","authors":"Pingyu Cao;Kepeng Zhao;Yihao Xu;Harm Van Zalinge;Sang Lam;Ping Zhang;Miao Cui;Fei Xue","doi":"10.1109/JEDS.2025.3588210","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588210","url":null,"abstract":"A monolithically integrated voltage reference based on p-GaN HEMT technology is demonstrated in this work. The proposed two-stage structure can improve the stability of the generated reference voltage over a wide range of the supply voltage and temperature. The static and dynamic performance was measured at various temperatures. Experimental results indicate that the output voltage is stable at 1.3 V when the supply voltage rises from 2.8 V to 40 V, with a line sensitivity of 0.035%/V at room temperature. When the measurement temperature increases to <inline-formula> <tex-math>$250~{^{circ }}$ </tex-math></inline-formula>C, the generated reference voltage slightly decreases to 1.25 V with a temperature coefficient of −22.1 ppm/°C. The power supply rejection ratio of this work is competitive, as the power supply rejection ratio changes from −46.64 dB to −56.2 dB, in which the noise frequency varies from 10 Hz to 5 MHz. The voltage variation of the generated reference voltage is relatively small when the frequency exceeds 5 MHz. The results show that the proposed work is particularly suitable for all-GaN monolithic integration circuits that require thermally stable bias voltages with high immunity to the supply voltage variation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"630-637"},"PeriodicalIF":2.4,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11078414","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-11DOI: 10.1109/JEDS.2025.3588180
Taeyoung Cho;Jesun Park;Sungyeop Jung;Myounggon Kang
This paper analyzes the intrinsic capacitance of enhancement-mode (e-mode) Gallium Nitridebased High Electron Mobility Transistor (GaN HEMTs). The intrinsic capacitance was measured using $C_{i s s}$ (input capacitance), $C_{o s s}$ (output capacitance), and $C_{r s s}$ (reverse transfer capacitance). The $C_{o s s}$ was also analyzed. Based on depletion-mode (d-mode) measurement data from the MIT virtual source GaN HEMT (MVSG) compact model, a measurement circuit for $C_{i s s}, C_{o s s}$ and $C_{r s s}$ was constructed and calibrated for reliability. Subsequently, the circuit, initially configured for d-mode GaN HEMT intrinsic capacitance measurements, was optimized for e-mode GaN HEMT, upon which intrinsic capacitance was measured. The influence on the graph was analyzed by varying parameters in the measured capacitance data, leading to the modeling of intrinsic capacitance.
分析了增强型氮化镓基高电子迁移率晶体管（GaN HEMTs）的本征电容。本征电容采用$C_{i s s}$（输入电容）、$C_{o s}$（输出电容）和$C_{r s s}$（反向传递电容）测量。对$C_{0 s}$也进行了分析。基于MIT虚拟源GaN HEMT （MVSG）紧凑模型的耗尽模式（d-mode）测量数据，构建了$C_{i s s}、$C_{o s s}$和$C_{r s s}$的测量电路，并对其进行了可靠性校准。随后，将最初配置用于d模GaN HEMT固有电容测量的电路优化为用于e模GaN HEMT，并在此基础上测量固有电容。通过改变测量电容数据中的参数来分析对图形的影响，从而建立本征电容的模型。
{"title":"Analysis and Modeling of Intrinsic Capacitance in Enhancement Mode GaN HEMT","authors":"Taeyoung Cho;Jesun Park;Sungyeop Jung;Myounggon Kang","doi":"10.1109/JEDS.2025.3588180","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588180","url":null,"abstract":"This paper analyzes the intrinsic capacitance of enhancement-mode (e-mode) Gallium Nitridebased High Electron Mobility Transistor (GaN HEMTs). The intrinsic capacitance was measured using <inline-formula> <tex-math>$C_{i s s}$ </tex-math></inline-formula> (input capacitance), <inline-formula> <tex-math>$C_{o s s}$ </tex-math></inline-formula> (output capacitance), and <inline-formula> <tex-math>$C_{r s s}$ </tex-math></inline-formula> (reverse transfer capacitance). The <inline-formula> <tex-math>$C_{o s s}$ </tex-math></inline-formula> was also analyzed. Based on depletion-mode (d-mode) measurement data from the MIT virtual source GaN HEMT (MVSG) compact model, a measurement circuit for <inline-formula> <tex-math>$C_{i s s}, C_{o s s}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$C_{r s s}$ </tex-math></inline-formula> was constructed and calibrated for reliability. Subsequently, the circuit, initially configured for d-mode GaN HEMT intrinsic capacitance measurements, was optimized for e-mode GaN HEMT, upon which intrinsic capacitance was measured. The influence on the graph was analyzed by varying parameters in the measured capacitance data, leading to the modeling of intrinsic capacitance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"638-641"},"PeriodicalIF":2.4,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11078449","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-03DOI: 10.1109/JEDS.2025.3585619
Bo Chen;Yifan Wu;Yuwei Qu;Anlin Liu;Yuzhe Hu;Pengpeng Sang;Jixuan Wu;Xuepeng Zhan;Jiezhi Chen
Hardware neural networks based on emerging nonvolatile memory are promising candidates to overcome the Von Neumann computing bottleneck. This study investigates the device characteristics and reliability of ferroelectric field-effect transistors (FeFETs) with a focus on their temperature-dependent performance. At 300 K, the FeFET demonstrates a 6.2 V memory window (MW) with 26.4% endurance degradation after 107 program/erase (P/E) cycles and 92.39% retention after 104 s. The accelerated charge trapping/detrapping dynamics enable superior short-term memory (STM) functionality. Remarkably, cryogenic operation at 77 K enhances the MW to 8 V while achieving exceptional stability with merely 0.4% degradation after 107 cycles and 99.02% retention at 104 seconds. The enhanced characteristics make it ideal for long-term memory (LTM) applications. Moreover, a reservoir computing (RC) network is proposed based on the cross-temperature FeFETs. By integrating the STM properties at 300 K and the LTM benefits at 77 K, the proposed RC network achieves a classification accuracy of 76.73% on the CIFAR-10 image recognition task. This surpasses the standalone results of 41.65% and 23.69% of 300 K and 77 K conditions, respectively. The findings highlight the potential to develop highly energy-efficient FeFET-based neuromorphic computing with varying temperature systems.
{"title":"Cross-Temperature FeFETs Enabling Long- and Short-Term Memory for Reservoir Computing Network","authors":"Bo Chen;Yifan Wu;Yuwei Qu;Anlin Liu;Yuzhe Hu;Pengpeng Sang;Jixuan Wu;Xuepeng Zhan;Jiezhi Chen","doi":"10.1109/JEDS.2025.3585619","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3585619","url":null,"abstract":"Hardware neural networks based on emerging nonvolatile memory are promising candidates to overcome the Von Neumann computing bottleneck. This study investigates the device characteristics and reliability of ferroelectric field-effect transistors (FeFETs) with a focus on their temperature-dependent performance. At 300 K, the FeFET demonstrates a 6.2 V memory window (MW) with 26.4% endurance degradation after 107 program/erase (P/E) cycles and 92.39% retention after 104 s. The accelerated charge trapping/detrapping dynamics enable superior short-term memory (STM) functionality. Remarkably, cryogenic operation at 77 K enhances the MW to 8 V while achieving exceptional stability with merely 0.4% degradation after 107 cycles and 99.02% retention at 104 seconds. The enhanced characteristics make it ideal for long-term memory (LTM) applications. Moreover, a reservoir computing (RC) network is proposed based on the cross-temperature FeFETs. By integrating the STM properties at 300 K and the LTM benefits at 77 K, the proposed RC network achieves a classification accuracy of 76.73% on the CIFAR-10 image recognition task. This surpasses the standalone results of 41.65% and 23.69% of 300 K and 77 K conditions, respectively. The findings highlight the potential to develop highly energy-efficient FeFET-based neuromorphic computing with varying temperature systems.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"582-586"},"PeriodicalIF":2.0,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11067954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144671149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-01DOI: 10.1109/JEDS.2025.3584809
Neng-Da Li;Yueh-Chin Lin;Kai-Wen Chen;Heng-Tung Hsu;Yi-Fan Tsao;Edward Yi Chang
In this study, AlGaN/GaN high-electron-mobility-transistor (HEMTs) with a small gate length were fabricated using a stepper. Additionally, a novel gate fabrication process was conducted to shrink the gate head, thus reducing the parasitic capacitance of the device to achieve high-power amplifier performance. The device performance in the research demonstrated a steady-state current density (Idss) of 975 mA/mm and a maximum transconductance (gm) of 369 mS/mm at a 20 V bias. Moreover, the cut-off frequency (fT) reached 50.6 GHz, and the maximum oscillation frequency (fmax) achieved 161 GHz as measured by S-parameter measurement. In the load-pull system, the frequency operation is under 28 GHz. For the $2times 50~mu $ m device at a drain bias of 20 V, it exhibits a maximum output power density (Pout) of 2.83 W/mm with a maximum 24.97% power-added efficiency (PAE). Additionally, for the $8times 50~mu $ m device at a drain bias of 32V, it achieves a $mathrm { P_{out}}$ of 1.27 W (3.18 W/mm). This work demonstrates that the novel gate fabrication process of shrinking gate head by using $mathrm { SiN_{x}}$ shield achieves high-frequency and high-output power characteristics for Ka-band application.
{"title":"Novel Gate Fabrication Process Enhancing High-Frequency Operation in AlGaN/GaN HEMTs for Ka-Band Applications","authors":"Neng-Da Li;Yueh-Chin Lin;Kai-Wen Chen;Heng-Tung Hsu;Yi-Fan Tsao;Edward Yi Chang","doi":"10.1109/JEDS.2025.3584809","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3584809","url":null,"abstract":"In this study, AlGaN/GaN high-electron-mobility-transistor (HEMTs) with a small gate length were fabricated using a stepper. Additionally, a novel gate fabrication process was conducted to shrink the gate head, thus reducing the parasitic capacitance of the device to achieve high-power amplifier performance. The device performance in the research demonstrated a steady-state current density (Idss) of 975 mA/mm and a maximum transconductance (gm) of 369 mS/mm at a 20 V bias. Moreover, the cut-off frequency (fT) reached 50.6 GHz, and the maximum oscillation frequency (fmax) achieved 161 GHz as measured by S-parameter measurement. In the load-pull system, the frequency operation is under 28 GHz. For the <inline-formula> <tex-math>$2times 50~mu $ </tex-math></inline-formula>m device at a drain bias of 20 V, it exhibits a maximum output power density (Pout) of 2.83 W/mm with a maximum 24.97% power-added efficiency (PAE). Additionally, for the <inline-formula> <tex-math>$8times 50~mu $ </tex-math></inline-formula>m device at a drain bias of 32V, it achieves a <inline-formula> <tex-math>$mathrm { P_{out}}$ </tex-math></inline-formula> of 1.27 W (3.18 W/mm). This work demonstrates that the novel gate fabrication process of shrinking gate head by using <inline-formula> <tex-math>$mathrm { SiN_{x}}$ </tex-math></inline-formula> shield achieves high-frequency and high-output power characteristics for Ka-band application.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"593-598"},"PeriodicalIF":2.4,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11062583","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Avalanche photodiodes (APDs) based on InGaAs/InP are pivotal for applications in low-light detection, yet their performance is often hindered by edge breakdown and high dark currents. This study systematically optimizes guard ring structures to address these challenges, focusing on attached guard rings (AGRs) and floating guard rings (FGRs) through a synergistic approach combining simulation-guided design, fabrication, and experimental validation. We analyze the impact of Zn diffusion depth, AGR/FGR geometries, and electric field distribution on device performance. Experimental results demonstrate that optimized AGR structures reduce dark currents by 70% and enhance quantum efficiency (QE) by 43%, while FGR structures achieve an order-of-magnitude reduction in dark current and a 90% QE improvement compared to non-guarded devices. The breakdown voltage increases by 2.5 V (AGR) and 4 V (FGR), leading to enhanced gain. These advancements highlight the critical role of guard ring optimization in effectively mitigating edge breakdown, offering a pathway to high-sensitivity InGaAs/InP APDs for photon detection technologies.
基于InGaAs/InP的雪崩光电二极管（apd）在低光检测应用中至关重要，但其性能经常受到边缘击穿和高暗电流的阻碍。本研究系统地优化了保护环结构以应对这些挑战，重点研究了附着保护环（agr）和浮动保护环（fgr），通过结合仿真指导设计、制造和实验验证的协同方法。我们分析了锌扩散深度、AGR/FGR几何形状和电场分布对器件性能的影响。实验结果表明，优化后的AGR结构减少了70%的暗电流，提高了43%的量子效率（QE），而FGR结构与非保护器件相比，暗电流减少了一个数量级，量子效率提高了90%。击穿电压增加2.5 V （AGR）和4 V (FGR)，导致增益增强。这些进展突出了保护环优化在有效减轻边缘击穿方面的关键作用，为光子探测技术的高灵敏度InGaAs/InP apd提供了一条途径。
{"title":"Optimization of Guard Ring Structures for Superior Dark Current Reduction and Improved Quantum Efficiency in InGaAs/InP APDs","authors":"Zefang Xu;Yu Chang;Kai Qiao;Liyu Liu;Linmeng Xu;Mengyan Fang;Chang Su;Fei Yin;Jieying Wang;Tianye Liu;Ming Li;Dian Wang;Lizhi Sheng;Xing Wang","doi":"10.1109/JEDS.2025.3583669","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3583669","url":null,"abstract":"Avalanche photodiodes (APDs) based on InGaAs/InP are pivotal for applications in low-light detection, yet their performance is often hindered by edge breakdown and high dark currents. This study systematically optimizes guard ring structures to address these challenges, focusing on attached guard rings (AGRs) and floating guard rings (FGRs) through a synergistic approach combining simulation-guided design, fabrication, and experimental validation. We analyze the impact of Zn diffusion depth, AGR/FGR geometries, and electric field distribution on device performance. Experimental results demonstrate that optimized AGR structures reduce dark currents by 70% and enhance quantum efficiency (QE) by 43%, while FGR structures achieve an order-of-magnitude reduction in dark current and a 90% QE improvement compared to non-guarded devices. The breakdown voltage increases by 2.5 V (AGR) and 4 V (FGR), leading to enhanced gain. These advancements highlight the critical role of guard ring optimization in effectively mitigating edge breakdown, offering a pathway to high-sensitivity InGaAs/InP APDs for photon detection technologies.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"551-557"},"PeriodicalIF":2.0,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11053970","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144598038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-27DOI: 10.1109/JEDS.2025.3583931
Hyeon-Seo Do;Ik-Jyae Kim;Jiwoung Choi;Jang-Sik Lee
This study investigates the role of positively charged oxygen vacancies in the central region of ferroelectric capacitors and their impact on fatigue. It has been found that, during fatigue, positively charged oxygen vacancies accumulate in the central region, leading to significant degradation in device performance. The application of a high-voltage recovery pulse effectively reverses the charge state of these vacancies from positive to neutral and redistributes them uniformly across the device, restoring its performance. This recovery process is analogous to the ‘wake-up’ state of the device, demonstrating its potential to restore electrical performance. The results of this study emphasize the importance of controlling the charge state and distribution of oxygen vacancies in the central region to enhance the durability and functionality of ferroelectric devices. This work provides a pathway for the broader and more effective application of ferroelectric materials in advanced semiconductor devices.
{"title":"Unraveling the Origins of Fatigue in Hafnia Ferroelectric Capacitors","authors":"Hyeon-Seo Do;Ik-Jyae Kim;Jiwoung Choi;Jang-Sik Lee","doi":"10.1109/JEDS.2025.3583931","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3583931","url":null,"abstract":"This study investigates the role of positively charged oxygen vacancies in the central region of ferroelectric capacitors and their impact on fatigue. It has been found that, during fatigue, positively charged oxygen vacancies accumulate in the central region, leading to significant degradation in device performance. The application of a high-voltage recovery pulse effectively reverses the charge state of these vacancies from positive to neutral and redistributes them uniformly across the device, restoring its performance. This recovery process is analogous to the ‘wake-up’ state of the device, demonstrating its potential to restore electrical performance. The results of this study emphasize the importance of controlling the charge state and distribution of oxygen vacancies in the central region to enhance the durability and functionality of ferroelectric devices. This work provides a pathway for the broader and more effective application of ferroelectric materials in advanced semiconductor devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"566-569"},"PeriodicalIF":2.0,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11053969","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144597652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article compares p-GaN-gate all-GaN cascode devices with standalone E-mode HEMTs on SiC substrates, with a focus on double pulse testing (DPT), a critical method for evaluating switching performance under realistic operating conditions. The all-GaN cascode, featuring a gate width of 85 mm, demonstrates a current rating of 15.6 A, an on-resistance of 7.7 m$Omega $ -cm2, a breakdown voltage of 970 V, and turn-on/off times of 71/52 ns, respectively. Additionally, it exhibits switching energy losses of 17/$8.2~mu $ J at $V_{DS} ,, {=} ,, 400$ V and $I_{DS} ,, {=} ,, 1$ A. Its dynamic RDS,on is measured at $0.7~Omega $ at $V_{DS} ,, {=} ,, 300$ V and $I_{DS} ,, {=} ,, 1$ A. The experimental results indicate a significant improvement compared to the standalone E-mode HEMT. This highlights the advantages of the all-GaN cascode in reducing dynamic resistance and enhancing switching efficiency, making it an excellent choice for high-performance applications.
{"title":"Evaluation of p-GaN-gate All-GaN Cascode HEMT on SiC Substrate: DC Characteristics and Switching Performance","authors":"Dian-Ying Wu;Chih-Yung Hsieh;Yi-Xian Huang;Yu-Chen Liu;Wen-Ching Hsu;Ci-Ze Li;Jia-Zhe Liu;Cheng-Yeu Wu;Meng-Chyi Wu","doi":"10.1109/JEDS.2025.3582342","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3582342","url":null,"abstract":"This article compares p-GaN-gate all-GaN cascode devices with standalone E-mode HEMTs on SiC substrates, with a focus on double pulse testing (DPT), a critical method for evaluating switching performance under realistic operating conditions. The all-GaN cascode, featuring a gate width of 85 mm, demonstrates a current rating of 15.6 A, an on-resistance of 7.7 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>-cm2, a breakdown voltage of 970 V, and turn-on/off times of 71/52 ns, respectively. Additionally, it exhibits switching energy losses of 17/<inline-formula> <tex-math>$8.2~mu $ </tex-math></inline-formula>J at <inline-formula> <tex-math>$V_{DS} ,, {=} ,, 400$ </tex-math></inline-formula> V and <inline-formula> <tex-math>$I_{DS} ,, {=} ,, 1$ </tex-math></inline-formula> A. Its dynamic RDS,on is measured at <inline-formula> <tex-math>$0.7~Omega $ </tex-math></inline-formula> at <inline-formula> <tex-math>$V_{DS} ,, {=} ,, 300$ </tex-math></inline-formula> V and <inline-formula> <tex-math>$I_{DS} ,, {=} ,, 1$ </tex-math></inline-formula> A. The experimental results indicate a significant improvement compared to the standalone E-mode HEMT. This highlights the advantages of the all-GaN cascode in reducing dynamic resistance and enhancing switching efficiency, making it an excellent choice for high-performance applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"642-648"},"PeriodicalIF":2.4,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11049654","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The potential of electrical tunability in a 3-gated (3G) Reconfigurable Field Effect Transistor (RFET) for analog/RF applications is investigated through four distinct configurations (R${}_{text {2-IG-LVT}}$ , R${}_{text {1-IG-Ambi}}$ , R${}_{text {3-IG-LVT}}$ , and R${}_{text {2-IG-HVT}}$ ). The electrical connections through two program gates (PG) and one control gate (CG) in 3G-RFET supports the implementation of configurations suitable for low-VTH (R${}_{text {2-IG-LVT}}$ and R${}_{text {3-IG-LVT}}$ ) and high-VTH (R${}_{text {2-IG-HVT}}$ ), phase follower/reversal (R${}_{text {2-IG-LVT}}$ ), frequency doubler (R${}_{text {1-IG-Ambi}}$ ), high gain (R${}_{text {3-IG-LVT}}$ ), lower parasitic capacitance (R${}_{text {2-IG-LVT}}$ and R${}_{text {3-IG-LVT}}$ ), and higher linearity (R${}_{text {3-IG-LVT}}$ ) applications. Results showcase electrical tunability as an opportunity to realize many analog/RF features–in–one nanoscale 3G-RFET.
{"title":"Electrical Tunability in 3-Gated Reconfigurable Transistor for Analog/RF Applications","authors":"Chinmayi Adoni;Sandeep Semwal;Manish Gupta;Jean-Pierre Raskin;Abhinav Kranti","doi":"10.1109/JEDS.2025.3581677","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3581677","url":null,"abstract":"The potential of electrical tunability in a 3-gated (3G) Reconfigurable Field Effect Transistor (RFET) for analog/RF applications is investigated through four distinct configurations (R<inline-formula> <tex-math>${}_{text {2-IG-LVT}}$ </tex-math></inline-formula>, R<inline-formula> <tex-math>${}_{text {1-IG-Ambi}}$ </tex-math></inline-formula>, R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>, and R<inline-formula> <tex-math>${}_{text {2-IG-HVT}}$ </tex-math></inline-formula>). The electrical connections through two program gates (PG) and one control gate (CG) in 3G-RFET supports the implementation of configurations suitable for low-VTH (R<inline-formula> <tex-math>${}_{text {2-IG-LVT}}$ </tex-math></inline-formula> and R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>) and high-VTH (R<inline-formula> <tex-math>${}_{text {2-IG-HVT}}$ </tex-math></inline-formula>), phase follower/reversal (R<inline-formula> <tex-math>${}_{text {2-IG-LVT}}$ </tex-math></inline-formula>), frequency doubler (R<inline-formula> <tex-math>${}_{text {1-IG-Ambi}}$ </tex-math></inline-formula>), high gain (R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>), lower parasitic capacitance (R<inline-formula> <tex-math>${}_{text {2-IG-LVT}}$ </tex-math></inline-formula> and R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>), and higher linearity (R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>) applications. Results showcase electrical tunability as an opportunity to realize many analog/RF features–in–one nanoscale 3G-RFET.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"558-565"},"PeriodicalIF":2.0,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11045726","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144598037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-11DOI: 10.1109/JEDS.2025.3577260
Ran Zhou;D. J. Gravesteijn;R. J. E. Hueting
In this work, we investigate the field and temperature dependence of the electron mobility in aluminum-gallium-nitride/gallium-nitride (AlGaN/GaN) high electron mobility transistors (HEMTs) realized on GaN-on-silicon (Si) substrates. For this purpose we employ an extraction method to eliminate parasitic and fringing effects. Our results show that especially at low fields the temperature dependence of the mobility, and consequently that of the specific on-resistance, is strongly affected by stress-induced charged dislocation scattering. For explaining the mobility behaviour at low fields, the subthreshold operation regime of the HEMTs has also been analyzed. An interface trap density at the AlGaN/GaN interface $(N_{textrm {it}})$ of $sim ~6.9times 10^{10}$ cm−2 has been extracted independent of the temperature which is close to the extracted dislocation density from mobility measurements. This suggests that the relatively high dislocation density in the GaN layer, which is a consequence of the still imperfect buffer layer in the GaN-on-Si substrate that is used to accommodate the strain difference, has an impact on $N_{textrm {it}}$ , thus subthreshold swing, in addition to the mobility reduction.
{"title":"Impact of Defects on the Low-Field Electron Mobility in GaN-on-Si HEMTs","authors":"Ran Zhou;D. J. Gravesteijn;R. J. E. Hueting","doi":"10.1109/JEDS.2025.3577260","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3577260","url":null,"abstract":"In this work, we investigate the field and temperature dependence of the electron mobility in aluminum-gallium-nitride/gallium-nitride (AlGaN/GaN) high electron mobility transistors (HEMTs) realized on GaN-on-silicon (Si) substrates. For this purpose we employ an extraction method to eliminate parasitic and fringing effects. Our results show that especially at low fields the temperature dependence of the mobility, and consequently that of the specific on-resistance, is strongly affected by stress-induced charged dislocation scattering. For explaining the mobility behaviour at low fields, the subthreshold operation regime of the HEMTs has also been analyzed. An interface trap density at the AlGaN/GaN interface <inline-formula> <tex-math>$(N_{textrm {it}})$ </tex-math></inline-formula> of <inline-formula> <tex-math>$sim ~6.9times 10^{10}$ </tex-math></inline-formula> cm−2 has been extracted independent of the temperature which is close to the extracted dislocation density from mobility measurements. This suggests that the relatively high dislocation density in the GaN layer, which is a consequence of the still imperfect buffer layer in the GaN-on-Si substrate that is used to accommodate the strain difference, has an impact on <inline-formula> <tex-math>$N_{textrm {it}}$ </tex-math></inline-formula>, thus subthreshold swing, in addition to the mobility reduction.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"516-523"},"PeriodicalIF":2.0,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11031174","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144472684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-11DOI: 10.1109/JEDS.2025.3578547
Ya-Hsiang Tai;Chih-Chung Tu;Chi-Hao Lin;Chi-Fan Lu
In large-area image sensing applications, such as under-display fingerprint sensors, amorphous silicon (a-Si) gap-type thin-film transistors (TFTs) are favored due to their simple fabrication process and high sensing current. These applications typically involve device operation under low-light illumination conditions. Despite these advantages, the recovery behavior of performance parameters after exposure to stress factors, including bias stress and photo-stress, has not been comprehensively explored, particularly in relation to reliability recovery. This study systematically investigates the impact of fixed-bias and pulsed-stress operations under low-light conditions. The experimental findings are further analyzed using Technology Computer-Aided Design (TCAD) simulations to elucidate the underlying mechanisms. Results indicate that long-term bias stress induces significant variations in the photocurrent characteristics of the devices. However, the introduction of pulsed operations in sensing applications markedly enhances the operational lifetime of the devices, offering a promising pathway to improving their reliability.
{"title":"Reliability of Gap-Type Thin Film Transistors Under Low Illumination for Imaging Sensing Applications","authors":"Ya-Hsiang Tai;Chih-Chung Tu;Chi-Hao Lin;Chi-Fan Lu","doi":"10.1109/JEDS.2025.3578547","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3578547","url":null,"abstract":"In large-area image sensing applications, such as under-display fingerprint sensors, amorphous silicon (a-Si) gap-type thin-film transistors (TFTs) are favored due to their simple fabrication process and high sensing current. These applications typically involve device operation under low-light illumination conditions. Despite these advantages, the recovery behavior of performance parameters after exposure to stress factors, including bias stress and photo-stress, has not been comprehensively explored, particularly in relation to reliability recovery. This study systematically investigates the impact of fixed-bias and pulsed-stress operations under low-light conditions. The experimental findings are further analyzed using Technology Computer-Aided Design (TCAD) simulations to elucidate the underlying mechanisms. Results indicate that long-term bias stress induces significant variations in the photocurrent characteristics of the devices. However, the introduction of pulsed operations in sensing applications markedly enhances the operational lifetime of the devices, offering a promising pathway to improving their reliability.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"524-531"},"PeriodicalIF":2.0,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11030751","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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