We prototyped a true analog current computing multilayer neural network (NN) chip, where multiple analog in-memory computing (AiMC) circuit blocks are connected to each other via simple analog non-linear operation circuits. The true analog current computing is achieved with the invention of an analog current rectified linear unit (ReLU) circuit of a three-stage current mirror. With the prototyped NN chip, we demonstrated that the true analog computing (1) achieves process variation compensation utilizing current driving, (2) eliminates digital-analog or analog-digital data conversion between NNs, and (3) realizes low power inference, not only in multiply-accumulate (MAC) but in ReLU operation. Through classification of Mixed National Institute of Standards and Technology dataset, the chip exhibits a low energy of 1.1 nJ/classification and an accuracy of 91.6%, achieves weight retention of five hours, much longer than dynamic random access memory, and enables 68% power reduction compared with serially connected two single-layer NN chips with analog-digital converters and digital-analog converters in between. Although periodic refresh from an external storage class memory is necessary for applications that require continuous operation exceeding five hours, our AiMC capable of MAC and non-linear operations with low power is effective in applications such as edge artificial intelligence terminals with limited power sources.
我们制作了真正的模拟电流计算多层神经网络（NN）芯片原型，其中多个模拟内存计算（AiMC）电路块通过简单的模拟非线性运算电路相互连接。三级电流镜的模拟电流整流线性单元（ReLU）电路的发明实现了真正的模拟电流计算。通过原型 NN 芯片，我们证明了真正的模拟计算：(1) 利用电流驱动实现了工艺变化补偿；(2) 消除了 NN 之间的数模或模数数据转换；(3) 实现了低功耗推理，不仅在乘法累加（MAC）中如此，在 ReLU 运算中也是如此。通过对美国国家标准与技术研究院的混合数据集进行分类，该芯片实现了 1.1 nJ/分类的低能耗和 91.6% 的准确率，重量保持时间长达 5 小时，远远超过动态随机存取存储器，与串行连接的两个单层 NN 芯片（中间带有模拟数字转换器和数字模拟转换器）相比，功耗降低了 68%。虽然对于需要连续工作超过五小时的应用来说，从外部存储类存储器定期刷新是必要的，但我们的 AiMC 能够以低功耗进行 MAC 和非线性操作，在诸如电源有限的边缘人工智能终端等应用中非常有效。
{"title":"A 1.1-nJ/Classification True Analog Current Computing on Multilayer Neural Network With Crystalline-IGZO/Si-CMOS Monolithic Stack Technology","authors":"Kazuki Tsuda;Kazuma Furutani;Yuto Yakubo;Hiromichi Godo;Yoshinori Ando;Atsutake Kosuge;Toru Nakura;Shunpei Yamazaki","doi":"10.1109/JEDS.2024.3439712","DOIUrl":"10.1109/JEDS.2024.3439712","url":null,"abstract":"We prototyped a true analog current computing multilayer neural network (NN) chip, where multiple analog in-memory computing (AiMC) circuit blocks are connected to each other via simple analog non-linear operation circuits. The true analog current computing is achieved with the invention of an analog current rectified linear unit (ReLU) circuit of a three-stage current mirror. With the prototyped NN chip, we demonstrated that the true analog computing (1) achieves process variation compensation utilizing current driving, (2) eliminates digital-analog or analog-digital data conversion between NNs, and (3) realizes low power inference, not only in multiply-accumulate (MAC) but in ReLU operation. Through classification of Mixed National Institute of Standards and Technology dataset, the chip exhibits a low energy of 1.1 nJ/classification and an accuracy of 91.6%, achieves weight retention of five hours, much longer than dynamic random access memory, and enables 68% power reduction compared with serially connected two single-layer NN chips with analog-digital converters and digital-analog converters in between. Although periodic refresh from an external storage class memory is necessary for applications that require continuous operation exceeding five hours, our AiMC capable of MAC and non-linear operations with low power is effective in applications such as edge artificial intelligence terminals with limited power sources.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"594-604"},"PeriodicalIF":2.0,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10628044","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-06DOI: 10.1109/JEDS.2024.3438886
Tomoya Sanuki;Hideto Horii;Takashi Maeda
In this work, we report the fast-read storage performance of thyristor operation in 3D flash memory. By forming a pseudo N+/P/N/P+ structure with the word line (WL) bias of 3D string cells, thyristor operation with steep switching characteristics and a high on-current can be obtained. It is known that there is a strong cell-to-cell interference effect in thyristor operation, and in previous report (Horii et al., 2020), we have suggested novel WL bias conditions, referred to as the wide barrier mode, that can suppress the cell-to-cell interference effect. In order to evaluate the advantages of thyristor operation in 3D flash memory further, we report for the first time the several cell characteristics and reliability issues of thyristor operation required for the actual usage of storage products. (1) We demonstrate excellent cell characteristics of a wide programmed Vth window and sufficient program slope values in thyristor operation, which are indispensable for realizing multi-level cells. (2) Cell characteristics of thyristor operation exhibit hysteresis when sweeping in the WL direction but not in the bit line (BL) direction, which is essential for determining the read operating waveform. (3) Our proposed new WL biasing scheme to suppress the cell-to-cell interference effect is described with a more detailed dependence on adjacent cells and its effect on the on-current. We show that a high on-current can still be achieved even with highly stacked WL of approximately 100 layers. (4) In terms of reliability issues, thyristor operation exhibits a sufficient margin against read cycle stress with minimal change in the cell Vth even after 2 million read cycles. Thyristor operation can be applied to storage products even in read-intensive applications. (5) We also describe storage performance, including read latency and bandwidth, for SLC and QLC mode in memory arrays with highly stacked WL of approximately 100 layers. Thyristor operation of 3D flash memory is a strong candidate for future high-speed storage products, as it can significantly improve read latency and program throughput.
{"title":"Fast-Read Storage Performance by Thyristor Operation in 3-D Flash Memory","authors":"Tomoya Sanuki;Hideto Horii;Takashi Maeda","doi":"10.1109/JEDS.2024.3438886","DOIUrl":"10.1109/JEDS.2024.3438886","url":null,"abstract":"In this work, we report the fast-read storage performance of thyristor operation in 3D flash memory. By forming a pseudo N+/P/N/P+ structure with the word line (WL) bias of 3D string cells, thyristor operation with steep switching characteristics and a high on-current can be obtained. It is known that there is a strong cell-to-cell interference effect in thyristor operation, and in previous report (Horii et al., 2020), we have suggested novel WL bias conditions, referred to as the wide barrier mode, that can suppress the cell-to-cell interference effect. In order to evaluate the advantages of thyristor operation in 3D flash memory further, we report for the first time the several cell characteristics and reliability issues of thyristor operation required for the actual usage of storage products. (1) We demonstrate excellent cell characteristics of a wide programmed Vth window and sufficient program slope values in thyristor operation, which are indispensable for realizing multi-level cells. (2) Cell characteristics of thyristor operation exhibit hysteresis when sweeping in the WL direction but not in the bit line (BL) direction, which is essential for determining the read operating waveform. (3) Our proposed new WL biasing scheme to suppress the cell-to-cell interference effect is described with a more detailed dependence on adjacent cells and its effect on the on-current. We show that a high on-current can still be achieved even with highly stacked WL of approximately 100 layers. (4) In terms of reliability issues, thyristor operation exhibits a sufficient margin against read cycle stress with minimal change in the cell Vth even after 2 million read cycles. Thyristor operation can be applied to storage products even in read-intensive applications. (5) We also describe storage performance, including read latency and bandwidth, for SLC and QLC mode in memory arrays with highly stacked WL of approximately 100 layers. Thyristor operation of 3D flash memory is a strong candidate for future high-speed storage products, as it can significantly improve read latency and program throughput.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"710-716"},"PeriodicalIF":2.0,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10624679","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-01DOI: 10.1109/JEDS.2024.3436820
Myeongsu Chae;Ho-Young Cha;Hyungtak Kim
In this work, we investigated the instability of threshold voltage (Vth) in p-GaN/AlGaN/GaN high electron mobility transistors (HEMTs) under positive gate biases and high temperatures. We reveal an abnormal temperature dependence of threshold voltage instability, suggesting that threshold voltage instability significant differences at elevated temperatures and is primarily attributed to the trapping/detrapping of charged carriers. Notably, the positive shift in threshold voltage diminished and eventually reversed at low gate bias as the temperature increased. In contrast, the negative shift intensified with increasing temperature but began to mitigate above 100°C at high gate bias due to an enhanced de-trapping process of electrons and holes. These results suggest the presence of multiple mechanisms behind the threshold voltage instability under varying thermal conditions.
{"title":"Abnormal Temperature and Bias Dependence of Threshold Voltage Instability in p-GaN/AlGaN/GaN HEMTs","authors":"Myeongsu Chae;Ho-Young Cha;Hyungtak Kim","doi":"10.1109/JEDS.2024.3436820","DOIUrl":"10.1109/JEDS.2024.3436820","url":null,"abstract":"In this work, we investigated the instability of threshold voltage (Vth) in p-GaN/AlGaN/GaN high electron mobility transistors (HEMTs) under positive gate biases and high temperatures. We reveal an abnormal temperature dependence of threshold voltage instability, suggesting that threshold voltage instability significant differences at elevated temperatures and is primarily attributed to the trapping/detrapping of charged carriers. Notably, the positive shift in threshold voltage diminished and eventually reversed at low gate bias as the temperature increased. In contrast, the negative shift intensified with increasing temperature but began to mitigate above 100°C at high gate bias due to an enhanced de-trapping process of electrons and holes. These results suggest the presence of multiple mechanisms behind the threshold voltage instability under varying thermal conditions.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"581-586"},"PeriodicalIF":2.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10620298","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141882126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-31DOI: 10.1109/jeds.2024.3436063
Huikai Chen, Jinbin Pan, Shulong Wang, Liutao Li, Jin Huang, Shupeng Chen, Hongxia Liu
{"title":"Explicit Function Model of Electromagnetic Reliability for CMOS Inverters Under HPM Coupling Based on Physical Mechanism Analysis and Neural Network Algorithm","authors":"Huikai Chen, Jinbin Pan, Shulong Wang, Liutao Li, Jin Huang, Shupeng Chen, Hongxia Liu","doi":"10.1109/jeds.2024.3436063","DOIUrl":"https://doi.org/10.1109/jeds.2024.3436063","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"292 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We demonstrate that the shorter channel self-aligned top-gate (SA TG) coplanar indiumgallium- zinc oxide (IGZO) thin-film transistors (TFTs), with negative voltage applied to the back-gate, exhibit superior characteristics as driving transistors in organic light-emitting diode (OLED) pixels compared to their longer channel counterparts. The shorter channel IGZO TFTs (with a channel length (L) of 3 μm) biased with a back gate voltage of −3.5 V showed a larger subthreshold swing (SS = 0.21 V/dec) than the longer channel ones (with L = 5 μm, SS = 0.16 V/dec) with a similar threshold value (VTH = 0.7–0.8 V). A large SS is beneficial for controlling grayscale levels, especially at low gray levels, when IGZO TFTs are used as driving transistors in OLED pixels. Furthermore, the negatively back-gate-biased shorter channel SA TG coplanar IGZO TFTs exhibited significantly enhanced electrical stability compared to the longer channel ones under both positive gate bias and hot carrier stresses. The findings of this study are expected to be useful in expanding the utility of IGZO TFTs in OLED displays.
{"title":"Demonstration of SA TG Coplanar IGZO TFTs With Large Subthreshold Swing Using the Back-Gate Biasing Technique for AMOLED Applications","authors":"Chae-Eun Oh;Ye-Lim Han;Dong-Ho Lee;Jin-Ha Hwang;Hwan-Seok Jeong;Myeong-Ho Kim;Kyoung-Seok Son;Sunhee Lee;Sang-Hun Song;Hyuck-In Kwon","doi":"10.1109/JEDS.2024.3434613","DOIUrl":"10.1109/JEDS.2024.3434613","url":null,"abstract":"We demonstrate that the shorter channel self-aligned top-gate (SA TG) coplanar indiumgallium- zinc oxide (IGZO) thin-film transistors (TFTs), with negative voltage applied to the back-gate, exhibit superior characteristics as driving transistors in organic light-emitting diode (OLED) pixels compared to their longer channel counterparts. The shorter channel IGZO TFTs (with a channel length (L) of 3 μm) biased with a back gate voltage of −3.5 V showed a larger subthreshold swing (SS = 0.21 V/dec) than the longer channel ones (with L = 5 μm, SS = 0.16 V/dec) with a similar threshold value (VTH = 0.7–0.8 V). A large SS is beneficial for controlling grayscale levels, especially at low gray levels, when IGZO TFTs are used as driving transistors in OLED pixels. Furthermore, the negatively back-gate-biased shorter channel SA TG coplanar IGZO TFTs exhibited significantly enhanced electrical stability compared to the longer channel ones under both positive gate bias and hot carrier stresses. The findings of this study are expected to be useful in expanding the utility of IGZO TFTs in OLED displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"564-568"},"PeriodicalIF":2.0,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10612771","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The use of the plasma-enhanced atomic layer deposition (ALD) technique for the deposition of HfO2-based ferroelectrics has received attention in recent years primarily due to wake-up free operation. However, these studies have primarily focused on metal-ferroelectric-metal (MFM) structures. In this work, we investigate the characteristics of ferroelectric field-effect transistors (FEFETs) in which the ferroelectric Hf0.5Zr0.5O2 (HZO) gate stack is deposited using the plasma-enhanced atomic layer deposition (PEALD) technique. We observe that PEALD FEFET requires a higher write voltage for the same memory window compared to an equivalent FEFET with thermal ALD (THALD)-grown HZO. The increase in write voltage in PEALD FEFET occurs primarily due to the increase of the interfacial oxide layer using the plasma process. In addition, we observe that the SiO2 interfacial layer underneath the ferroelectric (FE) HZO layer eliminates the wake-up behavior in both THALD and PEALD FEFETs.
{"title":"Plasma-Enhanced Atomic Layer Deposition-Based Ferroelectric Field-Effect Transistors","authors":"Chinsung Park;Prasanna Venkat Ravindran;Dipjyoti Das;Priyankka Gundlapudi Ravikumar;Chengyang Zhang;Nashrah Afroze;Lance Fernandes;Yu Hsin Kuo;Jae Hur;Hang Chen;Mengkun Tian;Winston Chern;Shimeng Yu;Asif Islam Khan","doi":"10.1109/JEDS.2024.3434598","DOIUrl":"10.1109/JEDS.2024.3434598","url":null,"abstract":"The use of the plasma-enhanced atomic layer deposition (ALD) technique for the deposition of HfO2-based ferroelectrics has received attention in recent years primarily due to wake-up free operation. However, these studies have primarily focused on metal-ferroelectric-metal (MFM) structures. In this work, we investigate the characteristics of ferroelectric field-effect transistors (FEFETs) in which the ferroelectric Hf0.5Zr0.5O2 (HZO) gate stack is deposited using the plasma-enhanced atomic layer deposition (PEALD) technique. We observe that PEALD FEFET requires a higher write voltage for the same memory window compared to an equivalent FEFET with thermal ALD (THALD)-grown HZO. The increase in write voltage in PEALD FEFET occurs primarily due to the increase of the interfacial oxide layer using the plasma process. In addition, we observe that the SiO2 interfacial layer underneath the ferroelectric (FE) HZO layer eliminates the wake-up behavior in both THALD and PEALD FEFETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"569-572"},"PeriodicalIF":2.0,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10612817","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a high-performance and low-HCI (Hot carrier injection) degradation LDMOS (Lateral double diffused metal oxide semiconductor) device is introduced. It consists of an additional mini LOCOS (Local oxidation of silicon) field plate combined with a mini STI (Shallow trench isolation) field plate without an additional complex fabrication process. A series of devices have been fabricated, and the field plate corner profile is optimized. The proposed hybrid FP(Field plate) can effectively reduce the electric field peak, and the BV (Breakdown voltage) achieves as high as 78.9V while the ${R}_{{on}{,}{sp}}$ (Specific on-resistance) is as low as $69.1~{{mathrm { m}}Omega cdot }{mm}^{2}$ , which is 65.8% improved compared with conventional transistors. Meanwhile, the hybrid FP device owns much better HCI (Hot carrier injection) degradation performance on ${R}_{on,sp}$ , threshold voltage ${V}_{T}$ , and gate-drain capacitance ${C}_{GD}$ . The degradation of ${R}_{{on}{,}{sp}}$ is only 8.6% under ${I}_{d}$ mode stress while it is as high as 15.8% for the conventional devices. At on-state, ${C}_{GD}$ degradation is only 9.1% while it is nearly 59.9% in the traditional device. At high voltage application regions, the device exhibits nearly 0% ${C}_{GD}$ degradation while it is as high as 43.8% in the traditional device. The results indicate the device’s robustness in both DC (Direct current) applications and RF (Radio frequency) applications.
{"title":"A High-Performance and Low HCI Degradation LDMOS Device With a Hybrid Field Plate","authors":"Shaoxin Yu;Rongsheng Chen;Weiheng Shao;Weiming Yu;Xiaoyan Zhao;Zheng Chen;Weizhong Shan;Jenhao Cheng","doi":"10.1109/JEDS.2024.3433442","DOIUrl":"10.1109/JEDS.2024.3433442","url":null,"abstract":"In this paper, a high-performance and low-HCI (Hot carrier injection) degradation LDMOS (Lateral double diffused metal oxide semiconductor) device is introduced. It consists of an additional mini LOCOS (Local oxidation of silicon) field plate combined with a mini STI (Shallow trench isolation) field plate without an additional complex fabrication process. A series of devices have been fabricated, and the field plate corner profile is optimized. The proposed hybrid FP(Field plate) can effectively reduce the electric field peak, and the BV (Breakdown voltage) achieves as high as 78.9V while the \u0000<inline-formula> <tex-math>${R}_{{on}{,}{sp}}$ </tex-math></inline-formula>\u0000 (Specific on-resistance) is as low as \u0000<inline-formula> <tex-math>$69.1~{{mathrm { m}}Omega cdot }{mm}^{2}$ </tex-math></inline-formula>\u0000, which is 65.8% improved compared with conventional transistors. Meanwhile, the hybrid FP device owns much better HCI (Hot carrier injection) degradation performance on \u0000<inline-formula> <tex-math>${R}_{on,sp}$ </tex-math></inline-formula>\u0000, threshold voltage \u0000<inline-formula> <tex-math>${V}_{T}$ </tex-math></inline-formula>\u0000, and gate-drain capacitance \u0000<inline-formula> <tex-math>${C}_{GD}$ </tex-math></inline-formula>\u0000. The degradation of \u0000<inline-formula> <tex-math>${R}_{{on}{,}{sp}}$ </tex-math></inline-formula>\u0000 is only 8.6% under \u0000<inline-formula> <tex-math>${I}_{d}$ </tex-math></inline-formula>\u0000 mode stress while it is as high as 15.8% for the conventional devices. At on-state, \u0000<inline-formula> <tex-math>${C}_{GD}$ </tex-math></inline-formula>\u0000 degradation is only 9.1% while it is nearly 59.9% in the traditional device. At high voltage application regions, the device exhibits nearly 0% \u0000<inline-formula> <tex-math>${C}_{GD}$ </tex-math></inline-formula>\u0000 degradation while it is as high as 43.8% in the traditional device. The results indicate the device’s robustness in both DC (Direct current) applications and RF (Radio frequency) applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"605-612"},"PeriodicalIF":2.0,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10609835","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-24DOI: 10.1109/JEDS.2024.3432971
Andreas Fuchsberger;Lukas Wind;Daniele Nazzari;Alexandra Dobler;Johannes Aberl;Enrique Prado Navarrete;Moritz Brehm;Lilian Vogl;Peter Schweizer;Sebastian Lellig;Xavier Maeder;Masiar Sistani;Walter M. Weber
A promising approach to advance electronics beyond static operations is to enhance state-ofthe- art systems by the functional diversification of transistors. Here, we experimentally demonstrate that an ultra-thin Ge channel implemented on a Si on insulator platform enables run-time switchable symmetric pand n-type field-effect transistor operability as well as the prominent feature of distinct room-temperature negative differential resistance. Temperature dependent bias spectroscopy is utilized to map electronic transport in these so called negative differential resistance mode reconfigurable transistors. Thereof, a profound understanding of the involved transport physics and electrostatic gating mechanisms is obtained and evaluated. Further, we show that a multi-gate negative differential resistance reconfigurable transistor can effectively replace a cascode of negative differential resistance devices, contributing to a smaller area footprint, and reduced latency of critical paths. Notably, the experimentally obtained multi-heterojunction transistors constitute the first chip-scale platform that combines efficient polarity control as well as sizeand energy-efficient room-temperature negative differential resistance, providing an inherent component of emerging neuromorphic computing.
通过晶体管的功能多样化来增强最先进的系统，是推动电子技术超越静态操作的一种可行方法。在这里，我们通过实验证明，在绝缘体上的硅平台上实现的超薄 Ge 沟道可以实现运行时可切换的对称 pand n 型场效应晶体管的可操作性，以及明显的室温负差分电阻的突出特点。利用随温度变化的偏压光谱绘制了这些所谓负差分电阻模式可重构晶体管中的电子传输图。由此，我们获得并评估了对相关传输物理学和静电门控机制的深刻理解。此外，我们还表明，多栅极负差分电阻可重构晶体管可以有效取代负差分电阻器件级联，从而缩小面积占用，并降低关键路径的延迟。值得注意的是，实验中获得的多异质结晶体管构成了第一个芯片级平台，它结合了高效极性控制以及尺寸和能效的室温负差分电阻，为新兴的神经形态计算提供了一个固有的组件。
{"title":"A Reconfigurable Ge Transistor Functionally Diversified by Negative Differential Resistance","authors":"Andreas Fuchsberger;Lukas Wind;Daniele Nazzari;Alexandra Dobler;Johannes Aberl;Enrique Prado Navarrete;Moritz Brehm;Lilian Vogl;Peter Schweizer;Sebastian Lellig;Xavier Maeder;Masiar Sistani;Walter M. Weber","doi":"10.1109/JEDS.2024.3432971","DOIUrl":"10.1109/JEDS.2024.3432971","url":null,"abstract":"A promising approach to advance electronics beyond static operations is to enhance state-ofthe- art systems by the functional diversification of transistors. Here, we experimentally demonstrate that an ultra-thin Ge channel implemented on a Si on insulator platform enables run-time switchable symmetric pand n-type field-effect transistor operability as well as the prominent feature of distinct room-temperature negative differential resistance. Temperature dependent bias spectroscopy is utilized to map electronic transport in these so called negative differential resistance mode reconfigurable transistors. Thereof, a profound understanding of the involved transport physics and electrostatic gating mechanisms is obtained and evaluated. Further, we show that a multi-gate negative differential resistance reconfigurable transistor can effectively replace a cascode of negative differential resistance devices, contributing to a smaller area footprint, and reduced latency of critical paths. Notably, the experimentally obtained multi-heterojunction transistors constitute the first chip-scale platform that combines efficient polarity control as well as sizeand energy-efficient room-temperature negative differential resistance, providing an inherent component of emerging neuromorphic computing.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"541-547"},"PeriodicalIF":2.0,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10608155","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-22DOI: 10.1109/JEDS.2024.3432783
Shaocheng Li;Shu Yang;Zhao Han;Weibing Hao;Kuang Sheng;Guangwei Xu;Shibing Long
Abstract Selective-area p-type doping has been regarded as one of the primary challenges in vertical GaN junction-based power devices. Nickel oxide (NiO), serving as a natural p-type semiconductor without the requirement for sophisticated activation and enabling adjustable charge concentration, is potentially feasible to form pn hetero-junction in GaN power devices. In this work, a vertical GaN Schottky barrier diode (SBD) featuring hybrid p-NiO junction termination extension (HP-JTE) with fluorine (F)-implanted buried layer (FIBL) has been demonstrated. With FIBL incorporated underneath p-NiO in the termination region, the reverse leakage current can be effectively reduced by approximately 3 orders of magnitude. By virtue of photon emission microscopy measurements, it has also been verified that the light emission and leakage current through p-NiO termination region can be effectively suppressed by FIBL. Thanks to the HP-JTE structure as well as the nearly ideal Schottky interface, the vertical GaN SBD exhibits a high current swing of $sim 10^{13}$ , a low ideality factor of $sim 1.02$ , a low differential $R_{O N}$ of $sim 0.89 mathrm{~m} Omega cdot mathrm{cm}^2$ , a low forward voltage drop of $sim 0.8 mathrm{~V}$ (defined at $100 mathrm{~A} / mathrm{cm}^2$ ), and a breakdown voltage of $sim 780 mathrm{~V}$ (defined at $0.1 mathrm{~A} / mathrm{cm}^2$ ). The characterizations and findings in this work can provide valuable insights into the p-NiO/GaN hetero-junction-based power devices.
{"title":"Vertical GaN Schottky Barrier Diode With Hybrid P-NiO Junction Termination Extension","authors":"Shaocheng Li;Shu Yang;Zhao Han;Weibing Hao;Kuang Sheng;Guangwei Xu;Shibing Long","doi":"10.1109/JEDS.2024.3432783","DOIUrl":"10.1109/JEDS.2024.3432783","url":null,"abstract":"Abstract Selective-area p-type doping has been regarded as one of the primary challenges in vertical GaN junction-based power devices. Nickel oxide (NiO), serving as a natural p-type semiconductor without the requirement for sophisticated activation and enabling adjustable charge concentration, is potentially feasible to form pn hetero-junction in GaN power devices. In this work, a vertical GaN Schottky barrier diode (SBD) featuring hybrid p-NiO junction termination extension (HP-JTE) with fluorine (F)-implanted buried layer (FIBL) has been demonstrated. With FIBL incorporated underneath p-NiO in the termination region, the reverse leakage current can be effectively reduced by approximately 3 orders of magnitude. By virtue of photon emission microscopy measurements, it has also been verified that the light emission and leakage current through p-NiO termination region can be effectively suppressed by FIBL. Thanks to the HP-JTE structure as well as the nearly ideal Schottky interface, the vertical GaN SBD exhibits a high current swing of \u0000<inline-formula> <tex-math>$sim 10^{13}$ </tex-math></inline-formula>\u0000, a low ideality factor of \u0000<inline-formula> <tex-math>$sim 1.02$ </tex-math></inline-formula>\u0000, a low differential \u0000<inline-formula> <tex-math>$R_{O N}$ </tex-math></inline-formula>\u0000 of \u0000<inline-formula> <tex-math>$sim 0.89 mathrm{~m} Omega cdot mathrm{cm}^2$ </tex-math></inline-formula>\u0000, a low forward voltage drop of \u0000<inline-formula> <tex-math>$sim 0.8 mathrm{~V}$ </tex-math></inline-formula>\u0000 (defined at \u0000<inline-formula> <tex-math>$100 mathrm{~A} / mathrm{cm}^2$ </tex-math></inline-formula>\u0000), and a breakdown voltage of \u0000<inline-formula> <tex-math>$sim 780 mathrm{~V}$ </tex-math></inline-formula>\u0000 (defined at \u0000<inline-formula> <tex-math>$0.1 mathrm{~A} / mathrm{cm}^2$ </tex-math></inline-formula>\u0000). The characterizations and findings in this work can provide valuable insights into the p-NiO/GaN hetero-junction-based power devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"548-554"},"PeriodicalIF":2.0,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10606442","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141786314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with the literature and the foundry models, the cryogenic behavior diverges in many aspects. These deviations include changes with respect to RT in magnitude and bias dependence that are conditional on transistor type and geometry, and even an additional systematic Lorentzian feature that is common among individual devices. Furthermore, we find the scaling of the average LFN with the area and its variability to be similar between RT and 4.2K, with the cryogenic scaling reported systematically for the first time. The findings suggest that, as no consistent decrease of LFN at lower temperatures is observed while the white noise is reduced, the impact of LFN for precision analog design at cryogenic temperatures gains a more predominant role.
{"title":"Cryogenic Characterization of Low-Frequency Noise in 40-nm CMOS","authors":"Gerd Kiene;Sadık İlik;Luigi Mastrodomenico;Masoud Babaie;Fabio Sebastiano","doi":"10.1109/JEDS.2024.3432283","DOIUrl":"10.1109/JEDS.2024.3432283","url":null,"abstract":"This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with the literature and the foundry models, the cryogenic behavior diverges in many aspects. These deviations include changes with respect to RT in magnitude and bias dependence that are conditional on transistor type and geometry, and even an additional systematic Lorentzian feature that is common among individual devices. Furthermore, we find the scaling of the average LFN with the area and its variability to be similar between RT and 4.2K, with the cryogenic scaling reported systematically for the first time. The findings suggest that, as no consistent decrease of LFN at lower temperatures is observed while the white noise is reduced, the impact of LFN for precision analog design at cryogenic temperatures gains a more predominant role.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"573-580"},"PeriodicalIF":2.0,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10606256","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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