This work demonstrates high-performance vertical NiO/Ga2O3 heterojunction diodes (HJDs) with a 2-step space-modulated junction termination extension. Distinct from the current state-of-the-art Ga2O3 HJDs, we achieve breakdown voltage exceeding 3 kV with a low turn on voltage (VON) of 0.8V, estimated at a forward current density (IF) of 1 $A-cm^{text {-2}}$ . The measured devices exhibit excellent turn-on characteristics achieving 100 $A-cm^{text {-2}}$ current density at a forward bias of 1.5V along with a low differential specific on-resistance (Ron,sp) of 4.4 m$Omega $ -cm2. The SM-JTE was realized using concentric NiO rings with varying widths and spacing that approximates a gradual reduction in JTE charge. The unipolar figure of merit (FOM) calculated exceeds 2 GW-cm2 and is among the best reported for devices with a sub-1V turn-on. The fabricated devices also displayed minimal change in forward I-V characteristics post reverse bias stress of 3 kV applied during breakdown voltage testing.
这项工作展示了高性能的垂直NiO/Ga2O3异质结二极管（HJDs），具有两步空间调制结终端扩展。与目前最先进的Ga2O3 HJDs不同，我们以0.8V的低导通电压（VON）实现了超过3kv的击穿电压，估计正向电流密度（IF）为1 $ a -cm^{text{-2}}$。所测器件具有优异的导通特性，在正向偏置1.5V下实现100 $ a -cm^{text{-2}}$电流密度，并具有4.4 m $Omega $ -cm2的低差分比导通电阻（Ron,sp）。SM-JTE采用不同宽度和间距的同心NiO环来实现，近似于逐渐减少JTE电荷。计算出的单极性能值（FOM）超过2 GW-cm2，是具有sub-1V导通的器件的最佳报告之一。在击穿电压测试中施加3kv反向偏置应力后，制备的器件也显示出最小的正向I-V特性变化。
{"title":">3kV NiO/Ga2O3 Heterojunction Diodes With Space-Modulated Junction Termination Extension and Sub-1V Turn-On","authors":"Advait Gilankar;Abishek Katta;Nabasindhu Das;Nidhin Kurian Kalarickal","doi":"10.1109/JEDS.2025.3562028","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562028","url":null,"abstract":"This work demonstrates high-performance vertical NiO/Ga2O3 heterojunction diodes (HJDs) with a 2-step space-modulated junction termination extension. Distinct from the current state-of-the-art Ga2O3 HJDs, we achieve breakdown voltage exceeding 3 kV with a low turn on voltage (VON) of 0.8V, estimated at a forward current density (IF) of 1 <inline-formula> <tex-math>$A-cm^{text {-2}}$ </tex-math></inline-formula>. The measured devices exhibit excellent turn-on characteristics achieving 100 <inline-formula> <tex-math>$A-cm^{text {-2}}$ </tex-math></inline-formula> current density at a forward bias of 1.5V along with a low differential specific on-resistance (Ron,sp) of 4.4 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>-cm2. The SM-JTE was realized using concentric NiO rings with varying widths and spacing that approximates a gradual reduction in JTE charge. The unipolar figure of merit (FOM) calculated exceeds 2 GW-cm2 and is among the best reported for devices with a sub-1V turn-on. The fabricated devices also displayed minimal change in forward I-V characteristics post reverse bias stress of 3 kV applied during breakdown voltage testing.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"373-377"},"PeriodicalIF":2.0,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10967383","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-10DOI: 10.1109/JEDS.2025.3558645
{"title":"Call for Nominations for Editor-in-Chief IEEE Electron Device Letters","authors":"","doi":"10.1109/JEDS.2025.3558645","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3558645","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1076-1076"},"PeriodicalIF":2.0,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10960702","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143817907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-10DOI: 10.1109/JEDS.2025.3558646
{"title":"Call for Nominations for Editor-in-Chief IEEE Transactions on Electron Devices(TED)","authors":"","doi":"10.1109/JEDS.2025.3558646","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3558646","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1077-1077"},"PeriodicalIF":2.0,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10960700","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143817942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ferroelectric (Fe) FET has emerged as a promising candidate for efficient in-memory computing due to its properties, such as non-volatility and low power. However, scaled 3D devices such as Fe-FinFET suffer from significant self-heating effects (SHE) and process variations. These issues cause inconsistent performance and reduce reliability, limiting their applicability in high-performance applications like ternary content addressable memory (TCAM) and Hyperdimensional computing (HDC). In this paper, we explore the impact of SHE on 14 nm Fe-FinFETs using a cross-layer framework, analyzing how these effects and associated variations affect both circuit-level (TCAM cells) and system-level (HDC) performance. Our results reveal an increased error probability in Hamming distance (HD) calculations through the TCAM array when SHE and variations are present. Additionally, we demonstrate how SHE and variations influence the inference accuracy of the HDC framework.
铁电场效应晶体管（Fe）由于其无挥发性和低功耗等特性，已成为高效内存计算的一个有希望的候选者。然而，像Fe-FinFET这样的缩放3D器件存在明显的自热效应（SHE）和工艺变化。这些问题导致性能不一致，降低了可靠性，限制了它们在三元内容可寻址存储器（TCAM）和超维计算（HDC）等高性能应用中的适用性。在本文中，我们使用跨层框架探讨了SHE对14nm fe - finfet的影响，分析了这些影响和相关变化如何影响电路级（TCAM单元）和系统级（HDC）性能。我们的研究结果表明，当SHE和变化存在时，通过TCAM阵列计算汉明距离（HD）的误差概率增加。此外，我们还演示了SHE和变化如何影响HDC框架的推理精度。
{"title":"Investigating Self-Heating Effects in Ferroelectric FinFETs for Reliable In-Memory Computing","authors":"Swati Deshwal;Shubham Kumar;Swetaki Chatterjee;Anirban Kar;Shivendra Singh Parihar;Yogesh Singh Chauhan;Hussam Amrouch","doi":"10.1109/JEDS.2025.3559332","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3559332","url":null,"abstract":"Ferroelectric (Fe) FET has emerged as a promising candidate for efficient in-memory computing due to its properties, such as non-volatility and low power. However, scaled 3D devices such as Fe-FinFET suffer from significant self-heating effects (SHE) and process variations. These issues cause inconsistent performance and reduce reliability, limiting their applicability in high-performance applications like ternary content addressable memory (TCAM) and Hyperdimensional computing (HDC). In this paper, we explore the impact of SHE on 14 nm Fe-FinFETs using a cross-layer framework, analyzing how these effects and associated variations affect both circuit-level (TCAM cells) and system-level (HDC) performance. Our results reveal an increased error probability in Hamming distance (HD) calculations through the TCAM array when SHE and variations are present. Additionally, we demonstrate how SHE and variations influence the inference accuracy of the HDC framework.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"838-844"},"PeriodicalIF":2.4,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10960387","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144764084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1109/JEDS.2025.3557432
Yuxuan Chen;Fugui Zhou;Yongheng Gong;Yongbo Su;Wuchang Ding;Jingyuan Shi;Peng Ding;Zhi Jin
Cryogenic InP High-electron-mobility transistors (HEMTs)-based low-noise amplifiers (LNAs) have been applied in deep space exploration, which demands high performance from InP HEMTs. Specifically, at low temperatures, the device needs to achieve low power consumption and high operating frequency. In this study, we fabricated a double-recessed InP HEMT with a heavily doped In0.65Ga0.35As/In0.53Ga0.47As/In0.52Al0.48As multilayer cap structure to optimize the device’s performance at low temperatures. At low temperatures, excessive on-resistance (RON) leads to increased power dissipation and also contributes to higher noise, which affects the performance of the LNAs. We employed the heavily doped In0.65Ga0.35As layer to reduce the metal-semiconductor contact resistance, thereby effectively lowering RON. Experimental results show that at 7 K, the device’s RON is $410~Omega cdot mu $ m, which could effectively reduce the power dissipation. Additionally, we adopted a double-recessed gate structure. This structure significantly improves the device’s maximum oscillation frequency($f_{max }$ ) by reducing the parasitic capacitance. At 7 K, the device’s $f_{max }$ reaches 740GHz. Furthermore, the design of the second gate recess reduces the exposed area of the gate recess, which combined with the $rm Si_{3}N_{4}$ passivation layer, effectively suppresses the kink effect caused by surface traps at low temperatures, further improving the device’s cryogenic performance.
{"title":"Cryogenic InP HEMTs With Enhanced fmax and Reduced On-Resistance Using Double Recess","authors":"Yuxuan Chen;Fugui Zhou;Yongheng Gong;Yongbo Su;Wuchang Ding;Jingyuan Shi;Peng Ding;Zhi Jin","doi":"10.1109/JEDS.2025.3557432","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3557432","url":null,"abstract":"Cryogenic InP High-electron-mobility transistors (HEMTs)-based low-noise amplifiers (LNAs) have been applied in deep space exploration, which demands high performance from InP HEMTs. Specifically, at low temperatures, the device needs to achieve low power consumption and high operating frequency. In this study, we fabricated a double-recessed InP HEMT with a heavily doped In0.65Ga0.35As/In0.53Ga0.47As/In0.52Al0.48As multilayer cap structure to optimize the device’s performance at low temperatures. At low temperatures, excessive on-resistance (RON) leads to increased power dissipation and also contributes to higher noise, which affects the performance of the LNAs. We employed the heavily doped In0.65Ga0.35As layer to reduce the metal-semiconductor contact resistance, thereby effectively lowering RON. Experimental results show that at 7 K, the device’s RON is <inline-formula> <tex-math>$410~Omega cdot mu $ </tex-math></inline-formula>m, which could effectively reduce the power dissipation. Additionally, we adopted a double-recessed gate structure. This structure significantly improves the device’s maximum oscillation frequency(<inline-formula> <tex-math>$f_{max }$ </tex-math></inline-formula>) by reducing the parasitic capacitance. At 7 K, the device’s <inline-formula> <tex-math>$f_{max }$ </tex-math></inline-formula> reaches 740GHz. Furthermore, the design of the second gate recess reduces the exposed area of the gate recess, which combined with the <inline-formula> <tex-math>$rm Si_{3}N_{4}$ </tex-math></inline-formula> passivation layer, effectively suppresses the kink effect caused by surface traps at low temperatures, further improving the device’s cryogenic performance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"366-372"},"PeriodicalIF":2.0,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10948522","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1109/JEDS.2025.3557732
Jangseop Lee;Taras Ravsher;Daniele Garbin;Sergiu Clima;Robin Degraeve;Attilio Belmonte;Hyunsang Hwang;Inhee Lee
In this study, we investigated the effect of pulse falling time (Tfall) on the electrical characteristics of SiGeAsSe-based selector-only memory (SOM) devices. Our experimental results demonstrate that increasing the $mathrm { T_{fall}}$ leads to an increased threshold voltage (Vth) and reduced $mathrm { V_{th}}$ drift in SiGeAsSe devices. The optimized devices exhibit a remarkable memory window (> 1 V) and significantly suppressed drift characteristics (~10 mV/dec.). Electrical measurements at high temperatures demonstrate that $mathrm { T_{fall}}$ is one of the important factors in material relaxation, and these improvements are attributed to the intentionally induced reconfiguration of the chalcogenide film. Furthermore, our results reveal that a suitable $mathrm { T_{fall}}$ can effectively mitigate the degradation of the memory window at high temperatures. These findings afford valuable insights into the role of material relaxation in SOM devices, potentially aiding the development of high-performance memory devices.
{"title":"Optimizing Pulse Conditions for Enhanced Memory Performance of Se-Based Selector-Only Memory","authors":"Jangseop Lee;Taras Ravsher;Daniele Garbin;Sergiu Clima;Robin Degraeve;Attilio Belmonte;Hyunsang Hwang;Inhee Lee","doi":"10.1109/JEDS.2025.3557732","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3557732","url":null,"abstract":"In this study, we investigated the effect of pulse falling time (Tfall) on the electrical characteristics of SiGeAsSe-based selector-only memory (SOM) devices. Our experimental results demonstrate that increasing the <inline-formula> <tex-math>$mathrm { T_{fall}}$ </tex-math></inline-formula> leads to an increased threshold voltage (Vth) and reduced <inline-formula> <tex-math>$mathrm { V_{th}}$ </tex-math></inline-formula> drift in SiGeAsSe devices. The optimized devices exhibit a remarkable memory window (> 1 V) and significantly suppressed drift characteristics (~10 mV/dec.). Electrical measurements at high temperatures demonstrate that <inline-formula> <tex-math>$mathrm { T_{fall}}$ </tex-math></inline-formula> is one of the important factors in material relaxation, and these improvements are attributed to the intentionally induced reconfiguration of the chalcogenide film. Furthermore, our results reveal that a suitable <inline-formula> <tex-math>$mathrm { T_{fall}}$ </tex-math></inline-formula> can effectively mitigate the degradation of the memory window at high temperatures. These findings afford valuable insights into the role of material relaxation in SOM devices, potentially aiding the development of high-performance memory devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"362-365"},"PeriodicalIF":2.0,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10949046","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143830515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1109/JEDS.2025.3557401
Oliver Durnan;Reem Alshanbari;Hong-Rae Cho;Ioannis Kymissis;Chang-Hyun Kim
This paper investigates the dependence of effective carrier mobility on the channel length in oxide thin-film transistors (TFTs). Bottom-gate staggered TFTs fabricated with a sputtered indium-galliumzinc-oxide channel exhibit a substantial increase in field-effect mobility with decreasing channel length, which is at variance with typical manifestation of contact resistance. An original model is thus proposed to describe the channel-length-dependent mobility in these TFTs. By decoupling local and intrinsic transport properties affecting the drain current, the model reproduces and rationalizes the observed phenomena. These results provide both a practical modeling tool and fundamental insights into the behaviors of oxide TFTs associated with the charge injection at their metal/semiconductor interface.
{"title":"Modeling the Increase in Effective Mobility in Short-Channel Oxide Thin-Film Transistors","authors":"Oliver Durnan;Reem Alshanbari;Hong-Rae Cho;Ioannis Kymissis;Chang-Hyun Kim","doi":"10.1109/JEDS.2025.3557401","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3557401","url":null,"abstract":"This paper investigates the dependence of effective carrier mobility on the channel length in oxide thin-film transistors (TFTs). Bottom-gate staggered TFTs fabricated with a sputtered indium-galliumzinc-oxide channel exhibit a substantial increase in field-effect mobility with decreasing channel length, which is at variance with typical manifestation of contact resistance. An original model is thus proposed to describe the channel-length-dependent mobility in these TFTs. By decoupling local and intrinsic transport properties affecting the drain current, the model reproduces and rationalizes the observed phenomena. These results provide both a practical modeling tool and fundamental insights into the behaviors of oxide TFTs associated with the charge injection at their metal/semiconductor interface.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"350-354"},"PeriodicalIF":2.0,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10948409","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Brain-inspired computing, with its potential for energy-efficient spatio-temporal data processing, has spurred significant interest in spiking neural networks and their hardware implementations. Leveraging their non-volatile memory and analog tunability, Ferroelectric field-effect transistors have emerged as promising candidates for realizing low-power synaptic devices within spiking neural networks. However, previous ferroelectric field-effect transistor-based implementations of spike-timing-dependent plasticity, a crucial learning mechanism in spiking neural networks, have often relied on complex circuit topologies or suffered from high energy consumption. Here, we report a comprehensive study of spike-timing-dependent plasticity learning dynamics in silicon-doped hafnium oxide-based ferroelectric field effect transistors, demonstrating precise control of synaptic weight modulation using various spike shapes and timings. We investigate the impact of different spike waveforms on energy consumption and find that triangular spikes achieve a 20% reduction in energy consumption compared to rectangular spikes, a significant improvement for large-scale spiking neural network implementations. Our results highlight the potential of single-device ferroelectric field-effect transistor synapses for realizing energy-efficient and scalable spiking neural networks, paving the way for next-generation neuromorphic computing.
{"title":"Spike-Timing Dependent Learning Dynamics in Silicon-Doped Hafnium-Oxide-Based Ferroelectric Field Effect Transistors","authors":"Masud Rana Sk;Apu Das;Gautham Kumar;Deepanshi Bhatnagar;Sourodeep Roy;Yannick Raffel;Maximilian Lederer;Konrad Seidel;Sourav De;Bhaswar Chakrabarti","doi":"10.1109/JEDS.2025.3556675","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3556675","url":null,"abstract":"Brain-inspired computing, with its potential for energy-efficient spatio-temporal data processing, has spurred significant interest in spiking neural networks and their hardware implementations. Leveraging their non-volatile memory and analog tunability, Ferroelectric field-effect transistors have emerged as promising candidates for realizing low-power synaptic devices within spiking neural networks. However, previous ferroelectric field-effect transistor-based implementations of spike-timing-dependent plasticity, a crucial learning mechanism in spiking neural networks, have often relied on complex circuit topologies or suffered from high energy consumption. Here, we report a comprehensive study of spike-timing-dependent plasticity learning dynamics in silicon-doped hafnium oxide-based ferroelectric field effect transistors, demonstrating precise control of synaptic weight modulation using various spike shapes and timings. We investigate the impact of different spike waveforms on energy consumption and find that triangular spikes achieve a 20% reduction in energy consumption compared to rectangular spikes, a significant improvement for large-scale spiking neural network implementations. Our results highlight the potential of single-device ferroelectric field-effect transistor synapses for realizing energy-efficient and scalable spiking neural networks, paving the way for next-generation neuromorphic computing.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"762-768"},"PeriodicalIF":2.4,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10947015","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144764079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we propose a p-NiO/n-Ga2O3 hetero-junction (HJ) Schottky barrier diode (SBD) with low turn-on voltage (Von) and high breakdown voltage (BV) with a trench SBD as a control. An investigation of its electrical characteristics is simulated by Sentaurus TCAD. The HJ SBD utilizes a low work-function anode metal to form a top electrode by reducing the $rm V_{on}$ of the diode at the forward state. A fin structure and metal/semiconductor (M/S) junction or PN HJ was employed to achieve an enhanced BV at the reverse state. An attempt to optimize the electrical characteristics of the device by modifying its structural parameters is also comprehensively analyzed in this work. The HJ SBD achieves a low $rm V_{on}$ of 0.57 V and a Power Figure of Merit (P-FOM) of 3.79 GW/cm2, simultaneously. The proposed structure provides a new approach for realizing high performance $beta $ -Ga2O3 SBDs with high reverse blocking and low loss capabilities.
{"title":"Proposal and Simulation of β-Ga₂O₃ Hetero- Junction Schottky Diodes With Low Work-Function Anode and High Breakdown Voltage","authors":"Ce Wang;Hong Zhou;Sami Alghamdi;Chunxu Su;Zhihong Liu;Kui Dang;Xuefeng Zheng;Xiaohua Ma;Peijun Ma;Yue Hao;Jincheng Zhang","doi":"10.1109/JEDS.2025.3556408","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3556408","url":null,"abstract":"In this work, we propose a p-NiO/n-Ga2O3 hetero-junction (HJ) Schottky barrier diode (SBD) with low turn-on voltage (Von) and high breakdown voltage (BV) with a trench SBD as a control. An investigation of its electrical characteristics is simulated by Sentaurus TCAD. The HJ SBD utilizes a low work-function anode metal to form a top electrode by reducing the <inline-formula> <tex-math>$rm V_{on}$ </tex-math></inline-formula> of the diode at the forward state. A fin structure and metal/semiconductor (M/S) junction or PN HJ was employed to achieve an enhanced BV at the reverse state. An attempt to optimize the electrical characteristics of the device by modifying its structural parameters is also comprehensively analyzed in this work. The HJ SBD achieves a low <inline-formula> <tex-math>$rm V_{on}$ </tex-math></inline-formula> of 0.57 V and a Power Figure of Merit (P-FOM) of 3.79 GW/cm2, simultaneously. The proposed structure provides a new approach for realizing high performance <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 SBDs with high reverse blocking and low loss capabilities.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"334-342"},"PeriodicalIF":2.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945755","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-31DOI: 10.1109/JEDS.2025.3552036
Pragya R. Shrestha;Alexander Zaslavsky;Valery Ortiz Jimenez;Jason P. Campbell;Curt A. Richter
This paper presents a high-endurance capacitorless one-transistor (1T) cryogenic memory, fabricated in a 180 nm bulk CMOS technology, with a high memory window of ($10{^{{7}}}~I_{1}$ /$I_{0}$ sense current ratio) and prolonged retention. The memory is enabled by the bistable $I_{D}$ –$V_{G}$ transistor characteristics due to impact ionization (II) at cryogenic temperatures (T < 30 K). Focusing on critical memory reliability parameters—switching time, endurance, and retention characteristics—we present write/erase speeds down to $approx ~45$ ns at T < 10 K and cycling endurance surpassing $10^{9}$ cycles while maintaining the $I_{1}$ /$I_{0}$ memory window. Retention times of >10 s with a 30x memory window were observed in extensive high-speed measurements. The fast switching and retention characteristics combine to yield a low power ($mu $ W-range) candidate for local cache memory to support quantum sensing or quantum computing control circuitry. Additionally, our study outlines essential measurements crucial for exploring the viability of alternative memory solutions for low-temperature quantum sensing and computation applications.
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