Pub Date : 2024-11-04DOI: 10.1109/TMAG.2024.3491334
Junzhan Liu;Liang Zhang;Jinhao Li;Shaoqing Du;Hui Jin;Hongxi Liu;Kaihua Cao;He Zhang;Wang Kang
Computing-in-memory (CIM) technique has attracted considerable attention as a candidate path to surmount the “memory wall” bottleneck in the post-Moore era. Due to its non-volatile characteristics, low power dissipation, and short response latency, magnetoresistive random access memory (MRAM) has emerged as a widely researched memory medium for CIM designs. This article proposes a multi-bit CIM paradigm based on the resistance-sum principle. This paradigm is implemented in our fabricated dual-MTJ-single-bottom-electrode spin-orbit torque MRAM (SOT-MRAM), referred to as MB-SOT-CIM, which can also be conveniently configured for binary neural networks (BNNs). Thanks to this paradigm, over 50% weight loading is eliminated. Besides, a non-idealities tuning mechanism is presented for the time-domain output unit through a concise lookup table (LUT). This work is simulated using a 40-nm foundry process based on the test parameters of our fabricated SOT devices. Due to the utilization of higher-resistance SOT devices and optimal circuit design, the results demonstrate that the proposed MB-SOT-CIM achieves 57.35 TOPS/W energy efficiency under 4/4/4-bit precision, normalized to 917.6 TOPS/W at 1-bit precision, while exhibits enhanced robustness. This offers a promising technical solution for edge devices.
{"title":"A SOT-MRAM-Based CIM Design With Multi-Bit Resistance-Sum Paradigm and Non-Idealities Tuning Mechanism","authors":"Junzhan Liu;Liang Zhang;Jinhao Li;Shaoqing Du;Hui Jin;Hongxi Liu;Kaihua Cao;He Zhang;Wang Kang","doi":"10.1109/TMAG.2024.3491334","DOIUrl":"https://doi.org/10.1109/TMAG.2024.3491334","url":null,"abstract":"Computing-in-memory (CIM) technique has attracted considerable attention as a candidate path to surmount the “memory wall” bottleneck in the post-Moore era. Due to its non-volatile characteristics, low power dissipation, and short response latency, magnetoresistive random access memory (MRAM) has emerged as a widely researched memory medium for CIM designs. This article proposes a multi-bit CIM paradigm based on the resistance-sum principle. This paradigm is implemented in our fabricated dual-MTJ-single-bottom-electrode spin-orbit torque MRAM (SOT-MRAM), referred to as MB-SOT-CIM, which can also be conveniently configured for binary neural networks (BNNs). Thanks to this paradigm, over 50% weight loading is eliminated. Besides, a non-idealities tuning mechanism is presented for the time-domain output unit through a concise lookup table (LUT). This work is simulated using a 40-nm foundry process based on the test parameters of our fabricated SOT devices. Due to the utilization of higher-resistance SOT devices and optimal circuit design, the results demonstrate that the proposed MB-SOT-CIM achieves 57.35 TOPS/W energy efficiency under 4/4/4-bit precision, normalized to 917.6 TOPS/W at 1-bit precision, while exhibits enhanced robustness. This offers a promising technical solution for edge devices.","PeriodicalId":13405,"journal":{"name":"IEEE Transactions on Magnetics","volume":"61 1","pages":"1-6"},"PeriodicalIF":2.1,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142912570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-04DOI: 10.1109/TMAG.2024.3490860
Ruilin Zhou;Tao Wang;Yan Nie;Xian Wang
The dc superimposition characteristic is a crucial consideration when employing inductors. Taking a molded inductor with dimensions of $6.6times 6.6times 2.88$