Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037509
Y. Ohta, T. Mimoto, Y. Torimaru, R. Miyake
when the CBlCS ratio ia grsatar than 1. AV1 in 121 i s larger than the mnventiond AV, in (11. The CBCS ratio is about LO in praelioe. For the mndition AV* AV, the new cell -raga fapaeitanes is snavgh to be abovt 314 that af the mnvintianal cell ( see Fig.2 1 . Thus the density of the FEC cell b-m~a~ullygrraterthenthatafthc2-alsmentcel l . thatisfactorof 1.6( m T a b l e 1 ).ThismaksstheFECcellsvlfableforhighd~ruityDRAM~.
{"title":"A novel memory cell architecture for high-density DRAMs","authors":"Y. Ohta, T. Mimoto, Y. Torimaru, R. Miyake","doi":"10.1109/VLSIC.1989.1037509","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037509","url":null,"abstract":"when the CBlCS ratio ia grsatar than 1. AV1 in 121 i s larger than the mnventiond AV, in (11. The CBCS ratio is about LO in praelioe. For the mndition AV* AV, the new cell -raga fapaeitanes is snavgh to be abovt 314 that af the mnvintianal cell ( see Fig.2 1 . Thus the density of the FEC cell b-m~a~ullygrraterthenthatafthc2-alsmentcel l . thatisfactorof 1.6( m T a b l e 1 ).ThismaksstheFECcellsvlfableforhighd~ruityDRAM~.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124844125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037514
K. Arimoto, Y. Matsuda, K. Furutani, M. Tsukude, T. Oisiii, K. Mashiko, K. Fujishima
A new array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. On the basis of a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes a practical array-embedded ECC with little area penalty and no access overhead in the page mode. This array architecture is applied to a scaled-down 16-Mbit DRAM and has achieved high performance.
{"title":"A speed enhancement DRAM array architecture with embedded ECC","authors":"K. Arimoto, Y. Matsuda, K. Furutani, M. Tsukude, T. Oisiii, K. Mashiko, K. Fujishima","doi":"10.1109/VLSIC.1989.1037514","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037514","url":null,"abstract":"A new array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. On the basis of a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes a practical array-embedded ECC with little area penalty and no access overhead in the page mode. This array architecture is applied to a scaled-down 16-Mbit DRAM and has achieved high performance.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126638578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037484
B. Wooley
As a consequence of the continuing scaling of semiconductor integrated circuit technology, digital means of processing, storing, and transmitting signals are rapidly displacing analog alternatives across a broad range of applications. Compared with analog implementations, digital systems offer higher resolution, noise insensitivity. and enhanced flexibility. They are also earierto both design and test, and are more readily amenable to design automation. Programmable general purpose digital signal processors have been available for some years, and design tools that aid in the automated generation of efficient application specific processors are becoming available.
{"title":"High-performance analog-to-digital converters","authors":"B. Wooley","doi":"10.1109/VLSIC.1989.1037484","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037484","url":null,"abstract":"As a consequence of the continuing scaling of semiconductor integrated circuit technology, digital means of processing, storing, and transmitting signals are rapidly displacing analog alternatives across a broad range of applications. Compared with analog implementations, digital systems offer higher resolution, noise insensitivity. and enhanced flexibility. They are also earierto both design and test, and are more readily amenable to design automation. Programmable general purpose digital signal processors have been available for some years, and design tools that aid in the automated generation of efficient application specific processors are becoming available.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121234389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037491
M. Suzuki, N. Yamanaka, M. Hirata, S. Kikuchi
A Si bipolar circuit design technology for gigabit-per-second crosspoint switch LSI's is described. An 8X 8 and an expandable 16X 16 crosspoint switch LSI have been developed utilizing a new circuit design and super self-aligned process technology (SST-1A). The LSI's success- fully switched with a bit error rate of less than at 2.5 Gbit/s using a Z9 - 1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 80 ps at 1.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSI's have an ECL-compatible interface, -4- and - 2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8 X 8 LSI and 2.8 W for the expandable 16~ 16 LSI.
{"title":"A circuit design for 2 Gbit/s Si brpolar crosspoint switch LSIs","authors":"M. Suzuki, N. Yamanaka, M. Hirata, S. Kikuchi","doi":"10.1109/VLSIC.1989.1037491","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037491","url":null,"abstract":"A Si bipolar circuit design technology for gigabit-per-second crosspoint switch LSI's is described. An 8X 8 and an expandable 16X 16 crosspoint switch LSI have been developed utilizing a new circuit design and super self-aligned process technology (SST-1A). The LSI's success- fully switched with a bit error rate of less than at 2.5 Gbit/s using a Z9 - 1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 80 ps at 1.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSI's have an ECL-compatible interface, -4- and - 2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8 X 8 LSI and 2.8 W for the expandable 16~ 16 LSI.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114035070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037483
A. Shubat, Y. Cedar, B. Sani, D. Nguyen, A. Singh, S. Ali
{"title":"Mappable memory subsystem for high speed applications","authors":"A. Shubat, Y. Cedar, B. Sani, D. Nguyen, A. Singh, S. Ali","doi":"10.1109/VLSIC.1989.1037483","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037483","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115392807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037471
W. Henkels, N. Lu, W. Hwang, T. Rajeevakumar, R. Franch, K. Jenkins, T. J. Bumlot, D. Heidel, M. Immediato
{"title":"An experimental low temperature DRAM","authors":"W. Henkels, N. Lu, W. Hwang, T. Rajeevakumar, R. Franch, K. Jenkins, T. J. Bumlot, D. Heidel, M. Immediato","doi":"10.1109/VLSIC.1989.1037471","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037471","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122641491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037492
W. Haimsch, R. Krebs, K. Ziemann
A 2k x 8bit, ECL lOOK compatible BiCMOS SRAM with 4 ne 1 6 0 ' . -4.5V) address a c c e s s time is re6ort;d. The properly controlled bit . line voltageswing (60mV), a current sensing method and optimized ECL decoding circuits provide the reliable and fasf readout opeiation. The SRAM features an on chip write pulse generator. latches for input and output bits and a full six transistor CMOS cell array. Power dissipation is 1.9511 end chio size is 3.9x5.9mm2. The SRAM is curkently processed in 1.2um BiCMOS, using double metal, triple polysilicon end self aligned bipolar transistors. this contribution to saturation can be everted. The address access time is mainly determined by the wordline and bitline capacitence which deDends on the cell array-configuration. With respect to the driving capability of the Totem Pole buffer controlline wordline the best arrangement was fouGd to be 64 rows and 2 5 6 columns. B e a h l w r i t P a n d s m s p r i r . is shown in fig. 2 . The bitline ( Z B L l R ) potential is mainly fixed by two emitter followers (11T! 1ZT). Additionally a 30um PMOS transistor (12P) clamps the voltage swing to 60 mV. This small valtage swing is amplified by B bipolar sense ampiifier which consists oftwo stages. The first stage (15T, 14T). a bioolar differential pair, detects the voitage drop caused by the cell current at the resistors RSENSLl and RSENSR1. The voltage drop of the buried layer which connects the double collector contacts (11T, 12T) adds to the voltage drao at each sense resistor. 32 of these dif?erential pairs have common collectors and a common current source (16T). TO reduce voltage swing of the common collector nodes they are connected to the second stage. a.cascode configuration. which controlls the output buffer with latch. Column select is done a ECL signal of 200 mV voltage swing 1; the base of transistor 13T which works a s an emitter follower. If select signal is high, the current of the =ommon sense amplifier current source (16T) flows through the corresponding differential pair. For WRITE operation. clamp transistor (12P) and bipolar pullup transistors (11T. 12T) are switched off. while two NMOS transistors (12N. 13N); which connect bitline to the write bus. are switched on. The write bus 1BLLW. BLRW) itself is controlled by two.large NMOS transistors. An ECL WRITE pulse can be generated by an on chip C ~ n e r a t ~ r 1 W P G l . An external WRITE pulse signal can alternatively be used. An ECL multiplexer selects one of the both WRITE pulses. The WRITE bus consists of 16 signal lines end is controlled by 16 pull down NMOS transistors (200um). These are driven by 2x8 complementary CMOS signals which a r e generated from 8 DATA-IN signela. A system of 14 bias drivers supplies the 16k BiCMOS SRAM with the necessary reference voltaees. The SRAM features three operatio: modes: asynchronous without WPG or clock driven. with or without WPG. The clock input signal is internally converted to differential logic. Low ou
一个2k x 8位，ECL lOOK兼容的BiCMOS SRAM, 4 ne 16 0 '。-4.5V)地址a c c c c c s时间报告;正确控制钻头。线路电压振荡(60mV)，电流传感方法和优化的ECL解码电路提供了可靠和快速的读出操作。SRAM具有片上写脉冲发生器。用于输入和输出位的锁存器和一个完整的六晶体管CMOS单元阵列。功耗为1.9511，端部尺寸为3.9x5.9mm2。SRAM目前采用1.2um BiCMOS工艺，采用双金属、三多晶硅端自校准双极晶体管。这种对饱和度的贡献是可以改变的。地址访问时间主要由字行和位行容量决定，而字行和位行容量又取决于单元阵列的配置。考虑到图腾柱缓冲控制线的驱动能力，优选出64行2 ~ 6列的排列方式。B:我是说，我是说，我是说，我是说，我是说，我是说，我是说，我是说，我是说。如图2所示。位线(Z B L L R)势主要由两个发射器跟随器(11T!1 zt型)。此外，30um PMOS晶体管(12P)将电压摆幅箝位到60 mV。这个小的电压摆幅被B双极感放大器放大，该放大器由两级组成。第一级(15T, 14T)。一个生物极差分对，检测由电阻RSENSLl和RSENSR1处的细胞电流引起的电压下降。连接双集电极触点(11T, 12T)的埋地层的电压降增加了每个感测电阻处的电压损耗。其中32个不同?电压对具有公共集电极和公共电流源(16T)。为了减少普通集电极节点的电压摆动，它们被连接到第二级。a.cascode配置。用锁存器控制输出缓冲器。选柱时用ECL信号进行200mv电压摆幅1;晶体管13T的基极作为发射极跟随器工作。如果所选信号高，则=常识放大器电流源(16T)的电流流过相应的差分对。用于WRITE操作。钳形晶体管(12P)和双极上拉晶体管(11T)。12T)被关闭。两个NMOS晶体管(12N。13 n);将位线连接到写总线。都打开了。写总线1BLLW。BLRW本身由两家公司控制。大型NMOS晶体管。一个ECL WRITE脉冲可以由片上的C ~ n / r / 1 W / P / l产生。外部WRITE脉冲信号可以替代地使用。ECL多路复用器选择两个WRITE脉冲中的一个。WRITE总线由16根信号线组成，末端由16个下拉NMOS晶体管(200um)控制。这些是由由8个DATA-IN信号产生的2x8互补CMOS信号驱动的。一个由14个偏置驱动器组成的系统为16k BiCMOS SRAM提供必要的参考电压。SRAM具有三种操作模式:异步无WPG或时钟驱动。有或没有WPG。时钟输入信号在内部转换为差分逻辑。低输出阻抗发射器跟随器驱动两个~独立的时钟来限制负载。16k BiCMOS SRAM的不同部分对c - c - c - 8时间和功耗的贡献如表所示
{"title":"A 4ns 16k BiCMOS SRAM","authors":"W. Haimsch, R. Krebs, K. Ziemann","doi":"10.1109/VLSIC.1989.1037492","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037492","url":null,"abstract":"A 2k x 8bit, ECL lOOK compatible BiCMOS SRAM with 4 ne 1 6 0 ' . -4.5V) address a c c e s s time is re6ort;d. The properly controlled bit . line voltageswing (60mV), a current sensing method and optimized ECL decoding circuits provide the reliable and fasf readout opeiation. The SRAM features an on chip write pulse generator. latches for input and output bits and a full six transistor CMOS cell array. Power dissipation is 1.9511 end chio size is 3.9x5.9mm2. The SRAM is curkently processed in 1.2um BiCMOS, using double metal, triple polysilicon end self aligned bipolar transistors. this contribution to saturation can be everted. The address access time is mainly determined by the wordline and bitline capacitence which deDends on the cell array-configuration. With respect to the driving capability of the Totem Pole buffer controlline wordline the best arrangement was fouGd to be 64 rows and 2 5 6 columns. B e a h l w r i t P a n d s m s p r i r . is shown in fig. 2 . The bitline ( Z B L l R ) potential is mainly fixed by two emitter followers (11T! 1ZT). Additionally a 30um PMOS transistor (12P) clamps the voltage swing to 60 mV. This small valtage swing is amplified by B bipolar sense ampiifier which consists oftwo stages. The first stage (15T, 14T). a bioolar differential pair, detects the voitage drop caused by the cell current at the resistors RSENSLl and RSENSR1. The voltage drop of the buried layer which connects the double collector contacts (11T, 12T) adds to the voltage drao at each sense resistor. 32 of these dif?erential pairs have common collectors and a common current source (16T). TO reduce voltage swing of the common collector nodes they are connected to the second stage. a.cascode configuration. which controlls the output buffer with latch. Column select is done a ECL signal of 200 mV voltage swing 1; the base of transistor 13T which works a s an emitter follower. If select signal is high, the current of the =ommon sense amplifier current source (16T) flows through the corresponding differential pair. For WRITE operation. clamp transistor (12P) and bipolar pullup transistors (11T. 12T) are switched off. while two NMOS transistors (12N. 13N); which connect bitline to the write bus. are switched on. The write bus 1BLLW. BLRW) itself is controlled by two.large NMOS transistors. An ECL WRITE pulse can be generated by an on chip C ~ n e r a t ~ r 1 W P G l . An external WRITE pulse signal can alternatively be used. An ECL multiplexer selects one of the both WRITE pulses. The WRITE bus consists of 16 signal lines end is controlled by 16 pull down NMOS transistors (200um). These are driven by 2x8 complementary CMOS signals which a r e generated from 8 DATA-IN signela. A system of 14 bias drivers supplies the 16k BiCMOS SRAM with the necessary reference voltaees. The SRAM features three operatio: modes: asynchronous without WPG or clock driven. with or without WPG. The clock input signal is internally converted to differential logic. Low ou","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130007232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037468
U. Kawabe
Superconducting three-terminal devices have been extensively given attention as one of future digital devices since Bcdnorz and Mueller discovered high-critical-temperature superconductivity in the La-Ba-Cu-0 system. The use of zero-resistance superconductivity and low noise cryogenics is expectcd for a limiting field of silicone semiconductor devices. In this paper, it is worthwhile to review some superconducting threeterminal devices expected for fulure devices though almost the materials used are low-temperature superconductors. The feature of various devices hitheno reported is discussed. The possibility and problem of high-temperature superconducting devices are also discussed.
{"title":"A review of superconducting three-terminal devices","authors":"U. Kawabe","doi":"10.1109/VLSIC.1989.1037468","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037468","url":null,"abstract":"Superconducting three-terminal devices have been extensively given attention as one of future digital devices since Bcdnorz and Mueller discovered high-critical-temperature superconductivity in the La-Ba-Cu-0 system. The use of zero-resistance superconductivity and low noise cryogenics is expectcd for a limiting field of silicone semiconductor devices. In this paper, it is worthwhile to review some superconducting threeterminal devices expected for fulure devices though almost the materials used are low-temperature superconductors. The feature of various devices hitheno reported is discussed. The possibility and problem of high-temperature superconducting devices are also discussed.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121309511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037465
E. Seevinck, J. Dikken, H. Schumacher
Abstruct -An emitter coupled logic (ECL) lOOK compatible output buffer circuit fabricated in a submicrometer CMOS-only process is presented. High speed (0.9-11s delay) and sufficient precision are achieved through the use of a new circuit principle. Negative feedback and an error correction technique are applied in such a way that external components and/or additional power supplies are not required. Aspects of stability and accuracy are investigated and simulation results are discussed to explain the new circuit technique. The actual design and practical aspects of it, such as layout, implementation in silicon, as well as technology features, are shown. Measured results and simulation results, showing the good performance of the ECL output buffer across a wide range of capacitive loading, are presented.
{"title":"CMOS subnanosecond true-ECL output buffer","authors":"E. Seevinck, J. Dikken, H. Schumacher","doi":"10.1109/VLSIC.1989.1037465","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037465","url":null,"abstract":"Abstruct -An emitter coupled logic (ECL) lOOK compatible output buffer circuit fabricated in a submicrometer CMOS-only process is presented. High speed (0.9-11s delay) and sufficient precision are achieved through the use of a new circuit principle. Negative feedback and an error correction technique are applied in such a way that external components and/or additional power supplies are not required. Aspects of stability and accuracy are investigated and simulation results are discussed to explain the new circuit technique. The actual design and practical aspects of it, such as layout, implementation in silicon, as well as technology features, are shown. Measured results and simulation results, showing the good performance of the ECL output buffer across a wide range of capacitive loading, are presented.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131064920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of an outline font rasterizing LSI","authors":"I. Nagashirna, N. Kai, T. Minagawa, M. Ohhashi","doi":"10.1109/VLSIC.1989.1037517","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037517","url":null,"abstract":"lchiro Nagashima. Naoyuki Kai, Tsutomu Minagawa and Masahide Ohhashi Semiconductor Device Engineering Labratory Toshiba Corporation 580-1, Horikawa-cho, Saiwai-ku, Kawasaki, 210, Japan Phone (044)548-2511","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132566580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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