Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037503
P. Saul, D. Taylor
Digital to Analogue Converters (DACs) which each have a faster operating specification than any DAC currently available, The circuit is composed of a number of structured circuit blocks, each of which can be tested independently. This approach has benefits both during device evaluation and as an aid to minimising production test times. Inucduction A block diagram of a direct frequency synthesiser is shown in figure 1. The main operational difference between a direct frequency synthesiser and the Phase Locked Loop (PLL) type is that the DFS does not contain feedback loops. This is a major advantage in settling to a new frequency; a good PLL has acquisition times of amund Ims, whereas the DFS can acquire a new frequency in a time limited only by pipeline delays in the accumulator and the DAC settling time. The frequency shift in the DFS is phase coherent, which is very difficult to achieve in any other way. The primary source of stability is the clock oscillator, so that, in the limit, since the clock is always at a higher frequency than the output, the output phase noise is better than the clock itself.
{"title":"A 2 GHz clock direct frequency synthesiser","authors":"P. Saul, D. Taylor","doi":"10.1109/VLSIC.1989.1037503","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037503","url":null,"abstract":"Digital to Analogue Converters (DACs) which each have a faster operating specification than any DAC currently available, The circuit is composed of a number of structured circuit blocks, each of which can be tested independently. This approach has benefits both during device evaluation and as an aid to minimising production test times. Inucduction A block diagram of a direct frequency synthesiser is shown in figure 1. The main operational difference between a direct frequency synthesiser and the Phase Locked Loop (PLL) type is that the DFS does not contain feedback loops. This is a major advantage in settling to a new frequency; a good PLL has acquisition times of amund Ims, whereas the DFS can acquire a new frequency in a time limited only by pipeline delays in the accumulator and the DAC settling time. The frequency shift in the DFS is phase coherent, which is very difficult to achieve in any other way. The primary source of stability is the clock oscillator, so that, in the limit, since the clock is always at a higher frequency than the output, the output phase noise is better than the clock itself.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129029445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037488
T. Matsuura, M. Ban, T. Tsukada, S. Ueda, H. Sato
{"title":"An 8 bit 100 MHz 3 channel CMOS DAC with analog switching current cells","authors":"T. Matsuura, M. Ban, T. Tsukada, S. Ueda, H. Sato","doi":"10.1109/VLSIC.1989.1037488","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037488","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"346 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123355788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037516
J. Takahashi, S. Hamaguchi, K. Tansho, T. Kimura
To aclualize a continuous speech recognition System with a large vocabulary, we proposed ring-my-pmessor architecture 11-21, This architecture has the two features: highly parallel DTW(Dynamie Time Warping) processing [31 capability. which is the main algorithm used to realim speech recognition. and array size flexibility. which makes it possible to determine the number of PE(hxessing Element) contained by the array processor according to vocabulwy si?.. This paper describes the PE-LSl’s architecture used to realize a high performance array processor and the VLSI implementation methodology. and discusses obtained resulu.
为了实现具有大词汇量的连续语音识别系统，我们提出了ring-my-pmessor架构11-21，该架构具有两个特点:高度并行的DTW(Dynamie Time Warping)处理能力[31]。这是实现语音识别的主要算法。以及数组大小的灵活性。这使得可以根据词汇量来确定数组处理器所包含的PE(hxessing Element)的数量。本文介绍了用于实现高性能阵列处理器的PE-LSl体系结构和VLSI的实现方法。并对所得结果进行了讨论。
{"title":"A modularized speech recognition processor LSI with a highly parallel structure","authors":"J. Takahashi, S. Hamaguchi, K. Tansho, T. Kimura","doi":"10.1109/VLSIC.1989.1037516","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037516","url":null,"abstract":"To aclualize a continuous speech recognition System with a large vocabulary, we proposed ring-my-pmessor architecture 11-21, This architecture has the two features: highly parallel DTW(Dynamie Time Warping) processing [31 capability. which is the main algorithm used to realim speech recognition. and array size flexibility. which makes it possible to determine the number of PE(hxessing Element) contained by the array processor according to vocabulwy si?.. This paper describes the PE-LSl’s architecture used to realize a high performance array processor and the VLSI implementation methodology. and discusses obtained resulu.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128063656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037498
K. Kennnizaki, M. Ogata, T. Mochizuki, S. Kubono, T. Kazimoto, Y. Shimbo, K. Sato, O. Minato
I, In t roduc t i on Recently, P S ~ U ~ O s t a t i c RAH CllC21 (PSRAH) c l i i ~ ~ have been used w i d e l y i n m a i l wstems such as personal computers and p r i n t e r bu f fe rs . Since PSRAH uses a dynamic type of memory cell which cons is t s of one HOS t r ans i s to r and one CaPacitor. i t needs a per iod i c re f resh cyc le to re1,ain data. Because i t i s ex t rese ly d e s i r a b l e f o r PSRAn t o act as i f i t i s S R A I I , t h i s p e r i o d i c re f resh cyc le has to be c a r r i e d aut au tomat i ca l l y by the PSRA'I i t s e l f . Th is re f resh mode is c a l l e d s e l f r e f r e s h mode. In s e l f node. a IOW power d i s s i p a t i o n i s essential because t he c h i p v i l i r e q u i r e bat tery 'backup i n standby node. However. the sore nenory d e n s i t y increases, to I H b i t s , f o r i ns tance . t he h isher the power d i r s i P a t i o n becomes.
{"title":"A 36μa 4MB PSRAM with quadruple array operation","authors":"K. Kennnizaki, M. Ogata, T. Mochizuki, S. Kubono, T. Kazimoto, Y. Shimbo, K. Sato, O. Minato","doi":"10.1109/VLSIC.1989.1037498","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037498","url":null,"abstract":"I, In t roduc t i on Recently, P S ~ U ~ O s t a t i c RAH CllC21 (PSRAH) c l i i ~ ~ have been used w i d e l y i n m a i l wstems such as personal computers and p r i n t e r bu f fe rs . Since PSRAH uses a dynamic type of memory cell which cons is t s of one HOS t r ans i s to r and one CaPacitor. i t needs a per iod i c re f resh cyc le to re1,ain data. Because i t i s ex t rese ly d e s i r a b l e f o r PSRAn t o act as i f i t i s S R A I I , t h i s p e r i o d i c re f resh cyc le has to be c a r r i e d aut au tomat i ca l l y by the PSRA'I i t s e l f . Th is re f resh mode is c a l l e d s e l f r e f r e s h mode. In s e l f node. a IOW power d i s s i p a t i o n i s essential because t he c h i p v i l i r e q u i r e bat tery 'backup i n standby node. However. the sore nenory d e n s i t y increases, to I H b i t s , f o r i ns tance . t he h isher the power d i r s i P a t i o n becomes.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"388 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115584664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037519
G. Uvieghara, Y. Nakagome, D. Jeong, D. Hodges
Ahtract-Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional READ and WRITE operations. An experimental 1240-bit smart memory chip is implemented in a 1.6-pm double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34 658 transistors, occupies an area of 3.8 mm X 5.2 mm, and dissipates 0.51 W I117 [a.
RAT (Ahtract-Register Alias Table)是一种嵌入在高性能基板(HPSm)中的智能内存，HPSm是一种Berkeley数据流CPU。它是一种多端口内存，除了常规的READ和WRITE操作外，还具有内容可寻址性，并支持分支预测和异常处理。采用1.6 pm双金属可扩展CMOS工艺实现了实验性1240位智能存储芯片。该存储器在100 ns的周期时间内执行15次操作，具有34658个晶体管，占地3.8 mm X 5.2 mm，功耗为0.51 W I117 [a]。
{"title":"An on-chip smart memory for a data flow CPU","authors":"G. Uvieghara, Y. Nakagome, D. Jeong, D. Hodges","doi":"10.1109/VLSIC.1989.1037519","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037519","url":null,"abstract":"Ahtract-Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional READ and WRITE operations. An experimental 1240-bit smart memory chip is implemented in a 1.6-pm double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34 658 transistors, occupies an area of 3.8 mm X 5.2 mm, and dissipates 0.51 W I117 [a.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131836198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037515
Daeje Chin, Changhyun Kim, Y. Choi, D. Min, H. Hwang, Hoon Choi, S. Cho, T. Chung, C. Park, Y. Shin, Kwangpyuk Suh, Y. E. Park
In high-density DRAM'S, a large peak current of typically 200-300mA occurs when sense amplifiers start latching in a conventional scheme (Figure la), resulting in intolerable power bus noise. Four-phase drive for PMOS restoring was reported to reduce the pe& current by triggering four pull-up transistors successively.[l] The initial sensing operation by NMOS latches, however, is more critical to signal margjn and sensing speed.
{"title":"An expermental 16Mb DRAM with reduced peak-current noise","authors":"Daeje Chin, Changhyun Kim, Y. Choi, D. Min, H. Hwang, Hoon Choi, S. Cho, T. Chung, C. Park, Y. Shin, Kwangpyuk Suh, Y. E. Park","doi":"10.1109/VLSIC.1989.1037515","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037515","url":null,"abstract":"In high-density DRAM'S, a large peak current of typically 200-300mA occurs when sense amplifiers start latching in a conventional scheme (Figure la), resulting in intolerable power bus noise. Four-phase drive for PMOS restoring was reported to reduce the pe& current by triggering four pull-up transistors successively.[l] The initial sensing operation by NMOS latches, however, is more critical to signal margjn and sensing speed.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124186035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037496
C. Koo, T. Toms, J. Jelemensky, E. Carter, P. Smith
circuit technique that detects all possible process defects which may cause data retention or non-static failures in a CMOS SRAM array. The technique, dubbed Soft defect detection (SDD), can accomplish the 100% static test, that was unachievable previously, in milliseconds to assure perfect data retention without relying on high temperature hake. The SDD technique has been successfully implemented into the 16K bit SRAM module of a new 32 bit microcontroller. This paper will describe a newly developed
{"title":"High reliability CMOS SRAM with built-in soft defect detection","authors":"C. Koo, T. Toms, J. Jelemensky, E. Carter, P. Smith","doi":"10.1109/VLSIC.1989.1037496","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037496","url":null,"abstract":"circuit technique that detects all possible process defects which may cause data retention or non-static failures in a CMOS SRAM array. The technique, dubbed Soft defect detection (SDD), can accomplish the 100% static test, that was unachievable previously, in milliseconds to assure perfect data retention without relying on high temperature hake. The SDD technique has been successfully implemented into the 16K bit SRAM module of a new 32 bit microcontroller. This paper will describe a newly developed","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116119872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037511
H. Kotani, H. Akarnatsu, J. Matsushima, S. Okada, T. Shiragasawa, J. Houma, T. Yamada, M. Inoue
Ahstract-An 8-Mbit (1 Mwordsx8 bits) dynamic RAM for video applications has been developed. To obtain low peak current, a new sensing scheme called the column direction drive (CDD) sense amplifier is proposed. The power supply peak current is reduced to about one fourth when compared with conventional circuits. The chip is able to operate at 50 MHz. The chip is fabricated with a 0.7-pm n-well CMOS, double-level polysilicon, single polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell (SCC) structure. The cell sue is 1.8X3.0 pd, and the chip area is 12.7X 16.91 md.
{"title":"A 50MHz 8Mb video RAM with a column direction drive sense amplifier","authors":"H. Kotani, H. Akarnatsu, J. Matsushima, S. Okada, T. Shiragasawa, J. Houma, T. Yamada, M. Inoue","doi":"10.1109/VLSIC.1989.1037511","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037511","url":null,"abstract":"Ahstract-An 8-Mbit (1 Mwordsx8 bits) dynamic RAM for video applications has been developed. To obtain low peak current, a new sensing scheme called the column direction drive (CDD) sense amplifier is proposed. The power supply peak current is reduced to about one fourth when compared with conventional circuits. The chip is able to operate at 50 MHz. The chip is fabricated with a 0.7-pm n-well CMOS, double-level polysilicon, single polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell (SCC) structure. The cell sue is 1.8X3.0 pd, and the chip area is 12.7X 16.91 md.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130849975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037467
H. Yamauchi, H. Sakuma, Y. Fujinami, K. Takamizawa
Timing verification is one of the most difficult tasks In logic LSI designing. For example, in designing ASICs using automatic layout. despite the dispersion of wiring length has to be considered in clocking skew or setup/hold verification before the Layout. logic simulator cannot deal with such kinds of problems. and has a shortcoming that it can verify only those which can be activated by a given test pattern. The path analysis [I1 C21 Is another approach, however, i t has a wssibllity to detect the paths that cannot be activated and is only avallable for SimPIY smchronized circuits. Therefor, any exlsting CAD twls cannot verify the setup/hold constrafnts accurately. To overcome these problem we have developed a new timing analysis system, called ALTiCS. Thls system uses a new path analysis method. I.e., through the estlmation of logical behavlors. it can eliminate the paths that cannot be activated. Precise backward-trace for clock distribution circult relaxes the restriction on smchronlzation. Combination of two optimized Path trace realizes a setuP/hoid veriflcation within a practically acceptable mmputatlon time.
{"title":"ALTICS: an advanced timing analysis system for VLSI","authors":"H. Yamauchi, H. Sakuma, Y. Fujinami, K. Takamizawa","doi":"10.1109/VLSIC.1989.1037467","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037467","url":null,"abstract":"Timing verification is one of the most difficult tasks In logic LSI designing. For example, in designing ASICs using automatic layout. despite the dispersion of wiring length has to be considered in clocking skew or setup/hold verification before the Layout. logic simulator cannot deal with such kinds of problems. and has a shortcoming that it can verify only those which can be activated by a given test pattern. The path analysis [I1 C21 Is another approach, however, i t has a wssibllity to detect the paths that cannot be activated and is only avallable for SimPIY smchronized circuits. Therefor, any exlsting CAD twls cannot verify the setup/hold constrafnts accurately. To overcome these problem we have developed a new timing analysis system, called ALTiCS. Thls system uses a new path analysis method. I.e., through the estlmation of logical behavlors. it can eliminate the paths that cannot be activated. Precise backward-trace for clock distribution circult relaxes the restriction on smchronlzation. Combination of two optimized Path trace realizes a setuP/hoid veriflcation within a practically acceptable mmputatlon time.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128586644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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