Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037494
H. Tran, P. Fung, D. Scott
BiCMOS technolory has been ~ioven to be most effective for improving the performance of SRAMs. A sub 10"s access time has been reported in jl BiCMOS SRAM of IMeg bit density I] In addition to performance advantaaes. the availability of birk transistors in &CMOS technology has triggered an evolutibn of BiCMOS de"!" techniques for improving margin and minimining process sensitivity of Ultra Large Scale IC's. In this paper an Automatic Gain Control (AGC) circuit is discussed. This AGC circuit is applied to a high speed RiCMOS SRAM bitline scheme to control the bitline voltage swings BO that they are independent or temperature, operation and pmcess variations. Utilization of the superior small signal amplification eapabilitu of bioolar tranristor differential sense L~DB to directly coude
{"title":"Automatic gain control (AGC) circuit for high density BiCMOS SRAM","authors":"H. Tran, P. Fung, D. Scott","doi":"10.1109/VLSIC.1989.1037494","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037494","url":null,"abstract":"BiCMOS technolory has been ~ioven to be most effective for improving the performance of SRAMs. A sub 10\"s access time has been reported in jl BiCMOS SRAM of IMeg bit density I] In addition to performance advantaaes. the availability of birk transistors in &CMOS technology has triggered an evolutibn of BiCMOS de\"!\" techniques for improving margin and minimining process sensitivity of Ultra Large Scale IC's. In this paper an Automatic Gain Control (AGC) circuit is discussed. This AGC circuit is applied to a high speed RiCMOS SRAM bitline scheme to control the bitline voltage swings BO that they are independent or temperature, operation and pmcess variations. Utilization of the superior small signal amplification eapabilitu of bioolar tranristor differential sense L~DB to directly coude","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125638332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037486
S. Hosotani, T. Miki, A. Maoda, N. Yazawa
(MSjs) CMOS AjD con verter with SO-mW power consumption has been integrated into an area of 2.09 mm X 2.15 mm. The characteristics of low power consumption and small chip area have been achieved by introducing a new architecture to a subranging AjD converter. In this architecture, both coarse and fine AjD conversions can be accomplished in a unique circuit. Consequently, a large number of comparators and processing circuits for comparison results have been removed from the conventional subranging AjD converter. This arch itecture has been realized by the introduction of a new chopper-type comparator with three input terminals. This comparator makes both coarse and fine comparisons by itself with its sample-and-hold function. The AjD converter has two 8-bit sub-AjD converters which employ this new archi tecture, and they are pipelined to improve thc conversion rate. The experimental results have shown good performances. Both the differential and the integral nonlinearity are less than ±O.S LSB at a 2O-MSjs sampling frequency. The effective resolution at 20-MSjs sampling fre quency is 7.4 bits at a 1.97-MHz input frequency and 6.7 bits at a 9.79-MHz input frequency. The AjD converter has been fabricated in a I-I'm CMOS technology.
(MSjs) CMOS AjD转换器与SO-mW功耗已集成到2.09 mm X 2.15 mm的面积。通过引入一种新的结构，实现了低功耗和小芯片面积的特点。在这个体系结构中，粗的和细的AjD转换都可以在一个独特的电路中完成。因此，大量的比较器和用于比较结果的处理电路已经从传统的分频AjD转换器中移除。这种结构是通过引入一种具有三个输入端子的新型剪切比较器来实现的。该比较器通过其采样保持功能自行进行粗比较和细比较。AjD转换器有两个采用这种新架构的8位子AjD转换器，它们被流水线化以提高转换速率。实验结果表明，该方法具有良好的性能。微分非线性和积分非线性均小于±0。S LSB在20 - msjs采样频率下。在20-MSjs采样频率下，1.97 mhz输入频率下有效分辨率为7.4位，9.79 mhz输入频率下有效分辨率为6.7位。AjD转换器采用I-I - m CMOS技术制造。
{"title":"An 8-bit 20 MS/s CMOS A/D converter with 59 mW power consumption","authors":"S. Hosotani, T. Miki, A. Maoda, N. Yazawa","doi":"10.1109/VLSIC.1989.1037486","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037486","url":null,"abstract":"(MSjs) CMOS AjD con verter with SO-mW power consumption has been integrated into an area of 2.09 mm X 2.15 mm. The characteristics of low power consumption and small chip area have been achieved by introducing a new architecture to a subranging AjD converter. In this architecture, both coarse and fine AjD conversions can be accomplished in a unique circuit. Consequently, a large number of comparators and processing circuits for comparison results have been removed from the conventional subranging AjD converter. This arch itecture has been realized by the introduction of a new chopper-type comparator with three input terminals. This comparator makes both coarse and fine comparisons by itself with its sample-and-hold function. The AjD converter has two 8-bit sub-AjD converters which employ this new archi tecture, and they are pipelined to improve thc conversion rate. The experimental results have shown good performances. Both the differential and the integral nonlinearity are less than ±O.S LSB at a 2O-MSjs sampling frequency. The effective resolution at 20-MSjs sampling fre quency is 7.4 bits at a 1.97-MHz input frequency and 6.7 bits at a 9.79-MHz input frequency. The AjD converter has been fabricated in a I-I'm CMOS technology.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126696627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037479
K. Kobayashi, T. Nakayama, M. Hayashikoshi, Y. Miyawaki, Y. Terada, H. Arima, T. Matsukawa, T. Yoshihara
{"title":"A self-timed dynamic sensing scheme for 5V only multi-Mb flash E/sup 2/PROMs","authors":"K. Kobayashi, T. Nakayama, M. Hayashikoshi, Y. Miyawaki, Y. Terada, H. Arima, T. Matsukawa, T. Yoshihara","doi":"10.1109/VLSIC.1989.1037479","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037479","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124514868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037507
F. Kub, I. Mack, K. Moon
For the hyblid digital-analog approach, rhom in Figure 1. the --log loultiplier w e i g h t valves are generated from digical words stored in digital memory. The analog voltages are X-Y addrossed to rhe nulciplier sites using decoding circuitry and are dynsmically stored on capaciCorr aL the gatel of WOSFET conductance elements. The analog voltages are periodicelly refreshed from rhe vsighr values stored in the digital memory.
{"title":"Programmable vector-matrix multipliers for artificial neural networks","authors":"F. Kub, I. Mack, K. Moon","doi":"10.1109/VLSIC.1989.1037507","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037507","url":null,"abstract":"For the hyblid digital-analog approach, rhom in Figure 1. the --log loultiplier w e i g h t valves are generated from digical words stored in digital memory. The analog voltages are X-Y addrossed to rhe nulciplier sites using decoding circuitry and are dynsmically stored on capaciCorr aL the gatel of WOSFET conductance elements. The analog voltages are periodicelly refreshed from rhe vsighr values stored in the digital memory.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121469865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037481
M. Asakura, Y. Matsuda, H. Hidaka, Y. Tanaka, K. Fujishima, T. Yoshihara
In the recent progress of the micro procesaor unit (MPU), requirements for fast accom a p e d memories have become strong. And a cost-effective cache subsystem is desired for the low-end work station and the personal computer. On the other hand, as for DRAMs, problems of the reliability such as a-particle induced soft e r " will be more serious according to the increase of density. To overcome these problems, the DRAMs with on-chip ECC (Error Checking and Correcting) circuit were reportcd.l".12' But using ECC circnit, the access a p e d is delayed to d e t n t and Correct errors. This paper presents the newly proposed CACHE DRAM with the ECC circuit. This ECC circuit improves the reliability of the DRAM data. And on-chip cache =heme can provide a high-speed data mapping and relieve an access time loss for error correction and w reduces the average access time.
在最近的微处理器(MPU)的发展中，对快速访问和数据存储的要求越来越高。对于低端工作站和个人计算机，需要一种性价比高的缓存子系统。另一方面，对于dram来说，随着密度的增加，a粒子诱导的“软e - r”等可靠性问题将更加严重。为了克服这些问题，我们报道了带有片上ECC (Error Checking and Correcting)电路的dram。但使用ECC电路时，接入信号会被延迟，从而对信号进行检测和纠错。本文提出了一种基于ECC电路的高速缓存DRAM。该ECC电路提高了DRAM数据的可靠性。片上缓存可以提供高速的数据映射，减轻纠错的访问时间损失，减少平均访问时间。
{"title":"An eyperimental 1Mb cache DRAM with ECC","authors":"M. Asakura, Y. Matsuda, H. Hidaka, Y. Tanaka, K. Fujishima, T. Yoshihara","doi":"10.1109/VLSIC.1989.1037481","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037481","url":null,"abstract":"In the recent progress of the micro procesaor unit (MPU), requirements for fast accom a p e d memories have become strong. And a cost-effective cache subsystem is desired for the low-end work station and the personal computer. On the other hand, as for DRAMs, problems of the reliability such as a-particle induced soft e r \" will be more serious according to the increase of density. To overcome these problems, the DRAMs with on-chip ECC (Error Checking and Correcting) circuit were reportcd.l\".12' But using ECC circnit, the access a p e d is delayed to d e t n t and Correct errors. This paper presents the newly proposed CACHE DRAM with the ECC circuit. This ECC circuit improves the reliability of the DRAM data. And on-chip cache =heme can provide a high-speed data mapping and relieve an access time loss for error correction and w reduces the average access time.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129979723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037482
K. Nogami, T. Sakurai, K. Sawada, K. Sakaue, Y. Miyazawa, S. Tanaka, Y. Hiruta, K. Katoh, T. Takayanagi, T. Shirotopi, Y. Itoh, M. Uchma, T. Hzuka
Introduction After a Reduced Insrmction Set Computer (RISCJ was shown to be effective in increasing CPU perfomnceIl1, s e v d attempls have teen made to funher improve the CPU performance by including cache memory an the same chipl21. However, the formerly reported cache size is limited up to 2K bym. which is not sufficient to obtain more than 95% hit rate. This paper describes a 32K byte cache macro with an erperimmml RISC implemented on the Same chip.
{"title":"Circuit design of a 9ns-HIT-delay 32K byte cache macro","authors":"K. Nogami, T. Sakurai, K. Sawada, K. Sakaue, Y. Miyazawa, S. Tanaka, Y. Hiruta, K. Katoh, T. Takayanagi, T. Shirotopi, Y. Itoh, M. Uchma, T. Hzuka","doi":"10.1109/VLSIC.1989.1037482","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037482","url":null,"abstract":"Introduction After a Reduced Insrmction Set Computer (RISCJ was shown to be effective in increasing CPU perfomnceIl1, s e v d attempls have teen made to funher improve the CPU performance by including cache memory an the same chipl21. However, the formerly reported cache size is limited up to 2K bym. which is not sufficient to obtain more than 95% hit rate. This paper describes a 32K byte cache macro with an erperimmml RISC implemented on the Same chip.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134271665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037473
K. Ishibashi, T. Yamanaka, K. Shimohigashi
{"title":"An /spl alpha/-immune, 2V supply voltage SRAM using polysilicon PMOS load cell","authors":"K. Ishibashi, T. Yamanaka, K. Shimohigashi","doi":"10.1109/VLSIC.1989.1037473","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037473","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134264207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037485
C. Mangelsdorf
To achieve high input bandwidth, the flash architecture of Figure 1 vas used. A preamp buffers each of the 257 latching comparators improving dynamic response and isolating the input and reference ladder from snitching transients. Dual supplies (+SV and -5.2V) are used to provide a convenient ground centered input span with large over-range capability. The extra headroom afforded by dual supplies permits a large rwerse bias on the collector-base junctions of the input transistors. This avoids the distortion caused by voltage dependent input capacitance found in single supply flash ADCs.[l] A special form of cascode reduces Miller capacitance loading of the input pair wbile maintaining high switching speed. The small physical siie of the input devices (5.5 x 1.0 um emitters) leads to a tiny input capacitance of ZOpF, and contributes to high input bandwidth.
为了实现高输入带宽，使用了图1所示的闪存架构。前置放大器缓冲257个锁存比较器中的每一个，改善动态响应并隔离输入和参考阶梯，使其不受开关瞬态的影响。双电源(+SV和-5.2V)用于提供方便的地中心输入跨度，具有大的超量程能力。双电源提供的额外净空允许输入晶体管的集电极-基极结产生较大的反向偏置。这避免了由电压相关输入电容引起的失真，在单电源闪存adc中发现。[1]一种特殊形式的级联码在保持高开关速度的同时减少了输入对的米勒电容负载。输入器件的小物理尺寸(5.5 x 1.0 um发射器)导致ZOpF的微小输入电容，并有助于高输入带宽。
{"title":"Improving bandwidth and error rate in flash converters","authors":"C. Mangelsdorf","doi":"10.1109/VLSIC.1989.1037485","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037485","url":null,"abstract":"To achieve high input bandwidth, the flash architecture of Figure 1 vas used. A preamp buffers each of the 257 latching comparators improving dynamic response and isolating the input and reference ladder from snitching transients. Dual supplies (+SV and -5.2V) are used to provide a convenient ground centered input span with large over-range capability. The extra headroom afforded by dual supplies permits a large rwerse bias on the collector-base junctions of the input transistors. This avoids the distortion caused by voltage dependent input capacitance found in single supply flash ADCs.[l] A special form of cascode reduces Miller capacitance loading of the input pair wbile maintaining high switching speed. The small physical siie of the input devices (5.5 x 1.0 um emitters) leads to a tiny input capacitance of ZOpF, and contributes to high input bandwidth.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126367657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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