Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037467
H. Yamauchi, H. Sakuma, Y. Fujinami, K. Takamizawa
Timing verification is one of the most difficult tasks In logic LSI designing. For example, in designing ASICs using automatic layout. despite the dispersion of wiring length has to be considered in clocking skew or setup/hold verification before the Layout. logic simulator cannot deal with such kinds of problems. and has a shortcoming that it can verify only those which can be activated by a given test pattern. The path analysis [I1 C21 Is another approach, however, i t has a wssibllity to detect the paths that cannot be activated and is only avallable for SimPIY smchronized circuits. Therefor, any exlsting CAD twls cannot verify the setup/hold constrafnts accurately. To overcome these problem we have developed a new timing analysis system, called ALTiCS. Thls system uses a new path analysis method. I.e., through the estlmation of logical behavlors. it can eliminate the paths that cannot be activated. Precise backward-trace for clock distribution circult relaxes the restriction on smchronlzation. Combination of two optimized Path trace realizes a setuP/hoid veriflcation within a practically acceptable mmputatlon time.
{"title":"ALTICS: an advanced timing analysis system for VLSI","authors":"H. Yamauchi, H. Sakuma, Y. Fujinami, K. Takamizawa","doi":"10.1109/VLSIC.1989.1037467","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037467","url":null,"abstract":"Timing verification is one of the most difficult tasks In logic LSI designing. For example, in designing ASICs using automatic layout. despite the dispersion of wiring length has to be considered in clocking skew or setup/hold verification before the Layout. logic simulator cannot deal with such kinds of problems. and has a shortcoming that it can verify only those which can be activated by a given test pattern. The path analysis [I1 C21 Is another approach, however, i t has a wssibllity to detect the paths that cannot be activated and is only avallable for SimPIY smchronized circuits. Therefor, any exlsting CAD twls cannot verify the setup/hold constrafnts accurately. To overcome these problem we have developed a new timing analysis system, called ALTiCS. Thls system uses a new path analysis method. I.e., through the estlmation of logical behavlors. it can eliminate the paths that cannot be activated. Precise backward-trace for clock distribution circult relaxes the restriction on smchronlzation. Combination of two optimized Path trace realizes a setuP/hoid veriflcation within a practically acceptable mmputatlon time.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128586644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037477
S. All, D. Nguyen, B. Sani, A. Shubat, C. Hu, Y. Me, R. Kazarounian, B. Eltan
A new a r ray a r c h l t e c t u r e I s Introduced which I s s u l t a b l e f o r very h lgh dens l t y €PROMS. For a g lven se t o f deslgn r u l e s , t h l s approach y l e l d s 40% Smaller a r r a y size compared t o Drevlous a r r a y a rch l tec tu res . The Staggered V l r t u a l Ground (SVG) a r ray has been Implemented based on the sp l I t gate EPROM technology. A dual f unc t l on column muxlng scheme and Address T r a n s l t f o n Detec t lon deslgn techniques have been used t o achleve a 90nS 4Mb EPROM. The d l e size I s 7.6mn x 6 . 5 m and has been f a b r l c a t e d I n a 1.25um CMOS technology.
A ar ar新雷c h l t e c t u r e s I Introduced哪种美国洛杉矶t b h l e f o r非常lgh穴l t y€PROMS。对于一个人来说，这是不可能的。Staggered V l r r u Ground (SVG)有一段r ray根据sp . I t gate EPROM technology推出。一个反f的f我的尺寸是7。6×6。5米，一直是联邦调查局的技术。
{"title":"A new staggered virtual ground array architecture implemented in a 4Mb CMOS EPROM","authors":"S. All, D. Nguyen, B. Sani, A. Shubat, C. Hu, Y. Me, R. Kazarounian, B. Eltan","doi":"10.1109/VLSIC.1989.1037477","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037477","url":null,"abstract":"A new a r ray a r c h l t e c t u r e I s Introduced which I s s u l t a b l e f o r very h lgh dens l t y €PROMS. For a g lven se t o f deslgn r u l e s , t h l s approach y l e l d s 40% Smaller a r r a y size compared t o Drevlous a r r a y a rch l tec tu res . The Staggered V l r t u a l Ground (SVG) a r ray has been Implemented based on the sp l I t gate EPROM technology. A dual f unc t l on column muxlng scheme and Address T r a n s l t f o n Detec t lon deslgn techniques have been used t o achleve a 90nS 4Mb EPROM. The d l e size I s 7.6mn x 6 . 5 m and has been f a b r l c a t e d I n a 1.25um CMOS technology.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131194600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037511
H. Kotani, H. Akarnatsu, J. Matsushima, S. Okada, T. Shiragasawa, J. Houma, T. Yamada, M. Inoue
Ahstract-An 8-Mbit (1 Mwordsx8 bits) dynamic RAM for video applications has been developed. To obtain low peak current, a new sensing scheme called the column direction drive (CDD) sense amplifier is proposed. The power supply peak current is reduced to about one fourth when compared with conventional circuits. The chip is able to operate at 50 MHz. The chip is fabricated with a 0.7-pm n-well CMOS, double-level polysilicon, single polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell (SCC) structure. The cell sue is 1.8X3.0 pd, and the chip area is 12.7X 16.91 md.
{"title":"A 50MHz 8Mb video RAM with a column direction drive sense amplifier","authors":"H. Kotani, H. Akarnatsu, J. Matsushima, S. Okada, T. Shiragasawa, J. Houma, T. Yamada, M. Inoue","doi":"10.1109/VLSIC.1989.1037511","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037511","url":null,"abstract":"Ahstract-An 8-Mbit (1 Mwordsx8 bits) dynamic RAM for video applications has been developed. To obtain low peak current, a new sensing scheme called the column direction drive (CDD) sense amplifier is proposed. The power supply peak current is reduced to about one fourth when compared with conventional circuits. The chip is able to operate at 50 MHz. The chip is fabricated with a 0.7-pm n-well CMOS, double-level polysilicon, single polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell (SCC) structure. The cell sue is 1.8X3.0 pd, and the chip area is 12.7X 16.91 md.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130849975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037500
G. Nasserbakht, J. Adkisson, T. Kamins, B. Wooley, J. Harris
A fiber-optic receiver front-end integratedin B monolithic GaAr on silicon technology is described. In this circuit an interdigitated GaAs metal-semiconductor-metal photodetector is combined with a transimpedance preamplifier fabricated in silicon bipols technology. The integrated receiver is designed to operate with il bandwidth of 1GRz and a preamplifier transimpedance of 5kR.
{"title":"A monolithically integrated fiber-optic front-end receiver in GaAs Si technology","authors":"G. Nasserbakht, J. Adkisson, T. Kamins, B. Wooley, J. Harris","doi":"10.1109/VLSIC.1989.1037500","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037500","url":null,"abstract":"A fiber-optic receiver front-end integratedin B monolithic GaAr on silicon technology is described. In this circuit an interdigitated GaAs metal-semiconductor-metal photodetector is combined with a transimpedance preamplifier fabricated in silicon bipols technology. The integrated receiver is designed to operate with il bandwidth of 1GRz and a preamplifier transimpedance of 5kR.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132929600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037512
S. Dhong, W. Henkels, N. Lu, R. Scheuerlein, G. Brunner, K. Kitamura, V. Katavama, H. Niijima, T. Kirihata, R. Franch, W. Hwang, M. Nishiwaki, F. Pesavento, T. Rajeevakumar, Y. Sakaue, Y. Suzuki, E. Vañó
{"title":"An experimental 27w 1Mb CMOS high-speed DRAM","authors":"S. Dhong, W. Henkels, N. Lu, R. Scheuerlein, G. Brunner, K. Kitamura, V. Katavama, H. Niijima, T. Kirihata, R. Franch, W. Hwang, M. Nishiwaki, F. Pesavento, T. Rajeevakumar, Y. Sakaue, Y. Suzuki, E. Vañó","doi":"10.1109/VLSIC.1989.1037512","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037512","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132281526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037463
J. Gallia, A. Yee, K. Chau, I. Wang, W. Davis, K. Moore, B. Chas, C. Lemonds, R. Eklund, R. Havemann, T. Bonifield, J. Graham, J. Pozadzides, A. Shah
BiCMOS circuits have been shown to be particularly attractive lor gate array applications because 01 ECL I/O and the high on-chip capacitance drive capabilnies. Full BiCMOS gate arrays have been introduced with densities up to 20k gates11.2.sl. However, due to bipolar size constraints, higher density arrays have been restricted to CMOS wre with BiCMOS used only in the periphery of the wre and lor ECLmL 1/0.[41
{"title":"High performance BiCMOS circuit technology VLSI gate arrays","authors":"J. Gallia, A. Yee, K. Chau, I. Wang, W. Davis, K. Moore, B. Chas, C. Lemonds, R. Eklund, R. Havemann, T. Bonifield, J. Graham, J. Pozadzides, A. Shah","doi":"10.1109/VLSIC.1989.1037463","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037463","url":null,"abstract":"BiCMOS circuits have been shown to be particularly attractive lor gate array applications because 01 ECL I/O and the high on-chip capacitance drive capabilnies. Full BiCMOS gate arrays have been introduced with densities up to 20k gates11.2.sl. However, due to bipolar size constraints, higher density arrays have been restricted to CMOS wre with BiCMOS used only in the periphery of the wre and lor ECLmL 1/0.[41","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132295634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037513
H. Yamauchi, T. Yabu, T. Yamada, M. Inoue
1) INTRODUCTlON Recently,lG-Mbit DRAMS have been designed and fabricated using submicron CMOS technology. However, the submicron MOSFETs with LDD or Efficient Punch through Stop (EPS) structure 111 have serious problems-such as 1) the drain current asymmetry, 2) the threshold voltage difference , and 3) the gatekource capacitance imbalance. [21[31 This is due to asymmetry of source and drain impurity profile caused by the shadowing of ion-beams by gate electrodes. This asymmetry has been reported to degrade the sensitivity of a DRAM sense amplifier com osed of LDD or EPS transistors.[31 I41 Several metRods to suppress the asymmetry effects using the oblique-rotating ion implantation technique have been proposed.[Z1[51 In this paper, we propose a novel circuit design to suppress the sense amplifier asymmetry effects not using the special process technique, and describe the e x p e r i m e n t a l r e s u l t s a b o u t t h e s e n s i t i v i t y improvement of the 16-Mbit DRAM sense amplifier by using the circuit design technique, and also compare with the values in case of using the obliquerotatin ion implantaion technique.
最近，利用亚微米CMOS技术设计和制造了lmb dram。然而，具有LDD或高效穿孔通过停止(EPS)结构111的亚微米mosfet存在严重的问题，例如1)漏极电流不对称，2)阈值电压差，以及3)门源电容不平衡。[21]这是由于栅极对离子束的遮蔽造成源极和漏极杂质分布的不对称。据报道，这种不对称会降低由LDD或EPS晶体管组成的DRAM感测放大器的灵敏度。[31 I41]提出了几种利用斜旋转离子注入技术抑制不对称效应的方法。51 (Z1(在本文中,我们提出一种新颖的电路设计抑制放大器不对称影响不使用特殊工艺技术,并描述e x p e r m e n t l r e s u l t s b o t t h e s e u n s我t v t y改善16-Mbit DRAM读出放大器通过电路设计技术,并与使用obliquerotatin离子着床的值的技术。
{"title":"A circuit design to suppress asymmetrical characteristics in 16-Mbit DRAM sense amplifier","authors":"H. Yamauchi, T. Yabu, T. Yamada, M. Inoue","doi":"10.1109/VLSIC.1989.1037513","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037513","url":null,"abstract":"1) INTRODUCTlON Recently,lG-Mbit DRAMS have been designed and fabricated using submicron CMOS technology. However, the submicron MOSFETs with LDD or Efficient Punch through Stop (EPS) structure 111 have serious problems-such as 1) the drain current asymmetry, 2) the threshold voltage difference , and 3) the gatekource capacitance imbalance. [21[31 This is due to asymmetry of source and drain impurity profile caused by the shadowing of ion-beams by gate electrodes. This asymmetry has been reported to degrade the sensitivity of a DRAM sense amplifier com osed of LDD or EPS transistors.[31 I41 Several metRods to suppress the asymmetry effects using the oblique-rotating ion implantation technique have been proposed.[Z1[51 In this paper, we propose a novel circuit design to suppress the sense amplifier asymmetry effects not using the special process technique, and describe the e x p e r i m e n t a l r e s u l t s a b o u t t h e s e n s i t i v i t y improvement of the 16-Mbit DRAM sense amplifier by using the circuit design technique, and also compare with the values in case of using the obliquerotatin ion implantaion technique.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128681026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037499
M. Koyanagi, H. Takata, H. Mori, M. Hirose
1 . I n t r o d u c t i o n The o p t i c a l l y c o u p l e d t h r e e d i m e n s i o n a l common memory ( c a l l e d 3D-OCC memory h e r e a f t e r ) i a a newly p roposed i n t e l l i g e n t memory f o r h i g h speed p a r a l l e l p r o c e s s i n g i n c o m p u t a t i o n [ l ] . Rapid t r a n s f e r of memory d a t a and t h e i r s i m u l t a n e o u s use by many CPU's are key i s s u e s f o r a c h i e v i n g u l t r a f a s t p a r a l l e l p r o c e s s i n g . The 3 D O C C memory i a a b l e t o t r a n s f e r a l a r g e b l o c k of d a t a w i t h v e r y h i g h speed by means of o p t i c a l c o u p l i n g in t h e v e r t i c a l d i r e c t i o n , v h i l e t h e c o n v e n t i o n a l memory o p e r a t i o n i s c a r r i e d o u t in t h e h o r i a o n t a l p l s n e . A l s o , s t o r e d d a t a i n t h e c o m m o n memory c a n b e a c c e s s e d by many p r o o e s s o r a v i t h o u t c o l l i s i o n . T h i s p a p e r d e s c r i b e 8 t h e d e a i g n methodology o f s u c h 3D-OCC memory w i t h t h e c a p a c i t y of 4 K b i t a x l b i t x 4 l a y e r s b a s e d on 2pm CMOS t e c h n o l o g y .
{"title":"Design of optically coupled three dimensional common memory for parallel processor system","authors":"M. Koyanagi, H. Takata, H. Mori, M. Hirose","doi":"10.1109/VLSIC.1989.1037499","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037499","url":null,"abstract":"1 . I n t r o d u c t i o n The o p t i c a l l y c o u p l e d t h r e e d i m e n s i o n a l common memory ( c a l l e d 3D-OCC memory h e r e a f t e r ) i a a newly p roposed i n t e l l i g e n t memory f o r h i g h speed p a r a l l e l p r o c e s s i n g i n c o m p u t a t i o n [ l ] . Rapid t r a n s f e r of memory d a t a and t h e i r s i m u l t a n e o u s use by many CPU's are key i s s u e s f o r a c h i e v i n g u l t r a f a s t p a r a l l e l p r o c e s s i n g . The 3 D O C C memory i a a b l e t o t r a n s f e r a l a r g e b l o c k of d a t a w i t h v e r y h i g h speed by means of o p t i c a l c o u p l i n g in t h e v e r t i c a l d i r e c t i o n , v h i l e t h e c o n v e n t i o n a l memory o p e r a t i o n i s c a r r i e d o u t in t h e h o r i a o n t a l p l s n e . A l s o , s t o r e d d a t a i n t h e c o m m o n memory c a n b e a c c e s s e d by many p r o o e s s o r a v i t h o u t c o l l i s i o n . T h i s p a p e r d e s c r i b e 8 t h e d e a i g n methodology o f s u c h 3D-OCC memory w i t h t h e c a p a c i t y of 4 K b i t a x l b i t x 4 l a y e r s b a s e d on 2pm CMOS t e c h n o l o g y .","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125768352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037521
S. Kawahitc, M. Kameyama, T. Higuchi
1. I " 0 N In various VLSI systems for real-time applications, high-speed compact multipliers are required a s mcrocells. Signed-digit(SD) number representations are useful for such high-speed arithmetic circuits[l]. Since the SD number representation uses more than 3 values in each digit, we can expect the effective use of multiplevalued logic circuits for the compact harduare(VLS1) implementations. In particular, multiple-valued bidirectional current-mode circmits is essentially suitable. because frequently used linear summation including polarity can be performed by wiring[Z]. From the view point of compactness, the radix-4 SD number representation is attractive[31. For VLSI implementation, however, the radix-2 SD number( also called redundant binary number) representation is useful from the view points of stable and faster operation of multiple-valued current-mode circuits, if present VLSI process technology is directly used. In this paper, we describes high-speed compact radix-2 SO multiplier using multiple-valued current-mode logic circuits. A new tree structure of the SD multiplier using &-input addition of partial products are proposed. The current-mode wired summation can be fully used far the structure, so that the number of full adders and interconnections can be drastically reduced. The implemented results of a prototype adder chip as the basic module are shown. Finally, an application to highly parallel vector inner product processing is discussed. 2. BIDIREcTlowAL -DE SD llRIllHZlTC CIRCUITS The radix-2 SD number system utilized here is a redundant representation using a symmetrical digit set(-1. 0.1). Addition of two numbers, X and Y are performed by the following successive steps in each digit. STEP 1: STEP 2: 2c; + Yi = z> zi = xi + yi
1. 在各种用于实时应用的VLSI系统中，高速紧凑型乘法器需要5个微单元。符号数字(SD)数字表示对于这种高速算术电路是有用的[1]。由于SD数字表示在每个数字中使用3个以上的值，我们可以期望在紧凑硬件(VLS1)实现中有效地使用多重评估逻辑电路。特别是，多值双向电流模电路基本上是合适的。因为经常使用的包括极性的线性求和可以通过布线来完成[Z]。从紧性的角度来看，基-4 SD数表示是有吸引力的[31]。然而，对于VLSI实现，如果直接使用现有的VLSI工艺技术，从稳定和快速运行多值电流模式电路的角度来看，基数-2 SD数(也称为冗余二进制数)表示是有用的。在本文中，我们描述了高速紧凑的基数-2 SO乘法器采用多值电流型逻辑电路。提出了一种基于部分积&输入加法的SD乘法器树形结构。该结构充分利用了电流模式有线求和，从而大大减少了全加法器和互连的数量。给出了作为基本模块的加法器芯片原型的实现结果。最后讨论了在高度并行向量内积处理中的应用。2. 这里使用的基数-2 SD数系统是使用对称数字集(-1)的冗余表示。0.1)。两个数字X和Y的相加是通过对每个数字进行以下连续的步骤来完成的。步骤1:步骤2:2c;+ Yi = z> zi = xi + Yi
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Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037506
M. Shinagawa, Y. Akazawa, T. Wakimoto
1.Introductlon Recent LSI technology advances have resulted in major improvements in electronics. For A-to-D converters. particularly. not only a very high precision over 90 dB [I] but also an ultra high speed of 2 GHz for 6bit [2] have already been achieved. Accuracy and speed limitations of the converters are obviously important. Jitter problems are thought to be the principle limiting factors on the accuracy and speed of the converter. In this paper, our research penaining to these problems will be presented. First, a jitter generation model far a practical sampling system. including signal and clock generator jitter. will be proposed. Based on this model. a precision jitter measurement method is shown. which also enables each jitter component to be separated. Finally. accuracy and speed limitations of the converter will be discussed. and it will also be shown that effective band-width compro-ation between jitter reduction and operating speed are important for more advanced converter design.
1.最近大规模集成电路技术的进步导致了电子学的重大改进。用于a - d转换器。尤其是。不仅达到了超过90 dB [I]的高精度，而且还实现了6bit[2]的2ghz超高速。转换器的精度和速度限制显然很重要。抖动问题被认为是影响变换器精度和速度的主要限制因素。本文将介绍我们对这些问题的研究。首先，建立了实际采样系统的抖动生成模型。包括信号和时钟发生器抖动。将被提议。基于这个模型。给出了一种高精度的抖动测量方法。这也使得每个抖动组件可以被分离。最后。将讨论转换器的精度和速度限制。研究还表明，在减小抖动和运行速度之间进行有效的带宽补偿对于更高级的变换器设计是非常重要的。
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