Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037472
Y. Idei, N. Homma, H. Nambu, Y. Sakurai
The alpha-particle-induced soft-error mechanism in a high-speed bipolar SRAM which is used for the mainframe computers is investigated using a 3D device and circuit simu- lator. It is shown that a constant critical charge for the memory cell does not exist. This is because the memory cell's soft-error sensitivities to the charges collected at the base and collector of the cell transistor are different due to the difference in time constants of the base and collector. To take into account this sensitivity difference in the soft-error rate simulation, an ef- fective-charge model is proposed. This model incorporates weight coefficients that express the memory cell's soft-error sensitivities to the charges collected at the base and collector. Accelerated soft-error rates of the 4-kb SRAM's are simulated using the effective-charge model. Good agreement with exper- imental results is obtained.
{"title":"Soft-error characteristics in bipolar memory cells with small critical charge","authors":"Y. Idei, N. Homma, H. Nambu, Y. Sakurai","doi":"10.1109/VLSIC.1989.1037472","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037472","url":null,"abstract":"The alpha-particle-induced soft-error mechanism in a high-speed bipolar SRAM which is used for the mainframe computers is investigated using a 3D device and circuit simu- lator. It is shown that a constant critical charge for the memory cell does not exist. This is because the memory cell's soft-error sensitivities to the charges collected at the base and collector of the cell transistor are different due to the difference in time constants of the base and collector. To take into account this sensitivity difference in the soft-error rate simulation, an ef- fective-charge model is proposed. This model incorporates weight coefficients that express the memory cell's soft-error sensitivities to the charges collected at the base and collector. Accelerated soft-error rates of the 4-kb SRAM's are simulated using the effective-charge model. Good agreement with exper- imental results is obtained.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123185250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037495
Y. Takahashi, T. Ishii, H. Kanda, M. Arimura, M. Sugiyama, T. Tashiro, T. Shimizu
{"title":"\"A 1.6ns 64kb ECL RAM with 1K gate logic\"","authors":"Y. Takahashi, T. Ishii, H. Kanda, M. Arimura, M. Sugiyama, T. Tashiro, T. Shimizu","doi":"10.1109/VLSIC.1989.1037495","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037495","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116944906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037520
H. Takata, S. Komori, T. Tamum, F. Asai, T. Tokuda, K. Shima, H. Nisbikawa, H. Terada
{"title":"A 100 mega-access matching memory for a data-driven microprocessor","authors":"H. Takata, S. Komori, T. Tamum, F. Asai, T. Tokuda, K. Shima, H. Nisbikawa, H. Terada","doi":"10.1109/VLSIC.1989.1037520","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037520","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129079698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037478
K. Imamiya, J. Miyamoto, N. Ohtstika, S. Atsurni, T. Sako, Y. Muroya, S. Mori, K. Yoshikawa, S. Tanaka
In a VLSI memory, noise generated by its own operation becomes a serious problem. The noise disturbs data sensing, especially in EPROM's which have a single-ended sensing scheme. To develop high- density and high-speed EPROM's, it is inevitably necessary to solve the noise problems. Incorrect EPROM functions due to the noise are dis- cussed in this paper. High-noise-immunity circuit techniques are proposed for stable data sensing and high-speed access time. Thesecare divided bit-line layout, reference line with dummy bit lines, and CE transition detector. Using these circuit techniques and 0.8- pm n-well CMOS technol- ogy, a 512K X 8-bit CMOS EPROM was developed. A 6&ns access time was achieved. The die sue is 5.62 mm X 15.30 mm and it is assembled in a 600-mil cerdip package.
在超大规模集成电路存储器中，其自身运行产生的噪声成为一个严重的问题。噪声干扰了数据传感，特别是在单端传感方案的EPROM中。要发展高密度、高速的EPROM，必然要解决噪声问题。本文讨论了噪声对EPROM功能的影响。为了稳定的数据感知和高速的访问时间，提出了高抗噪电路技术。它们包括分割位线布局、带虚拟位线的参考线和CE过渡检测器。利用这些电路技术和0.8 pm n阱CMOS技术，开发了一个512K X 8位CMOS EPROM。实现了6&ns的访问时间。该模具是5.62毫米X 15.30毫米，它是在一个600毫米的cerdip封装组装。
{"title":"A 68ns 4Mbit CMOS EPROM with high noise immunity design","authors":"K. Imamiya, J. Miyamoto, N. Ohtstika, S. Atsurni, T. Sako, Y. Muroya, S. Mori, K. Yoshikawa, S. Tanaka","doi":"10.1109/VLSIC.1989.1037478","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037478","url":null,"abstract":"In a VLSI memory, noise generated by its own operation becomes a serious problem. The noise disturbs data sensing, especially in EPROM's which have a single-ended sensing scheme. To develop high- density and high-speed EPROM's, it is inevitably necessary to solve the noise problems. Incorrect EPROM functions due to the noise are dis- cussed in this paper. High-noise-immunity circuit techniques are proposed for stable data sensing and high-speed access time. Thesecare divided bit-line layout, reference line with dummy bit lines, and CE transition detector. Using these circuit techniques and 0.8- pm n-well CMOS technol- ogy, a 512K X 8-bit CMOS EPROM was developed. A 6&ns access time was achieved. The die sue is 5.62 mm X 15.30 mm and it is assembled in a 600-mil cerdip package.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121352501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037461
R. Katz
Single-chip processor performance has improved dramatically since the inception of the four-bit microprocessor in 1971. This is due in part to technological advances (i.e., faster devices and greater device density), but also because of the adoption of architectural approaches well suited to the opportunities and limitations of VLSI. These approaches reduce off-chip memory accesses and admit of a regular pipelined implementation. They are good features of an architecture for VLSl implementation, whether or not the instruction set is "reduced.
{"title":"High performance VLSI processor architectures","authors":"R. Katz","doi":"10.1109/VLSIC.1989.1037461","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037461","url":null,"abstract":"Single-chip processor performance has improved dramatically since the inception of the four-bit microprocessor in 1971. This is due in part to technological advances (i.e., faster devices and greater device density), but also because of the adoption of architectural approaches well suited to the opportunities and limitations of VLSI. These approaches reduce off-chip memory accesses and admit of a regular pipelined implementation. They are good features of an architecture for VLSl implementation, whether or not the instruction set is \"reduced.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128543915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037508
K. Tsuchida, Y. Ogwaki, M. Ohta, D. Takashima, S. Watanabe
The stabilized reference-line (SRL) technique, which reduces bit-line interference noise, is described. This technique can eliminate the capacitance coupling noise generated when the cell data are transferred to the bit line. As a result, the noise generated by the sensing timing difference, which is caused by the coupling noise, does not arise. Furthermore, the SRL technique can be realized by modifying the conventional folded bit-line architecture. Therefore, it is easy to apply the SRL technique to high-density DRAMs. >
{"title":"The stabilized reference-line (SRL) technique for scaled DRAMs","authors":"K. Tsuchida, Y. Ogwaki, M. Ohta, D. Takashima, S. Watanabe","doi":"10.1109/VLSIC.1989.1037508","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037508","url":null,"abstract":"The stabilized reference-line (SRL) technique, which reduces bit-line interference noise, is described. This technique can eliminate the capacitance coupling noise generated when the cell data are transferred to the bit line. As a result, the noise generated by the sensing timing difference, which is caused by the coupling noise, does not arise. Furthermore, the SRL technique can be realized by modifying the conventional folded bit-line architecture. Therefore, it is easy to apply the SRL technique to high-density DRAMs. >","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121773758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037480
Y. Wada, T. Maruyama, M. Chida, S. Takeda, K. Shinada, K. Sekiguchi, V. Suzuki, K. Kanzaki, M. Wada, M. Yoshizawa
and low power consumption E'PROM is necessary. The other is the field of the CMOS ASIC. Important key factors in ASIC are technological versatility for various applications and quick turn around time (QTAT). A CMOS Is1 comumes extremely lower power and operates at wider Operating voltage range than the o t h a device onen. From an electrical performance point of view, these are the mcet preferable features when applying ASIC to various applications. For QTAT, incircuit
{"title":"A 1.7 volts operating CMOS 64K bit E/sup 2/ PROM","authors":"Y. Wada, T. Maruyama, M. Chida, S. Takeda, K. Shinada, K. Sekiguchi, V. Suzuki, K. Kanzaki, M. Wada, M. Yoshizawa","doi":"10.1109/VLSIC.1989.1037480","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037480","url":null,"abstract":"and low power consumption E'PROM is necessary. The other is the field of the CMOS ASIC. Important key factors in ASIC are technological versatility for various applications and quick turn around time (QTAT). A CMOS Is1 comumes extremely lower power and operates at wider Operating voltage range than the o t h a device onen. From an electrical performance point of view, these are the mcet preferable features when applying ASIC to various applications. For QTAT, incircuit","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117014368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-05-25DOI: 10.1109/VLSIC.1989.1037503
P. Saul, D. Taylor
Digital to Analogue Converters (DACs) which each have a faster operating specification than any DAC currently available, The circuit is composed of a number of structured circuit blocks, each of which can be tested independently. This approach has benefits both during device evaluation and as an aid to minimising production test times. Inucduction A block diagram of a direct frequency synthesiser is shown in figure 1. The main operational difference between a direct frequency synthesiser and the Phase Locked Loop (PLL) type is that the DFS does not contain feedback loops. This is a major advantage in settling to a new frequency; a good PLL has acquisition times of amund Ims, whereas the DFS can acquire a new frequency in a time limited only by pipeline delays in the accumulator and the DAC settling time. The frequency shift in the DFS is phase coherent, which is very difficult to achieve in any other way. The primary source of stability is the clock oscillator, so that, in the limit, since the clock is always at a higher frequency than the output, the output phase noise is better than the clock itself.
{"title":"A 2 GHz clock direct frequency synthesiser","authors":"P. Saul, D. Taylor","doi":"10.1109/VLSIC.1989.1037503","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037503","url":null,"abstract":"Digital to Analogue Converters (DACs) which each have a faster operating specification than any DAC currently available, The circuit is composed of a number of structured circuit blocks, each of which can be tested independently. This approach has benefits both during device evaluation and as an aid to minimising production test times. Inucduction A block diagram of a direct frequency synthesiser is shown in figure 1. The main operational difference between a direct frequency synthesiser and the Phase Locked Loop (PLL) type is that the DFS does not contain feedback loops. This is a major advantage in settling to a new frequency; a good PLL has acquisition times of amund Ims, whereas the DFS can acquire a new frequency in a time limited only by pipeline delays in the accumulator and the DAC settling time. The frequency shift in the DFS is phase coherent, which is very difficult to achieve in any other way. The primary source of stability is the clock oscillator, so that, in the limit, since the clock is always at a higher frequency than the output, the output phase noise is better than the clock itself.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129029445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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