Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979532
M. Ieong, E. C. Jones, T. Kanarsky, Zhibin Ren, Omer Dokumaci, Ronnen, Roy, Leathen Shi, SToshiharu Furukawa, Yuan Taw, Robert J. Miller, Philip Wong
Demonstrated double-gate devices with excellent drive current and short-channel-effect control. The double-gate devices exhibit ideal linear, sub-threshold slope of 60 mV/dec and better than ideal saturated sub-threshold slope of 55 mV/dec. The effective mobility in all device structures follows the universal mobility curve. The symmetric double-gate offers 20% mobility enhancement over a GP device at 1.0 V gate over-drive. Because the double-gate can be operated at a much lower effective-field, substantial mobility enhancement (>2X) over scaled bulk CMOS can be achieved. For the first time, DC operation of double-gate CMOS inverters are demonstrated down to Vdd=0.3 V.
{"title":"Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs","authors":"M. Ieong, E. C. Jones, T. Kanarsky, Zhibin Ren, Omer Dokumaci, Ronnen, Roy, Leathen Shi, SToshiharu Furukawa, Yuan Taw, Robert J. Miller, Philip Wong","doi":"10.1109/IEDM.2001.979532","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979532","url":null,"abstract":"Demonstrated double-gate devices with excellent drive current and short-channel-effect control. The double-gate devices exhibit ideal linear, sub-threshold slope of 60 mV/dec and better than ideal saturated sub-threshold slope of 55 mV/dec. The effective mobility in all device structures follows the universal mobility curve. The symmetric double-gate offers 20% mobility enhancement over a GP device at 1.0 V gate over-drive. Because the double-gate can be operated at a much lower effective-field, substantial mobility enhancement (>2X) over scaled bulk CMOS can be achieved. For the first time, DC operation of double-gate CMOS inverters are demonstrated down to Vdd=0.3 V.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"28 1","pages":"19.6.1-19.6.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88001403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979486
R. Van Langevelde, A. Scholten, R. Duffy, F. Cubaynes, M. J. Knitel, D. Klaassen
In this paper a new physical gate leakage model is introduced, which is both accurate and simple. It only uses 5 parameters, making parameter extraction straightforward. As a result the model can be used to extract effective length for modern CMOS technologies. The influence of gate current on the RF performance is studied.
{"title":"Gate current: Modeling, /spl Delta/L extraction and impact on RF performance","authors":"R. Van Langevelde, A. Scholten, R. Duffy, F. Cubaynes, M. J. Knitel, D. Klaassen","doi":"10.1109/IEDM.2001.979486","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979486","url":null,"abstract":"In this paper a new physical gate leakage model is introduced, which is both accurate and simple. It only uses 5 parameters, making parameter extraction straightforward. As a result the model can be used to extract effective length for modern CMOS technologies. The influence of gate current on the RF performance is studied.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"4 1","pages":"13.2.1-13.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88465526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979600
Keun-Ho Lee, Jin-Kyu Park, Young-Nam Yoon, Dai-Hyun Jung, J. Shin, Young-Kwan Park, J. Kong
Studies the effects of dummy-fills on the interconnect capacitance and the global planarity of chips in order to provide the design guideline of the dummy-fills. A simple but accurate full-chip RC extraction methodology taking the floating dummy-fills into account is proposed and applied to the analysis of changes in capacitance and signal delay of the global interconnects, for the first time. The results for 0.18 /spl mu/m designs clearly demonstrate the importance of considering floating dummy-fills in the interconnect modeling and the full-chip RC extraction.
{"title":"Analyzing the effects of floating dummy-fills: from feature scale analysis to full-chip RC extraction","authors":"Keun-Ho Lee, Jin-Kyu Park, Young-Nam Yoon, Dai-Hyun Jung, J. Shin, Young-Kwan Park, J. Kong","doi":"10.1109/IEDM.2001.979600","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979600","url":null,"abstract":"Studies the effects of dummy-fills on the interconnect capacitance and the global planarity of chips in order to provide the design guideline of the dummy-fills. A simple but accurate full-chip RC extraction methodology taking the floating dummy-fills into account is proposed and applied to the analysis of changes in capacitance and signal delay of the global interconnects, for the first time. The results for 0.18 /spl mu/m designs clearly demonstrate the importance of considering floating dummy-fills in the interconnect modeling and the full-chip RC extraction.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"84 ","pages":"31.3.1-31.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91448516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979664
Jinghong Chen, S. Kang
Electrostatically actuated MEMS mirror devices are finding increasing use in the field of optical communications and displays. In addition to the static displacement-voltage characteristics, accurate transient characterization of these devices is becoming increasingly important. The latter is strongly affected by viscous damping of the surrounding air. A complete analysis of the dynamic behavior should consist of coupled transient simulations including electrostatics, stress, deformation, and air fluidics. Direct numerical dynamic simulation based on fully-meshed structures is computationally very expensive. In order to perform efficient design prediction and optimization, designers need dynamically accurate macromodels for these devices. Such models need to reduce the computation cost without compromising accuracy. In this paper, we present techniques to develop such macromodels.
{"title":"Dynamic macromodeling of MEMS mirror devices","authors":"Jinghong Chen, S. Kang","doi":"10.1109/IEDM.2001.979664","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979664","url":null,"abstract":"Electrostatically actuated MEMS mirror devices are finding increasing use in the field of optical communications and displays. In addition to the static displacement-voltage characteristics, accurate transient characterization of these devices is becoming increasingly important. The latter is strongly affected by viscous damping of the surrounding air. A complete analysis of the dynamic behavior should consist of coupled transient simulations including electrostatics, stress, deformation, and air fluidics. Direct numerical dynamic simulation based on fully-meshed structures is computationally very expensive. In order to perform efficient design prediction and optimization, designers need dynamically accurate macromodels for these devices. Such models need to reduce the computation cost without compromising accuracy. In this paper, we present techniques to develop such macromodels.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"23 1","pages":"41.5.1-41.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86071291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979564
S. Esener
This paper describes the state of the art in free space optical interconnects as applied to chip-to-chip communication. We will review various technologies that integrate micro lasers and optical detectors with silicon CMOS, provide optical link characteristics obtained with these devices, and discuss the capabilities of low cost and robust optoelectronic packaging techniques to seamlessly integrate optics and electronics at the board level.
{"title":"Implementation and prospects for chip-to-chip free-space optical interconnects","authors":"S. Esener","doi":"10.1109/IEDM.2001.979564","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979564","url":null,"abstract":"This paper describes the state of the art in free space optical interconnects as applied to chip-to-chip communication. We will review various technologies that integrate micro lasers and optical detectors with silicon CMOS, provide optical link characteristics obtained with these devices, and discuss the capabilities of low cost and robust optoelectronic packaging techniques to seamlessly integrate optics and electronics at the board level.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"13 4 1","pages":"23.5.1-23.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87061001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979526
Yang-Kyu Choi, N. Lindert, Peiqi Xuan, Stephen Tang, Daewon Ha, E. Anderson, T. King, J. Bokor, C. Hu
A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current.
{"title":"Sub-20 nm CMOS FinFET technologies","authors":"Yang-Kyu Choi, N. Lindert, Peiqi Xuan, Stephen Tang, Daewon Ha, E. Anderson, T. King, J. Bokor, C. Hu","doi":"10.1109/IEDM.2001.979526","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979526","url":null,"abstract":"A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"26 1","pages":"19.1.1-19.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83261644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979510
P. Fromherz
The electrical interfacing of nerve cells and semiconductor microstructures is considered. The coupling of electron conducting silicon with ion conducting neurons relies on a close contact of the chip and the cell membrane with its ion channels. Excitation of neuronal activity is achieved by capacitive interaction with the channels and recording by the response of transistors to open channels. Integrated neuroelectronic systems are obtained by outgrowth of a neuronal net on silicon and by two-way interfacing of the neuronal and electronic components.
{"title":"Microelectronics meets molecular and neurobiology","authors":"P. Fromherz","doi":"10.1109/IEDM.2001.979510","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979510","url":null,"abstract":"The electrical interfacing of nerve cells and semiconductor microstructures is considered. The coupling of electron conducting silicon with ion conducting neurons relies on a close contact of the chip and the cell membrane with its ion channels. Excitation of neuronal activity is achieved by capacitive interaction with the channels and recording by the response of transistors to open channels. Integrated neuroelectronic systems are obtained by outgrowth of a neuronal net on silicon and by two-way interfacing of the neuronal and electronic components.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"16 1","pages":"16.1.1-16.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84294958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979648
M. Radhakrishnan, K. Pey, C. Tung, W. Lin, S. Ong
Detailed physical analysis is of paramount importance to understand the exact mechanisms of failures or degradation in devices, especially as dimensions are shrinking in nanometer scale. This paper describes the physical analysis of soft and hard breakdown failures of thin gate oxides to establish a link to the electrical failure signatures. The progression of changes happening in sub-nanometer levels during device degradation is illustrated using high-resolution transmission electron microscopic analysis.
{"title":"Physical analysis of reliability degradation in sub-micron devices","authors":"M. Radhakrishnan, K. Pey, C. Tung, W. Lin, S. Ong","doi":"10.1109/IEDM.2001.979648","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979648","url":null,"abstract":"Detailed physical analysis is of paramount importance to understand the exact mechanisms of failures or degradation in devices, especially as dimensions are shrinking in nanometer scale. This paper describes the physical analysis of soft and hard breakdown failures of thin gate oxides to establish a link to the electrical failure signatures. The progression of changes happening in sub-nanometer levels during device degradation is illustrated using high-resolution transmission electron microscopic analysis.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"18 1","pages":"39.1.1-39.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81723508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979660
M. A. Butler, E. R. Deutsch, S. Senturia, M. Sinclair, W. Sweatt, D. Youngner, G. Hocker
A MEMS-based programmable diffraction grating has been developed that can generate arbitrary spatial grating profiles on a sub-millisecond time scale. Such profiles redirect wavelengths in a polychromatic light beam. These devices can synthesize the spectra of molecules and manipulate signals in a wavelength-division-multiplexed optical telecommunications system.
{"title":"A MEMS-based programmable diffraction grating for optical holography in the spectral domain","authors":"M. A. Butler, E. R. Deutsch, S. Senturia, M. Sinclair, W. Sweatt, D. Youngner, G. Hocker","doi":"10.1109/IEDM.2001.979660","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979660","url":null,"abstract":"A MEMS-based programmable diffraction grating has been developed that can generate arbitrary spatial grating profiles on a sub-millisecond time scale. Such profiles redirect wavelengths in a polychromatic light beam. These devices can synthesize the spectra of molecules and manipulate signals in a wavelength-division-multiplexed optical telecommunications system.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"37 1","pages":"41.1.1-41.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81558516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Reich, D. O'Mara, D. Young, A. Loomis, D. Rathman, D. Craig, S. Watson, M. Ulibarri, B. Kosicki
A 512/spl times/512-element, multi-frame charge-coupled device (CCD) has been developed for collecting four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity, the imager uses an electronic shutter technology developed for back-illuminated CCDs. The megahertz frame rates also required metal strapping of the polysilicon gate electrodes. Tested imagers have demonstrated multi-frame capture capability.
{"title":"High-fill-factor, burst-frame-rate charge-coupled device","authors":"R. Reich, D. O'Mara, D. Young, A. Loomis, D. Rathman, D. Craig, S. Watson, M. Ulibarri, B. Kosicki","doi":"10.1117/12.520901","DOIUrl":"https://doi.org/10.1117/12.520901","url":null,"abstract":"A 512/spl times/512-element, multi-frame charge-coupled device (CCD) has been developed for collecting four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity, the imager uses an electronic shutter technology developed for back-illuminated CCDs. The megahertz frame rates also required metal strapping of the polysilicon gate electrodes. Tested imagers have demonstrated multi-frame capture capability.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"17 1","pages":"24.6.1-24.6.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89242770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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