International Journal of Circuit Theory and Applications最新文献

This paper introduces a novel three-phase grid-tied multilevel inverter (MLI) topology that employs a basic unit per phase, yielding a symmetrical configuration capable of generating five-level output voltage and an asymmetrical configuration producing seven-level and nine-level output voltages. The generalization of the proposed MLI is presented in terms of the number of modules (M) and output levels (L). A comprehensive comparative analysis of the proposed MLI topology against existing configurations is presented for both symmetric and asymmetric cases. The switching devices in the MLI are controlled using the in-phase disposition level shift PWM (IPD-LSPWM) technique. The synchronization of the grid-tied MLI is addressed by considering the uncertainties in grid and load parameters at the point of common coupling (PCC). To achieve synchronization, a PLL-less grid voltage- modulated direct power control (GVM-DPC) technique is implemented. To mitigate the delay associated with PLL, a GVM-DPC based on the stationary reference frame (SRF) is applied. This paper also includes mathematical modelling of GVM-DPC without PLL and the design of an LCL filter. A simulation model of a 15-kVA, three-phase, nine-level grid-tied MLI is developed in MATLAB/Simulink and tested under both steady-state and dynamic conditions. The proposed controller's performance is evaluated under the load variations and sudden changes in available power from the distributed generator (DG). Robustness is tested under adverse conditions such as voltage sag/swell at the PCC. Furthermore, the system is implemented in the OPAL-RT OP4510 real-time simulator, and the results are validated to confirm the effectiveness and robustness of the proposed grid-tied MLI.

This article offers a novel flux controlled floating memristor emulator based on second-generation current conveyor (CCII). The floating memristor is designed using two CCIIs, one resistor, and one PMOS transistor. The presented memristor emulator does not need external capacitance. The proposed designed circuit exhibits pinch hysteresis loops in voltage–current plane up to 2 GHz frequency. The performance of the circuit under consideration is evaluated using 180 nm CMOS technology parameter by the SPICE simulator. The circuit requires a DC power supply of ±1.2 V and exhibits a power consumption of 0.766 mW. Furthermore, the resilience of the planned circuit is assessed by examining process corner fluctuation, supply voltage variation, temperature variation, and transistor size variations. In addition, a Schmitt trigger circuit and high order filters based on designed memristor are used to confirm the operation of the proposed design at high and low frequency, respectively.

Transition metal dichalcogenide field-effect transistors (TMDFETs) as a replacement for conventional metal–oxide–semiconductor field-effect transistors (MOSFETs) have attracted the attention of researchers in recent years. The efficiency of these devices should be investigated in different aspects in digital systems. One of the important components of such systems is dynamic random-access memory (DRAM), which is used in most computers and many electronic systems as the main memory due to its small area and simple structure, compared to static memory (SRAM) cells. In this paper, a regular DRAM cell is designed based on TMDFET devices and its performance is compared with a similar cell in conventional MOSFET technology from various aspects, including DRAM-specific timing characteristics considering changes in design and environmental parameter variations using Monte Carlo simulations. The simulations have been carried out in HSPICE with 16 nm technology under fair conditions for different technologies, at room temperature with a 0.7-V power supply. The results show that the TMD-DRAM has 3.55×, 3.08×, and 2.23× faster bitline recovery, merge time, and sense time than Si-MOS-DRAM, respectively. The Si-MOS-DRAM, on the other hand, has 1.65× faster write time compared to TMD-DRAM. However, TMD-DRAM consumes overall higher power than Si-MOS-DRAM, and shows higher average read power variability with the σ/μ = 0.476. The TMD-DRAM also shows higher variability in the studied timing characteristics than Si-MOS-DRAM except merge and sense times.

In this paper, to analyze the tuning range (TR) of transistors, we introduced two streamlined modeling approaches that can precisely predict the extent and direction of the TR. The first approach, known as the average DC (I_d) method, employed a simplified circuit model to dissect transistor characteristics, enabling us to understand the general trajectory of the TR. The second approach involved the transient current Id (t_c) method, which offers a nuanced portrayal of the transistor's real-world performance. By analyzing the current fluctuations within the transistor during transient states, its tuning capabilities could be more accurately ascertained. Further, this paper presents several designs for ultra-wide-tuning-range complementary metal–oxide–semiconductor (CMOS) voltage-controlled oscillators (VCOs) that employ a novel two-mode current-starved delay cell, featuring a tunable transistor-based current source for coarse frequency adjustment operating in synergy with a varactor for precise tuning. Using the 65-nm CMOS process, three prototype VCOs (Designs 2/3/4) based on the new cell and targeting different numbers of phases and performance were fabricated, thoroughly characterized, and compared with their traditional inverter-based counterpart (Design 1). Design 1 featured an inverter-based four-phase structure, with an output frequency range of 3.14–9.82 GHz, i.e., a radio frequency (RF) TR of 103%, with phase noise (PN) ranging from 137.7 to 132.1 dBc/Hz at an offset of 100 MHz, figure of merit with tuning range and area (FoMTA) varying from 200.7 to 205.1 dBc/Hz, and area of 0.0036 mm². In contrast, Designs 2/3/4, based on the new delay cell, featured 8/3/4 phases, with output frequencies in the ranges of 1.14–9.17, 1.26–16.53, and 1.15–18.32 GHz, respectively, resulting in increased RF TRs of 155.8%, 171.7% and 176.4%, as well as PN at an offset of 100 MHz in the ranges of 142.1–138, 130.5–131.3, and 131.9–129.6 dBc/Hz, respectively. This yielded better FoMTAs in the ranges of 201.2–209.9, 205.3–217.9, and 194.1–209.9 dBc/Hz, thus allowing the VCOs to maintain consistent performance across the frequency band and occupy comparable or smaller silicon areas of 0.00425, 0.000972, and 0.00348 mm² in the same 65 nm technology. These designs showcase the versatility and efficiency of the two-mode current-starved delay architecture, which offers wide TRs, tiny areas, and competitive performance metrics for various applications in RF integrated circuits.

A novel multi-band pass negative group delay circuit has been designed and proposed. The circuit consists of three types of components: capacitance, inductance, and resistance. An n-order bandpass negative group delay circuit was analyzed and presented, and taking a three-frequency bandpass negative group delay circuit as an example, the influence of different component values on the circuit group delay and insertion loss was analyzed. The actual test results of this circuit are consistent with the simulation results, and it can achieve the function of a multi-bandpass circuit. In actual testing, the circuit frequencies with negative group delay are 49, 82, and 102 MHz, with corresponding group delay values of −2.177, −2.058, and −1.903 ns and corresponding insertion loss values of −5.810, −5.835, and −5.866 dB.

Addressing the sensitivity of permanent magnet synchronous motors to external disturbances, a novel sliding mode control (NSMC) strategy is proposed to suppress sliding mode jitter and enhance speed regulation performance. First, an advanced nonsingular fast terminal sliding mode (ANFTSM) surface and a new adaptive power rate reaching law (NAPRRL) were developed. A new switching function replaces the conventional sign function to enhance the system's disturbance immunity and dynamic response speed. Then, the system's anti-interference performance was further enhanced by introducing an improved novel sliding mode observer (INSMO) for feedback compensation of the aggregate disturbance. Finally, MATLAB/Simulink simulations and experimental validations demonstrate that the NSMC control strategy exhibits superior performance in both the start-up response and load disturbance phases, with enhanced dither resistance, rapid dynamic response, and disturbance suppression capabilities.