This paper introduces a novel three‐phase grid‐tied multilevel inverter (MLI) topology that employs a basic unit per phase, yielding a symmetrical configuration capable of generating five‐level output voltage and an asymmetrical configuration producing seven‐level and nine‐level output voltages. The generalization of the proposed MLI is presented in terms of the number of modules (M) and output levels (L). A comprehensive comparative analysis of the proposed MLI topology against existing configurations is presented for both symmetric and asymmetric cases. The switching devices in the MLI are controlled using the in‐phase disposition level shift PWM (IPD‐LSPWM) technique. The synchronization of the grid‐tied MLI is addressed by considering the uncertainties in grid and load parameters at the point of common coupling (PCC). To achieve synchronization, a PLL‐less grid voltage‐ modulated direct power control (GVM‐DPC) technique is implemented. To mitigate the delay associated with PLL, a GVM‐DPC based on the stationary reference frame (SRF) is applied. This paper also includes mathematical modelling of GVM‐DPC without PLL and the design of an LCL filter. A simulation model of a 15‐kVA, three‐phase, nine‐level grid‐tied MLI is developed in MATLAB/Simulink and tested under both steady‐state and dynamic conditions. The proposed controller's performance is evaluated under the load variations and sudden changes in available power from the distributed generator (DG). Robustness is tested under adverse conditions such as voltage sag/swell at the PCC. Furthermore, the system is implemented in the OPAL‐RT OP4510 real‐time simulator, and the results are validated to confirm the effectiveness and robustness of the proposed grid‐tied MLI.
{"title":"A PLL‐less grid‐tied three‐phase multilevel inverter with reduced device count and LCL filter","authors":"Rohit Kumar, Madhuri Avinash Chaudhari, Pradyumn Chaturvedi, Sharat Chandra Choube","doi":"10.1002/cta.4170","DOIUrl":"https://doi.org/10.1002/cta.4170","url":null,"abstract":"This paper introduces a novel three‐phase grid‐tied multilevel inverter (MLI) topology that employs a basic unit per phase, yielding a symmetrical configuration capable of generating five‐level output voltage and an asymmetrical configuration producing seven‐level and nine‐level output voltages. The generalization of the proposed MLI is presented in terms of the number of modules (<jats:italic>M</jats:italic>) and output levels (<jats:italic>L</jats:italic>). A comprehensive comparative analysis of the proposed MLI topology against existing configurations is presented for both symmetric and asymmetric cases. The switching devices in the MLI are controlled using the in‐phase disposition level shift PWM (IPD‐LSPWM) technique. The synchronization of the grid‐tied MLI is addressed by considering the uncertainties in grid and load parameters at the point of common coupling (PCC). To achieve synchronization, a PLL‐less grid voltage‐ modulated direct power control (GVM‐DPC) technique is implemented. To mitigate the delay associated with PLL, a GVM‐DPC based on the stationary reference frame (SRF) is applied. This paper also includes mathematical modelling of GVM‐DPC without PLL and the design of an LCL filter. A simulation model of a 15‐kVA, three‐phase, nine‐level grid‐tied MLI is developed in MATLAB/Simulink and tested under both steady‐state and dynamic conditions. The proposed controller's performance is evaluated under the load variations and sudden changes in available power from the distributed generator (DG). Robustness is tested under adverse conditions such as voltage sag/swell at the PCC. Furthermore, the system is implemented in the OPAL‐RT OP4510 real‐time simulator, and the results are validated to confirm the effectiveness and robustness of the proposed grid‐tied MLI.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yuqiao Xie, Tao Xu, Zhongyang Liu, Guoji Qiu, Dawei Bi, Zhiyuan Hu, Zhengxuan Zhang, Shichang Zou
This paper comprehensively perfects the sensitive node transient detection feedback latch (SNTDFL) technique, subsequently conceptualizes an ideal hardening structure for the pre‐amplification stage, and proposes a radiation hardened by design (RHBD) strategy to cope with the severe single‐event transient (SET) effects of high‐precision voltage comparators in a space radiation environment. Analysis and verification results show that the hardening strategy exhibits excellent SET hardening performance, which can not only detect extremely small transient voltage disturbances at sensitive nodes but also effectively resist transient current pulses of various intensities generated by SETs. Compared with an unhardened high‐precision comparator, the proposed one, hardened with a hybrid strategy of SNTDFL and triple modular redundancy (TMR) techniques, can greatly preserve the original electrical properties and remarkably improve the tolerance of SET with little overhead. In addition, the proposed high‐precision comparator significantly reduces static power consumption compared with the one hardened with the TMR technique alone and has a smaller area overhead.
本文全面完善了敏感节点瞬态检测反馈锁存器（SNTDFL）技术，随后构思了一种理想的前置放大级加固结构，并提出了一种辐射加固设计（RHBD）策略，以应对空间辐射环境下高精度电压比较器的严重单次瞬态（SET）效应。分析和验证结果表明，该加固策略具有出色的 SET 加固性能，不仅能检测敏感节点上极小的瞬态电压干扰，还能有效抵御 SET 产生的各种强度的瞬态电流脉冲。与未加固的高精度比较器相比，采用 SNTDFL 和三重模块冗余（TMR）技术混合策略加固的高精度比较器可以极大地保留原有的电气特性，并以很小的开销显著提高 SET 的耐受性。此外，与单独使用 TMR 技术加固的比较器相比，所提出的高精度比较器大大降低了静态功耗，而且面积开销更小。
{"title":"High‐precision single‐event transient hardened comparator with the sensitive node transient detection feedback latch technique","authors":"Yuqiao Xie, Tao Xu, Zhongyang Liu, Guoji Qiu, Dawei Bi, Zhiyuan Hu, Zhengxuan Zhang, Shichang Zou","doi":"10.1002/cta.4187","DOIUrl":"https://doi.org/10.1002/cta.4187","url":null,"abstract":"This paper comprehensively perfects the sensitive node transient detection feedback latch (SNTDFL) technique, subsequently conceptualizes an ideal hardening structure for the pre‐amplification stage, and proposes a radiation hardened by design (RHBD) strategy to cope with the severe single‐event transient (SET) effects of high‐precision voltage comparators in a space radiation environment. Analysis and verification results show that the hardening strategy exhibits excellent SET hardening performance, which can not only detect extremely small transient voltage disturbances at sensitive nodes but also effectively resist transient current pulses of various intensities generated by SETs. Compared with an unhardened high‐precision comparator, the proposed one, hardened with a hybrid strategy of SNTDFL and triple modular redundancy (TMR) techniques, can greatly preserve the original electrical properties and remarkably improve the tolerance of SET with little overhead. In addition, the proposed high‐precision comparator significantly reduces static power consumption compared with the one hardened with the TMR technique alone and has a smaller area overhead.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chaowei Yang, Yong Chen, Kai Cheng, Crovetti Paolo Stefano, Rui P. Martins, Pui‐In Mak
In this paper, to analyze the tuning range (TR) of transistors, we introduced two streamlined modeling approaches that can precisely predict the extent and direction of the TR. The first approach, known as the average DC (Id) method, employed a simplified circuit model to dissect transistor characteristics, enabling us to understand the general trajectory of the TR. The second approach involved the transient current Id (tc) method, which offers a nuanced portrayal of the transistor's real‐world performance. By analyzing the current fluctuations within the transistor during transient states, its tuning capabilities could be more accurately ascertained. Further, this paper presents several designs for ultra‐wide‐tuning‐range complementary metal–oxide–semiconductor (CMOS) voltage‐controlled oscillators (VCOs) that employ a novel two‐mode current‐starved delay cell, featuring a tunable transistor‐based current source for coarse frequency adjustment operating in synergy with a varactor for precise tuning. Using the 65‐nm CMOS process, three prototype VCOs (Designs 2/3/4) based on the new cell and targeting different numbers of phases and performance were fabricated, thoroughly characterized, and compared with their traditional inverter‐based counterpart (Design 1). Design 1 featured an inverter‐based four‐phase structure, with an output frequency range of 3.14–9.82 GHz, i.e., a radio frequency (RF) TR of 103%, with phase noise (PN) ranging from 137.7 to 132.1 dBc/Hz at an offset of 100 MHz, figure of merit with tuning range and area (FoMTA) varying from 200.7 to 205.1 dBc/Hz, and area of 0.0036 mm2. In contrast, Designs 2/3/4, based on the new delay cell, featured 8/3/4 phases, with output frequencies in the ranges of 1.14–9.17, 1.26–16.53, and 1.15–18.32 GHz, respectively, resulting in increased RF TRs of 155.8%, 171.7% and 176.4%, as well as PN at an offset of 100 MHz in the ranges of 142.1–138, 130.5–131.3, and 131.9–129.6 dBc/Hz, respectively. This yielded better FoMTAs in the ranges of 201.2–209.9, 205.3–217.9, and 194.1–209.9 dBc/Hz, thus allowing the VCOs to maintain consistent performance across the frequency band and occupy comparable or smaller silicon areas of 0.00425, 0.000972, and 0.00348 mm2 in the same 65 nm technology. These designs showcase the versatility and efficiency of the two‐mode current‐starved delay architecture, which offers wide TRs, tiny areas, and competitive performance metrics for various applications in RF integrated circuits.
{"title":"Area‐efficient ultra‐wide‐tuning‐range ring oscillators in 65‐nm complementary metal–oxide–semiconductor","authors":"Chaowei Yang, Yong Chen, Kai Cheng, Crovetti Paolo Stefano, Rui P. Martins, Pui‐In Mak","doi":"10.1002/cta.4195","DOIUrl":"https://doi.org/10.1002/cta.4195","url":null,"abstract":"In this paper, to analyze the tuning range (TR) of transistors, we introduced two streamlined modeling approaches that can precisely predict the extent and direction of the TR. The first approach, known as the average DC (I<jats:sub>d</jats:sub>) method, employed a simplified circuit model to dissect transistor characteristics, enabling us to understand the general trajectory of the TR. The second approach involved the transient current Id (t<jats:sub>c</jats:sub>) method, which offers a nuanced portrayal of the transistor's real‐world performance. By analyzing the current fluctuations within the transistor during transient states, its tuning capabilities could be more accurately ascertained. Further, this paper presents several designs for ultra‐wide‐tuning‐range complementary metal–oxide–semiconductor (CMOS) voltage‐controlled oscillators (VCOs) that employ a novel two‐mode current‐starved delay cell, featuring a tunable transistor‐based current source for coarse frequency adjustment operating in synergy with a varactor for precise tuning. Using the 65‐nm CMOS process, three prototype VCOs (Designs 2/3/4) based on the new cell and targeting different numbers of phases and performance were fabricated, thoroughly characterized, and compared with their traditional inverter‐based counterpart (Design 1). Design 1 featured an inverter‐based four‐phase structure, with an output frequency range of 3.14–9.82 GHz, i.e., a radio frequency (RF) TR of 103%, with phase noise (PN) ranging from 137.7 to 132.1 dBc/Hz at an offset of 100 MHz, figure of merit with tuning range and area (FoMTA) varying from 200.7 to 205.1 dBc/Hz, and area of 0.0036 mm<jats:sup>2</jats:sup>. In contrast, Designs 2/3/4, based on the new delay cell, featured 8/3/4 phases, with output frequencies in the ranges of 1.14–9.17, 1.26–16.53, and 1.15–18.32 GHz, respectively, resulting in increased RF TRs of 155.8%, 171.7% and 176.4%, as well as PN at an offset of 100 MHz in the ranges of 142.1–138, 130.5–131.3, and 131.9–129.6 dBc/Hz, respectively. This yielded better FoMTAs in the ranges of 201.2–209.9, 205.3–217.9, and 194.1–209.9 dBc/Hz, thus allowing the VCOs to maintain consistent performance across the frequency band and occupy comparable or smaller silicon areas of 0.00425, 0.000972, and 0.00348 mm<jats:sup>2</jats:sup> in the same 65 nm technology. These designs showcase the versatility and efficiency of the two‐mode current‐starved delay architecture, which offers wide TRs, tiny areas, and competitive performance metrics for various applications in RF integrated circuits.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article offers a novel flux controlled floating memristor emulator based on second‐generation current conveyor (CCII). The floating memristor is designed using two CCIIs, one resistor, and one PMOS transistor. The presented memristor emulator does not need external capacitance. The proposed designed circuit exhibits pinch hysteresis loops in voltage–current plane up to 2 GHz frequency. The performance of the circuit under consideration is evaluated using 180 nm CMOS technology parameter by the SPICE simulator. The circuit requires a DC power supply of ±1.2 V and exhibits a power consumption of 0.766 mW. Furthermore, the resilience of the planned circuit is assessed by examining process corner fluctuation, supply voltage variation, temperature variation, and transistor size variations. In addition, a Schmitt trigger circuit and high order filters based on designed memristor are used to confirm the operation of the proposed design at high and low frequency, respectively.
{"title":"Second generation current conveyor based capacitorless floating memristor emulator","authors":"Navnit Kumar, Manjeet Kumar, Neeta Pandey, Shahram Minaei","doi":"10.1002/cta.4175","DOIUrl":"https://doi.org/10.1002/cta.4175","url":null,"abstract":"This article offers a novel flux controlled floating memristor emulator based on second‐generation current conveyor (CCII). The floating memristor is designed using two CCIIs, one resistor, and one PMOS transistor. The presented memristor emulator does not need external capacitance. The proposed designed circuit exhibits pinch hysteresis loops in voltage–current plane up to 2 GHz frequency. The performance of the circuit under consideration is evaluated using 180 nm CMOS technology parameter by the SPICE simulator. The circuit requires a DC power supply of ±1.2 V and exhibits a power consumption of 0.766 mW. Furthermore, the resilience of the planned circuit is assessed by examining process corner fluctuation, supply voltage variation, temperature variation, and transistor size variations. In addition, a Schmitt trigger circuit and high order filters based on designed memristor are used to confirm the operation of the proposed design at high and low frequency, respectively.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Transition metal dichalcogenide field‐effect transistors (TMDFETs) as a replacement for conventional metal–oxide–semiconductor field‐effect transistors (MOSFETs) have attracted the attention of researchers in recent years. The efficiency of these devices should be investigated in different aspects in digital systems. One of the important components of such systems is dynamic random‐access memory (DRAM), which is used in most computers and many electronic systems as the main memory due to its small area and simple structure, compared to static memory (SRAM) cells. In this paper, a regular DRAM cell is designed based on TMDFET devices and its performance is compared with a similar cell in conventional MOSFET technology from various aspects, including DRAM‐specific timing characteristics considering changes in design and environmental parameter variations using Monte Carlo simulations. The simulations have been carried out in HSPICE with 16 nm technology under fair conditions for different technologies, at room temperature with a 0.7‐V power supply. The results show that the TMD‐DRAM has 3.55×, 3.08×, and 2.23× faster bitline recovery, merge time, and sense time than Si‐MOS‐DRAM, respectively. The Si‐MOS‐DRAM, on the other hand, has 1.65× faster write time compared to TMD‐DRAM. However, TMD‐DRAM consumes overall higher power than Si‐MOS‐DRAM, and shows higher average read power variability with the σ/μ = 0.476. The TMD‐DRAM also shows higher variability in the studied timing characteristics than Si‐MOS‐DRAM except merge and sense times.
{"title":"Transition metal dichalcogenide FET‐based dynamic random‐access memory","authors":"Mahdiye Raoofi, Morteza Gholipour","doi":"10.1002/cta.4173","DOIUrl":"https://doi.org/10.1002/cta.4173","url":null,"abstract":"Transition metal dichalcogenide field‐effect transistors (TMDFETs) as a replacement for conventional metal–oxide–semiconductor field‐effect transistors (MOSFETs) have attracted the attention of researchers in recent years. The efficiency of these devices should be investigated in different aspects in digital systems. One of the important components of such systems is dynamic random‐access memory (DRAM), which is used in most computers and many electronic systems as the main memory due to its small area and simple structure, compared to static memory (SRAM) cells. In this paper, a regular DRAM cell is designed based on TMDFET devices and its performance is compared with a similar cell in conventional MOSFET technology from various aspects, including DRAM‐specific timing characteristics considering changes in design and environmental parameter variations using Monte Carlo simulations. The simulations have been carried out in HSPICE with 16 nm technology under fair conditions for different technologies, at room temperature with a 0.7‐V power supply. The results show that the TMD‐DRAM has 3.55×, 3.08×, and 2.23× faster bitline recovery, merge time, and sense time than Si‐MOS‐DRAM, respectively. The Si‐MOS‐DRAM, on the other hand, has 1.65× faster write time compared to TMD‐DRAM. However, TMD‐DRAM consumes overall higher power than Si‐MOS‐DRAM, and shows higher average read power variability with the <jats:italic>σ</jats:italic>/<jats:italic>μ</jats:italic> = 0.476. The TMD‐DRAM also shows higher variability in the studied timing characteristics than Si‐MOS‐DRAM except merge and sense times.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SummaryThis article narrates a robust sensor‐less indirect rotor field‐oriented control (IRFOC) of a six‐phase asymmetrical induction motor (SPAIM) drive with an online estimation of parameters and reduction of common mode voltage (CMV). In comparison to the conventional IRFOC technique, the proposed IRFOC provides the least CMV using modified space vector modulation (SVM). To guarantee proper operation of IRFOC, accurate estimation of rotor time constant is mandatory; any mismatch in the actual and tuned value may lead to poor performance of the IRFOC algorithm. This problem will be further accelerated with encoder‐less control using model‐based estimators. In this manuscript, the problem of simultaneous estimation of speed and machine parameters is investigated, and a model reference adaptive system (MRAS) based speed estimator accompanied by online estimation of parameters is proposed to improve sturdiness against variation of parameters. A Simulink model of the proposed method is developed and a simulation study is carried out. To validate the simulation results, a scaled prototype model of The SPAIM rated for 2 HP, 200 V is developed and encoder‐less IRFOC for the SPAIM drives is implemented using an STM32F407VG controller board. The performance of the proposed observers is tested and verified for all the possible operating conditions and results are presented.
{"title":"A robust sensor‐less field‐oriented control of six‐phase induction motor drive with reduced common mode voltage","authors":"Krunal Shah, Rakesh Maurya","doi":"10.1002/cta.4208","DOIUrl":"https://doi.org/10.1002/cta.4208","url":null,"abstract":"SummaryThis article narrates a robust sensor‐less indirect rotor field‐oriented control (IRFOC) of a six‐phase asymmetrical induction motor (SPAIM) drive with an online estimation of parameters and reduction of common mode voltage (CMV). In comparison to the conventional IRFOC technique, the proposed IRFOC provides the least CMV using modified space vector modulation (SVM). To guarantee proper operation of IRFOC, accurate estimation of rotor time constant is mandatory; any mismatch in the actual and tuned value may lead to poor performance of the IRFOC algorithm. This problem will be further accelerated with encoder‐less control using model‐based estimators. In this manuscript, the problem of simultaneous estimation of speed and machine parameters is investigated, and a model reference adaptive system (MRAS) based speed estimator accompanied by online estimation of parameters is proposed to improve sturdiness against variation of parameters. A Simulink model of the proposed method is developed and a simulation study is carried out. To validate the simulation results, a scaled prototype model of The SPAIM rated for 2 HP, 200 V is developed and encoder‐less IRFOC for the SPAIM drives is implemented using an STM32F407VG controller board. The performance of the proposed observers is tested and verified for all the possible operating conditions and results are presented.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Analog integrated circuit sizing is a laborious process that requires many times of iteration with Spice simulations. Even by applying the method, it still requires iterations and test assignment of device values (and biasings) in each iteration until reaching a satisfactory sizing result. When facing a design of multiple‐stage circuits (such as multiple‐stage operational amplifier [Op Amp]), sizing becomes more challenging due to the requirement on pole‐zero placement in order to achieve a better high‐frequency performance. Simulation‐in‐the‐loop method has been the dominating means taken by a great many of existing circuit sizer, but they suffer from intolerable runtime while lacking the possibility of offering insight or design knowledge acquisition. On the other hand, behavioral‐level synthesis methods, although intuitive and fast, suffer from accuracy loss due to the adoption of simplified device models and significantly condensed design equations. However, a proper combination of these two types of methods could lead to a lucrative research territory, yet it demands a methodological development for efficient deployment in practice, namely, implementation easy, less runtime, and guaranteed sizing quality. In this paper, we propose a two‐step method that takes the advantage of behavioral synthesis (in the first step) that is capable of fast and broader coverage of design space then makes correction (in the second step) on sizing refining by Spice simulation. Due to the profiling knowledge acquired on the design space in the first step, it can avoid blindness of the optimization landscape that is faced by many simulation‐centric methods which could easily get trapped in local optima. Conducted experiments over eight three‐stage Op Amps with different compensation configurations, including nested Miller capacitor (NMC), NMC with feedforward path (NMCF), NMC with feedforward path and nulling resistor (NMCFNR), NMC with nulling resistor (NMCNR), double pole‐zero cancellation (DPZC), transconductance with capacitances feedback compensation (TCFC), impedance adapting compensation (IAC), active feedback frequency compensation (AFFC), have validated that the proposed method can successfully generate qualified sizing results, offering an opportunity to compare fairly what merit a specific compensation strategy could possibly have.
{"title":"A two‐step sizing method for multistage Op Amps based on behavioral initial sizing followed by Spice‐in‐the‐loop refining","authors":"Qixu Xie, Guoyong Shi","doi":"10.1002/cta.4182","DOIUrl":"https://doi.org/10.1002/cta.4182","url":null,"abstract":"Analog integrated circuit sizing is a laborious process that requires many times of iteration with Spice simulations. Even by applying the method, it still requires iterations and test assignment of device values (and biasings) in each iteration until reaching a satisfactory sizing result. When facing a design of multiple‐stage circuits (such as multiple‐stage operational amplifier [Op Amp]), sizing becomes more challenging due to the requirement on pole‐zero placement in order to achieve a better high‐frequency performance. Simulation‐in‐the‐loop method has been the dominating means taken by a great many of existing circuit sizer, but they suffer from intolerable runtime while lacking the possibility of offering insight or design knowledge acquisition. On the other hand, behavioral‐level synthesis methods, although intuitive and fast, suffer from accuracy loss due to the adoption of simplified device models and significantly condensed design equations. However, a proper combination of these two types of methods could lead to a lucrative research territory, yet it demands a methodological development for efficient deployment in practice, namely, implementation easy, less runtime, and guaranteed sizing quality. In this paper, we propose a <jats:italic>two‐step</jats:italic> method that takes the advantage of behavioral synthesis (in the first step) that is capable of fast and broader coverage of design space then makes correction (in the second step) on sizing refining by Spice simulation. Due to the profiling knowledge acquired on the design space in the first step, it can avoid blindness of the optimization landscape that is faced by many simulation‐centric methods which could easily get trapped in local optima. Conducted experiments over eight three‐stage Op Amps with different compensation configurations, including nested Miller capacitor (NMC), NMC with feedforward path (NMCF), NMC with feedforward path and nulling resistor (NMCFNR), NMC with nulling resistor (NMCNR), double pole‐zero cancellation (DPZC), transconductance with capacitances feedback compensation (TCFC), impedance adapting compensation (IAC), active feedback frequency compensation (AFFC), have validated that the proposed method can successfully generate qualified sizing results, offering an opportunity to compare fairly what merit a specific compensation strategy could possibly have.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The cascade converter system has been widely concerned along with the medium power operating conditions, and it is crucial to address the intricate interplay among individual modules to ensure stability of both the source and load subsystems. This paper analyzes the DC‐link voltage stability based on impedance matching and proposes a normalized sensitivity calculation method based on the control strategy, which prevents the complex products and matrix calculations of traditional methods. The three‐level boost (TLB) output impedance model is derived based on state‐space averaging for open‐loop and considering the double‐loop, and the full‐bridge LLC (FBLLC) input impedance model is derived based on the fundamental equivalent circuit. Then the effect of the double‐loop PI parameters on the output impedance of the TLB is analyzed in detail based on the normalized sensitivity and verified by the Bode plots. The experimental results of the 30 kW prototype indicate that the control parameters were varied by a factor of 10 compared to the theoretical control group. The most significant alteration was the modification of the kp_i, resulting in an 8.9% increase in the DC‐link voltage ripple, while the ki_v was modified, resulting in a 0.53% increase, indicating that the effects of the PI parameter are consistent with the normalized sensitivity results.
随着中等功率运行条件的出现，级联变流器系统受到了广泛关注，解决各个模块之间错综复杂的相互作用以确保源子系统和负载子系统的稳定性至关重要。本文分析了基于阻抗匹配的直流链电压稳定性，并提出了一种基于控制策略的归一化灵敏度计算方法，避免了传统方法中复杂的乘积和矩阵计算。基于开环的状态空间平均并考虑双环，推导出了三电平升压（TLB）输出阻抗模型；基于基本等效电路，推导出了全桥 LLC（FBLLC）输入阻抗模型。然后，根据归一化灵敏度详细分析了双环 PI 参数对 TLB 输出阻抗的影响，并通过 Bode 图进行了验证。30 千瓦原型机的实验结果表明，与理论控制组相比，控制参数变化了 10 倍。最明显的变化是对 kp_i 的修改，导致直流链电压纹波增加了 8.9%，而对 ki_v 的修改则导致纹波增加了 0.53%，这表明 PI 参数的影响与归一化灵敏度结果一致。
{"title":"DC‐link voltage stability analysis for three‐level boost + full‐bridge LLC cascaded converter using impedance modeling","authors":"Ruiqi Ma, Shuiyuan He, Chongshan Xie, Xinbo Liu, Jiepin Zhang, Yingtao Ma, Chengwei Kang, Lijun Diao","doi":"10.1002/cta.4188","DOIUrl":"https://doi.org/10.1002/cta.4188","url":null,"abstract":"The cascade converter system has been widely concerned along with the medium power operating conditions, and it is crucial to address the intricate interplay among individual modules to ensure stability of both the source and load subsystems. This paper analyzes the DC‐link voltage stability based on impedance matching and proposes a normalized sensitivity calculation method based on the control strategy, which prevents the complex products and matrix calculations of traditional methods. The three‐level boost (TLB) output impedance model is derived based on state‐space averaging for open‐loop and considering the double‐loop, and the full‐bridge LLC (FBLLC) input impedance model is derived based on the fundamental equivalent circuit. Then the effect of the double‐loop PI parameters on the output impedance of the TLB is analyzed in detail based on the normalized sensitivity and verified by the Bode plots. The experimental results of the 30 kW prototype indicate that the control parameters were varied by a factor of 10 compared to the theoretical control group. The most significant alteration was the modification of the <jats:italic>k</jats:italic><jats:sub><jats:italic>p_i</jats:italic></jats:sub>, resulting in an 8.9% increase in the DC‐link voltage ripple, while the <jats:italic>k</jats:italic><jats:sub><jats:italic>i_v</jats:italic></jats:sub> was modified, resulting in a 0.53% increase, indicating that the effects of the PI parameter are consistent with the normalized sensitivity results.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Niannan Chang, Aixia Yuan, Ying Wang, Junzheng Liu
A novel multi‐band pass negative group delay circuit has been designed and proposed. The circuit consists of three types of components: capacitance, inductance, and resistance. An n‐order bandpass negative group delay circuit was analyzed and presented, and taking a three‐frequency bandpass negative group delay circuit as an example, the influence of different component values on the circuit group delay and insertion loss was analyzed. The actual test results of this circuit are consistent with the simulation results, and it can achieve the function of a multi‐bandpass circuit. In actual testing, the circuit frequencies with negative group delay are 49, 82, and 102 MHz, with corresponding group delay values of −2.177, −2.058, and −1.903 ns and corresponding insertion loss values of −5.810, −5.835, and −5.866 dB.
{"title":"Multi‐band pass negative group delay circuit with low insertion loss","authors":"Niannan Chang, Aixia Yuan, Ying Wang, Junzheng Liu","doi":"10.1002/cta.4177","DOIUrl":"https://doi.org/10.1002/cta.4177","url":null,"abstract":"A novel multi‐band pass negative group delay circuit has been designed and proposed. The circuit consists of three types of components: capacitance, inductance, and resistance. An <jats:italic>n</jats:italic>‐order bandpass negative group delay circuit was analyzed and presented, and taking a three‐frequency bandpass negative group delay circuit as an example, the influence of different component values on the circuit group delay and insertion loss was analyzed. The actual test results of this circuit are consistent with the simulation results, and it can achieve the function of a multi‐bandpass circuit. In actual testing, the circuit frequencies with negative group delay are 49, 82, and 102 MHz, with corresponding group delay values of −2.177, −2.058, and −1.903 ns and corresponding insertion loss values of −5.810, −5.835, and −5.866 dB.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chengming Chen, Zhizhong Xie, Xuan Wang, Zhengling Lei, Chunxia Shangguan
Addressing the sensitivity of permanent magnet synchronous motors to external disturbances, a novel sliding mode control (NSMC) strategy is proposed to suppress sliding mode jitter and enhance speed regulation performance. First, an advanced nonsingular fast terminal sliding mode (ANFTSM) surface and a new adaptive power rate reaching law (NAPRRL) were developed. A new switching function replaces the conventional sign function to enhance the system's disturbance immunity and dynamic response speed. Then, the system's anti‐interference performance was further enhanced by introducing an improved novel sliding mode observer (INSMO) for feedback compensation of the aggregate disturbance. Finally, MATLAB/Simulink simulations and experimental validations demonstrate that the NSMC control strategy exhibits superior performance in both the start‐up response and load disturbance phases, with enhanced dither resistance, rapid dynamic response, and disturbance suppression capabilities.
{"title":"Sliding mode disturbance compensated speed control for PMSM based on an advanced reaching law","authors":"Chengming Chen, Zhizhong Xie, Xuan Wang, Zhengling Lei, Chunxia Shangguan","doi":"10.1002/cta.4185","DOIUrl":"https://doi.org/10.1002/cta.4185","url":null,"abstract":"Addressing the sensitivity of permanent magnet synchronous motors to external disturbances, a novel sliding mode control (NSMC) strategy is proposed to suppress sliding mode jitter and enhance speed regulation performance. First, an advanced nonsingular fast terminal sliding mode (ANFTSM) surface and a new adaptive power rate reaching law (NAPRRL) were developed. A new switching function replaces the conventional sign function to enhance the system's disturbance immunity and dynamic response speed. Then, the system's anti‐interference performance was further enhanced by introducing an improved novel sliding mode observer (INSMO) for feedback compensation of the aggregate disturbance. Finally, MATLAB/Simulink simulations and experimental validations demonstrate that the NSMC control strategy exhibits superior performance in both the start‐up response and load disturbance phases, with enhanced dither resistance, rapid dynamic response, and disturbance suppression capabilities.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：