Nanopore ion channels are a promising solution for certain molecular structure analyses. Large arrays of nanopore channels and their associated readout circuits are used in many molecular studies such as DNA sequencing. Readout circuits must meet challenging performance criteria such as low noise operation, low power consumption, in-channel digitization capability, and high linearity. Previously, sigma–delta modulators have been presented to address these criteria; however, their specifications show drifts with temperature. In this paper, an approach is presented to keep modulator performance constant with temperature variations. For this purpose, the sigma–delta modulator's feedforward and feedback branches are modified so that their gain coefficient remains constant over a certain temperature range. With large sensors arrays, solutions employing high bias currents in the feedback paths are not suitable due to power consumption limitations. Here, the design gives the possibility of switching low current levels in the feedback paths without affecting the ENOB. The proposed temperature compensation solution shows good performance when temperature is swept from 27°C to 100°C. Over the mentioned temperature range, the gain and bandwidth of the modulator show a change of less than 0.4%. It is further shown that for a 10 kHz input current signal with an amplitude of 600 pA, the ENOB and power consumption are 12.9 and 4.6 mW, respectively.
{"title":"Low noise, temperature-compensated, electrochemical cell sigma–delta current measurement readout circuit","authors":"Pegah Tahani, Mehdi Habibi, Sebastian Magierowski","doi":"10.1002/cta.4163","DOIUrl":"10.1002/cta.4163","url":null,"abstract":"<div>\u0000 \u0000 <p>Nanopore ion channels are a promising solution for certain molecular structure analyses. Large arrays of nanopore channels and their associated readout circuits are used in many molecular studies such as DNA sequencing. Readout circuits must meet challenging performance criteria such as low noise operation, low power consumption, in-channel digitization capability, and high linearity. Previously, sigma–delta modulators have been presented to address these criteria; however, their specifications show drifts with temperature. In this paper, an approach is presented to keep modulator performance constant with temperature variations. For this purpose, the sigma–delta modulator's feedforward and feedback branches are modified so that their gain coefficient remains constant over a certain temperature range. With large sensors arrays, solutions employing high bias currents in the feedback paths are not suitable due to power consumption limitations. Here, the design gives the possibility of switching low current levels in the feedback paths without affecting the ENOB. The proposed temperature compensation solution shows good performance when temperature is swept from 27°C to 100°C. Over the mentioned temperature range, the gain and bandwidth of the modulator show a change of less than 0.4%. It is further shown that for a 10 kHz input current signal with an amplitude of 600 pA, the ENOB and power consumption are 12.9 and 4.6 mW, respectively.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 3","pages":"1234-1252"},"PeriodicalIF":1.8,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141885374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dynamic vision sensor (DVS) imaging quality is significantly affected by pixel noise and temporal contrast (TC), which is inversely proportional to sensitivity. To reduce the noise event rate and improve sensitivity in bright‐light conditions in the DVS pixel circuit, this paper proposes improvements to the conventional DVS pixel circuit. The proposed DVS pixel circuit adopts stacked medium‐threshold transistors instead of a single high‐threshold transistor in the photoreceptor and introduces a threshold switching circuit. Compared with the conventional DVS pixel circuit, this design increases event threshold normalized by root mean square (RMS) noise voltage, reducing the dim‐light noise bandwidth. Additionally, it achieves higher sensitivity in bright‐light conditions compared with dim‐light conditions. The proposed DVS pixel circuit is implemented in a 110‐nm complementary metal‐oxide semiconductor (CMOS) process. Post‐simulation results show that, for photocurrents between 5 fA and 100 pA, the proposed DVS pixel circuit achieves a 35 Hz peak event rate at 15% TC, which is reduced to 3.1% of the conventional structure. For photocurrents exceeding 30 pA, the proposed structure can switch TC from 15% to 5%, maintaining a noise event rate below 0.1 Hz.
{"title":"An improved pixel circuit with low noise event rate and enhanced bright‐light sensitivity for dynamic vision sensor","authors":"Zhiyuan Gao, Ding Zhang, Xiaopei Shi, Yanghao He, Jiangtao Xu","doi":"10.1002/cta.4203","DOIUrl":"https://doi.org/10.1002/cta.4203","url":null,"abstract":"Dynamic vision sensor (DVS) imaging quality is significantly affected by pixel noise and temporal contrast (TC), which is inversely proportional to sensitivity. To reduce the noise event rate and improve sensitivity in bright‐light conditions in the DVS pixel circuit, this paper proposes improvements to the conventional DVS pixel circuit. The proposed DVS pixel circuit adopts stacked medium‐threshold transistors instead of a single high‐threshold transistor in the photoreceptor and introduces a threshold switching circuit. Compared with the conventional DVS pixel circuit, this design increases event threshold normalized by root mean square (RMS) noise voltage, reducing the dim‐light noise bandwidth. Additionally, it achieves higher sensitivity in bright‐light conditions compared with dim‐light conditions. The proposed DVS pixel circuit is implemented in a 110‐nm complementary metal‐oxide semiconductor (CMOS) process. Post‐simulation results show that, for photocurrents between 5 fA and 100 pA, the proposed DVS pixel circuit achieves a 35 Hz peak event rate at 15% TC, which is reduced to 3.1% of the conventional structure. For photocurrents exceeding 30 pA, the proposed structure can switch TC from 15% to 5%, maintaining a noise event rate below 0.1 Hz.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"214 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper explores the investigation of an inverse Class‐E amplifier featuring a series output filter across various switch‐off duty ratios D. Analysis of different duty ratios as a design parameter reveals their impact on peak switch voltage, output power capability, and maximum operating frequency. Notably, it is demonstrated that adjusting the D ratio affects these parameters, with specific emphasis on achieving a maximum normalized switch voltage lower than 2 and an output power capability exceeding 0.1 for D = 0.7. Furthermore, the paper considers both parasitic shunt capacitance and series inductor in the load network, a departure from previous works that solely focused on the series inductor. The proposed circuit is highlighted for its ease of implementation compared with conventional reactance compensation circuits employing parallel resonant circuits, which are challenging to form directly. An innovative approach is introduced to showcase the broadband performance of the inverse Class‐E amplifier. The measured drain efficiency and output power versus input power at 430 MHz are 82% and 45.3 dBm, respectively. A similar performance can be achieved within the frequency range of 380–600 MHz by proper tuning at saturated power. The measurement results demonstrate a maximum high power‐added efficiency (PAE) of 79% and drain efficiency of 82% within this frequency range, accompanied by a gain exceeding 12.0 dB and output power surpassing 44 dBm.
本文探讨了对具有串联输出滤波器的反向 E 类放大器在不同关断占空比 D 下的研究。将不同占空比作为设计参数进行分析，可以发现其对峰值开关电压、输出功率能力和最大工作频率的影响。值得注意的是，本文证明了调整 D 比对这些参数的影响，特别强调了在 D = 0.7 时实现低于 2 的最大归一化开关电压和超过 0.1 的输出功率能力。此外，本文还考虑了负载网络中的寄生并联电容和串联电感，这与之前仅关注串联电感的研究有所不同。与采用并联谐振电路的传统电抗补偿电路相比，本文提出的电路更易于实现，因为直接形成并联谐振电路具有挑战性。为展示反向 E 类放大器的宽带性能，介绍了一种创新方法。在 430 MHz 频率下，测得的漏极效率和输出功率与输入功率之比分别为 82% 和 45.3 dBm。通过在饱和功率下进行适当调谐，在 380-600 MHz 频率范围内也能实现类似的性能。测量结果表明，在这一频率范围内，功率附加效率（PAE）最高可达 79%，漏极效率最高可达 82%，增益超过 12.0 dB，输出功率超过 44 dBm。
{"title":"Inverse Class‐E power amplifier with broadband capability at different switch‐off duty ratio","authors":"Akram Sheikhi, Hossein Hemesi, Andrei Grebennikov","doi":"10.1002/cta.4184","DOIUrl":"https://doi.org/10.1002/cta.4184","url":null,"abstract":"The paper explores the investigation of an inverse Class‐E amplifier featuring a series output filter across various switch‐off duty ratios <jats:italic>D</jats:italic>. Analysis of different duty ratios as a design parameter reveals their impact on peak switch voltage, output power capability, and maximum operating frequency. Notably, it is demonstrated that adjusting the <jats:italic>D</jats:italic> ratio affects these parameters, with specific emphasis on achieving a maximum normalized switch voltage lower than 2 and an output power capability exceeding 0.1 for <jats:italic>D</jats:italic> = 0.7. Furthermore, the paper considers both parasitic shunt capacitance and series inductor in the load network, a departure from previous works that solely focused on the series inductor. The proposed circuit is highlighted for its ease of implementation compared with conventional reactance compensation circuits employing parallel resonant circuits, which are challenging to form directly. An innovative approach is introduced to showcase the broadband performance of the inverse Class‐E amplifier. The measured drain efficiency and output power versus input power at 430 MHz are 82% and 45.3 dBm, respectively. A similar performance can be achieved within the frequency range of 380–600 MHz by proper tuning at saturated power. The measurement results demonstrate a maximum high power‐added efficiency (PAE) of 79% and drain efficiency of 82% within this frequency range, accompanied by a gain exceeding 12.0 dB and output power surpassing 44 dBm.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"26 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a novel non‐isolated bidirectional dc‐dc converter (NBDC) is proposed. Compared with other topologies proposed recently, the proposed converter has the advantages of high voltage gain, wide voltage range, and common ground, which is suitable for the application of electric vehicles (EVs). The operating principle, steady‐state analysis, performance comparison, and the small signal modeling of the proposed converter are presented in detail. Finally, a 265‐W prototype is built to verify the feasibility of the proposed converter. The experimental results well confirm the corresponding theoretical analysis, and the prototype has a peak efficiency of 92.81% and 93.61% in step‐up mode and step‐down mode, respectively.
{"title":"A novel wide‐range voltage gain bidirectional DC‐DC converter for electric vehicles","authors":"Ziqiang Wen, Faqiang Wang","doi":"10.1002/cta.4191","DOIUrl":"https://doi.org/10.1002/cta.4191","url":null,"abstract":"In this paper, a novel non‐isolated bidirectional dc‐dc converter (NBDC) is proposed. Compared with other topologies proposed recently, the proposed converter has the advantages of high voltage gain, wide voltage range, and common ground, which is suitable for the application of electric vehicles (EVs). The operating principle, steady‐state analysis, performance comparison, and the small signal modeling of the proposed converter are presented in detail. Finally, a 265‐W prototype is built to verify the feasibility of the proposed converter. The experimental results well confirm the corresponding theoretical analysis, and the prototype has a peak efficiency of 92.81% and 93.61% in step‐up mode and step‐down mode, respectively.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"9 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SummaryThis paper describes a novel seven‐level (7L) inverter. The suggested topology offers a 7L output voltage and a threefold gain by using proper capacitor values. The suggested topology reduces the spike current induced by the capacitor by the use of a resonant inductor. The suggested inverter's performance under various loads and situations is compared with those found in existing literature. The simulation findings confirm the system's strong performance in terms of component count, control circuit simplicity, and possible cost reductions, while retaining similar or enhanced performance metrics as compared with the aforementioned topologies. A laboratory setup is used to validate the feasibility of the suggested topology and provide solid evidence of its effectiveness. Furthermore, discussions about the possible uses of this structure in energy conversion are conducted.
{"title":"A novel seven‐level inverter with high gain and reducing spike current capabilities","authors":"Ravi Anand, Rajib Kumar Mandal, Ankita Choudhary","doi":"10.1002/cta.4200","DOIUrl":"https://doi.org/10.1002/cta.4200","url":null,"abstract":"SummaryThis paper describes a novel seven‐level (7L) inverter. The suggested topology offers a 7L output voltage and a threefold gain by using proper capacitor values. The suggested topology reduces the spike current induced by the capacitor by the use of a resonant inductor. The suggested inverter's performance under various loads and situations is compared with those found in existing literature. The simulation findings confirm the system's strong performance in terms of component count, control circuit simplicity, and possible cost reductions, while retaining similar or enhanced performance metrics as compared with the aforementioned topologies. A laboratory setup is used to validate the feasibility of the suggested topology and provide solid evidence of its effectiveness. Furthermore, discussions about the possible uses of this structure in energy conversion are conducted.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"296 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A power tracking method based on improved variable‐step perturbation observation approach has been proposed in this paper. This method is aimed at addressing the detuning issues caused by capacitor parameter drift in MCR‐WPT systems based on S‐S compensation circuits. Compared with traditional tuning methods, the proposed method has fast response, high accuracy, low complexity, and less prone to over‐tracking. Firstly, a mathematical model of the system based on the detuning factor has been established. Secondly, the impact of different detuning conditions on the system at the initial resonant frequency has been studied. Thirdly, the response characteristics of the system to different frequencies under different detuning conditions have been studied. Fourthly, based on the above researches, an improved variable‐step perturbation observation method based on the single‐step power drop factor has been proposed. Finally, an experimental platform was constructed, and relevant experiments were conducted. Experimental results validate the effectiveness of power tracking under different detuning conditions, with the lowest transmission efficiency being 81.51%.
{"title":"Detuning analysis and power tracking of dual‐ended resonant circuit based on improved variable‐step perturbation observation for wireless power transfer system","authors":"Jiangui Li, Guangbin Luo, Longyang Wang, Qinghe Si, Yinchong Peng, Zheyuan Guo","doi":"10.1002/cta.4204","DOIUrl":"https://doi.org/10.1002/cta.4204","url":null,"abstract":"A power tracking method based on improved variable‐step perturbation observation approach has been proposed in this paper. This method is aimed at addressing the detuning issues caused by capacitor parameter drift in MCR‐WPT systems based on S‐S compensation circuits. Compared with traditional tuning methods, the proposed method has fast response, high accuracy, low complexity, and less prone to over‐tracking. Firstly, a mathematical model of the system based on the detuning factor has been established. Secondly, the impact of different detuning conditions on the system at the initial resonant frequency has been studied. Thirdly, the response characteristics of the system to different frequencies under different detuning conditions have been studied. Fourthly, based on the above researches, an improved variable‐step perturbation observation method based on the single‐step power drop factor has been proposed. Finally, an experimental platform was constructed, and relevant experiments were conducted. Experimental results validate the effectiveness of power tracking under different detuning conditions, with the lowest transmission efficiency being 81.51%.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"29 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The successful implementation of artificial intelligence algorithms depends on the capacity to execute numerous repeated operations, which, in turn, requires systems with high data throughput. Although emerging computing‐in‐memory (CIM) eliminates the need for frequent data transfer between the memory and processing blocks and enables parallel activation of multiple rows, the traditional structure, where each row has only one identical input value, significantly limits its further application. To solve this problem, this study proposes a dual‐SRAM CIM architecture in which two SRAM arrays are coupled such that all operands are different, thus rendering the use of CIM considerably more flexible. The proposed dual‐SRAM array was implemented through a 55‐nm process, essentially delivering a frequency of 361 MHz for a 1.2‐V supply and energy efficiency of 161 TOPS/W at 0.9 V supply.
{"title":"High‐throughput in‐memory bitwise computing based on a coupled dual‐SRAM array with independent operands","authors":"Hongbiao Wu, Zhiting Lin, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng","doi":"10.1002/cta.4192","DOIUrl":"https://doi.org/10.1002/cta.4192","url":null,"abstract":"The successful implementation of artificial intelligence algorithms depends on the capacity to execute numerous repeated operations, which, in turn, requires systems with high data throughput. Although emerging computing‐in‐memory (CIM) eliminates the need for frequent data transfer between the memory and processing blocks and enables parallel activation of multiple rows, the traditional structure, where each row has only one identical input value, significantly limits its further application. To solve this problem, this study proposes a dual‐SRAM CIM architecture in which two SRAM arrays are coupled such that all operands are different, thus rendering the use of CIM considerably more flexible. The proposed dual‐SRAM array was implemented through a 55‐nm process, essentially delivering a frequency of 361 MHz for a 1.2‐V supply and energy efficiency of 161 TOPS/W at 0.9 V supply.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"32 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To improve the torque control accuracy of an open-winding permanent magnet synchronous motor with common DC bus, this paper studies a complex vector proportional–integral (CVPI) controller with the help of a proportional–integral (PI) controller to solve the problem of torque ripple caused by the current harmonics caused by the back electromotive force of the motor and the nonlinearity of the inverter. The controller has a higher gain at the center frequency and can realize the tracking of the alternating current (AC) quantity without static error. Therefore, it is used for the tracking control of current harmonics. According to the different characteristics of the dq0-axis, complex j is realized by orthogonal characteristics and all-pass filter in the dq-axis and 0-axis, respectively. At the same time, with the help of Ansys, Simplorer, and Matlab/Simulink tools, the co-simulation platform for an open-winding motor is established, and the motor parameters are optimized. The simulation and experimental results show that the control strategy based on CVPI has stronger harmonic suppression ability, smaller torque ripple, and better dynamic performance than proportional-resonance (PR) control.
{"title":"Torque ripple suppression of open-winding permanent magnet synchronous motor with common DC bus based on field circuit coupling method","authors":"Shirui Xie, Wendong Zhang, Xinpeng Feng, Wei Zhang, Pingping Gu, Ziqi Lei, Chaohui Zhao","doi":"10.1002/cta.4159","DOIUrl":"10.1002/cta.4159","url":null,"abstract":"<p>To improve the torque control accuracy of an open-winding permanent magnet synchronous motor with common DC bus, this paper studies a complex vector proportional–integral (CVPI) controller with the help of a proportional–integral (PI) controller to solve the problem of torque ripple caused by the current harmonics caused by the back electromotive force of the motor and the nonlinearity of the inverter. The controller has a higher gain at the center frequency and can realize the tracking of the alternating current (AC) quantity without static error. Therefore, it is used for the tracking control of current harmonics. According to the different characteristics of the <i>dq0</i>-axis, complex <i>j</i> is realized by orthogonal characteristics and all-pass filter in the <i>dq</i>-axis and <i>0</i>-axis, respectively. At the same time, with the help of Ansys, Simplorer, and Matlab/Simulink tools, the co-simulation platform for an open-winding motor is established, and the motor parameters are optimized. The simulation and experimental results show that the control strategy based on CVPI has stronger harmonic suppression ability, smaller torque ripple, and better dynamic performance than proportional-resonance (PR) control.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 3","pages":"1630-1648"},"PeriodicalIF":1.8,"publicationDate":"2024-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ashwin K, Nakul Narayanan K, L Umanand, Subba Reddy B
This paper introduces a resonant switched capacitor converter (RSCC) topology that enhances the operational efficiency by utilizing devices with reduced ratings. The RSCC eliminates bulky magnetic elements, yielding increased power density, modular structure, and compact size compared with switched inductor topologies. Significantly, all the switched capacitors in the proposed converter and approximately 50% of the switching power devices are explicitly rated for the input voltage enabling its use for high‐power applications. A compact inductor is utilized for resonant operation, and the switching frequency of the converter is significantly reduced leading to reduced switching losses and improved efficiency. Zero current turn‐ON and turn‐OFF of the switching devices is achieved. Elimination of load‐side bulky capacitor using inherent output voltage ripple reduction is achieved by aligning the switching phases of the converter such that individual capacitor voltage ripple gets cancelled out. The work extensively covers the analysis of the converter in steady‐state and the effect of non‐idealities during the resonant operation. Further, a detailed design of the topology with a discussion on component selection is presented. The operation of the proposed converter is systematically analyzed through a series of simulation results generated, and the converter is further validated by developing an experimental prototype at a power of 200 W with an efficiency of 95.83%.
{"title":"Design and analysis of a non‐ideal resonant switched capacitor DC‐DC converter with reduced device ratings","authors":"Ashwin K, Nakul Narayanan K, L Umanand, Subba Reddy B","doi":"10.1002/cta.4167","DOIUrl":"https://doi.org/10.1002/cta.4167","url":null,"abstract":"This paper introduces a resonant switched capacitor converter (RSCC) topology that enhances the operational efficiency by utilizing devices with reduced ratings. The RSCC eliminates bulky magnetic elements, yielding increased power density, modular structure, and compact size compared with switched inductor topologies. Significantly, all the switched capacitors in the proposed converter and approximately 50% of the switching power devices are explicitly rated for the input voltage enabling its use for high‐power applications. A compact inductor is utilized for resonant operation, and the switching frequency of the converter is significantly reduced leading to reduced switching losses and improved efficiency. Zero current turn‐ON and turn‐OFF of the switching devices is achieved. Elimination of load‐side bulky capacitor using inherent output voltage ripple reduction is achieved by aligning the switching phases of the converter such that individual capacitor voltage ripple gets cancelled out. The work extensively covers the analysis of the converter in steady‐state and the effect of non‐idealities during the resonant operation. Further, a detailed design of the topology with a discussion on component selection is presented. The operation of the proposed converter is systematically analyzed through a series of simulation results generated, and the converter is further validated by developing an experimental prototype at a power of 200 W with an efficiency of 95.83%.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"110 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yuqiao Xie, Tao Xu, Zhongyang Liu, Guoji Qiu, Dawei Bi, Zhiyuan Hu, Zhengxuan Zhang, Shichang Zou
This paper comprehensively perfects the sensitive node transient detection feedback latch (SNTDFL) technique, subsequently conceptualizes an ideal hardening structure for the pre-amplification stage, and proposes a radiation hardened by design (RHBD) strategy to cope with the severe single-event transient (SET) effects of high-precision voltage comparators in a space radiation environment. Analysis and verification results show that the hardening strategy exhibits excellent SET hardening performance, which can not only detect extremely small transient voltage disturbances at sensitive nodes but also effectively resist transient current pulses of various intensities generated by SETs. Compared with an unhardened high-precision comparator, the proposed one, hardened with a hybrid strategy of SNTDFL and triple modular redundancy (TMR) techniques, can greatly preserve the original electrical properties and remarkably improve the tolerance of SET with little overhead. In addition, the proposed high-precision comparator significantly reduces static power consumption compared with the one hardened with the TMR technique alone and has a smaller area overhead.
本文全面完善了敏感节点瞬态检测反馈锁存器（SNTDFL）技术，随后构思了一种理想的前置放大级加固结构，并提出了一种辐射加固设计（RHBD）策略，以应对空间辐射环境下高精度电压比较器的严重单次瞬态（SET）效应。分析和验证结果表明，该加固策略具有出色的 SET 加固性能，不仅能检测敏感节点上极小的瞬态电压干扰，还能有效抵御 SET 产生的各种强度的瞬态电流脉冲。与未加固的高精度比较器相比，采用 SNTDFL 和三重模块冗余（TMR）技术混合策略加固的高精度比较器可以极大地保留原有的电气特性，并以很小的开销显著提高 SET 的耐受性。此外，与单独使用 TMR 技术加固的比较器相比，所提出的高精度比较器大大降低了静态功耗，而且面积开销更小。
{"title":"High-precision single-event transient hardened comparator with the sensitive node transient detection feedback latch technique","authors":"Yuqiao Xie, Tao Xu, Zhongyang Liu, Guoji Qiu, Dawei Bi, Zhiyuan Hu, Zhengxuan Zhang, Shichang Zou","doi":"10.1002/cta.4187","DOIUrl":"10.1002/cta.4187","url":null,"abstract":"<p>This paper comprehensively perfects the sensitive node transient detection feedback latch (SNTDFL) technique, subsequently conceptualizes an ideal hardening structure for the pre-amplification stage, and proposes a radiation hardened by design (RHBD) strategy to cope with the severe single-event transient (SET) effects of high-precision voltage comparators in a space radiation environment. Analysis and verification results show that the hardening strategy exhibits excellent SET hardening performance, which can not only detect extremely small transient voltage disturbances at sensitive nodes but also effectively resist transient current pulses of various intensities generated by SETs. Compared with an unhardened high-precision comparator, the proposed one, hardened with a hybrid strategy of SNTDFL and triple modular redundancy (TMR) techniques, can greatly preserve the original electrical properties and remarkably improve the tolerance of SET with little overhead. In addition, the proposed high-precision comparator significantly reduces static power consumption compared with the one hardened with the TMR technique alone and has a smaller area overhead.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 3","pages":"1720-1733"},"PeriodicalIF":1.8,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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