Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357871
Qingyu Lin, Wei Miao, N. Wu
The paper proposes a high-speed target tracking CMOS image sensor. The target tracking CMOS image sensor consists of an image sensor array, row-parallel processors, a controller and a SRAM. It implements two novel concise algorithms that composed of efficient operations: such as collision detection, separation detection and position extraction. A 64 times 64 pixel array high-speed target tracking CMOS image sensor chip was implemented in using 0.35 mum 2P4M CMOS process. An N-well/P-sub SAB diode without salicide is used as photodiode in the image sensor. The chip size is 4.5 mm times 2.5 mm. The measured results demonstrated that the chip can perform target tracking at the rate of 1000 fps with more functionality and less area than the reported digital chips. The chip power consumption is 30 mW at the main clock of 20 MHz.
提出了一种高速目标跟踪CMOS图像传感器。目标跟踪CMOS图像传感器由图像传感器阵列、行并行处理器、控制器和SRAM组成。它实现了碰撞检测、分离检测和位置提取两种新颖简洁的算法。采用0.35 μ m 2P4M CMOS工艺，实现了64 × 64像素阵列高速目标跟踪CMOS图像传感器芯片。在图像传感器中，采用不含水杨酸的n阱/ p阱SAB二极管作为光电二极管。芯片尺寸为4.5 mm × 2.5 mm。测量结果表明，该芯片可以以1000 fps的速度进行目标跟踪，并且比现有的数字芯片具有更大的功能和更小的面积。芯片功耗为30mw，主频为20mhz。
{"title":"A High-Speed Target Tracking CMOS Image Sensor","authors":"Qingyu Lin, Wei Miao, N. Wu","doi":"10.1109/ASSCC.2006.357871","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357871","url":null,"abstract":"The paper proposes a high-speed target tracking CMOS image sensor. The target tracking CMOS image sensor consists of an image sensor array, row-parallel processors, a controller and a SRAM. It implements two novel concise algorithms that composed of efficient operations: such as collision detection, separation detection and position extraction. A 64 times 64 pixel array high-speed target tracking CMOS image sensor chip was implemented in using 0.35 mum 2P4M CMOS process. An N-well/P-sub SAB diode without salicide is used as photodiode in the image sensor. The chip size is 4.5 mm times 2.5 mm. The measured results demonstrated that the chip can perform target tracking at the rate of 1000 fps with more functionality and less area than the reported digital chips. The chip power consumption is 30 mW at the main clock of 20 MHz.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127244660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357859
Tsung-Hsien Lin, Chao-Ching Chi
This paper presents a 50% duty-cycle correction (DCC) circuit. The proposed DCC circuit consists of a clock generator and a delay detector. The clock generator is edge-triggered by the input and produces an output signal whose pulse width is controlled by the delay detector to half of the input signal period. Meanwhile, the input phase information is preserved owing to the edge-trigger nature. The circuit is implemented in a TSMC 0.35-μm CMOS process. To evaluate the output duty-cycle accuracy, a single-sideband mixing measurement technique is adopted. This circuit operates from 70 MHz to 490 MHz, and accommodates input duty cycles ranging from 10% to 90%. The output signal is corrected to 50% ± 2%. Operated from a 3.3-V supply, the circuit dissipates 8 mA at 490 MHz.
{"title":"A 70-490 MHz 50% Duty-Cycle Correction Circuit in 0.3-μm CMOS","authors":"Tsung-Hsien Lin, Chao-Ching Chi","doi":"10.1109/ASSCC.2006.357859","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357859","url":null,"abstract":"This paper presents a 50% duty-cycle correction (DCC) circuit. The proposed DCC circuit consists of a clock generator and a delay detector. The clock generator is edge-triggered by the input and produces an output signal whose pulse width is controlled by the delay detector to half of the input signal period. Meanwhile, the input phase information is preserved owing to the edge-trigger nature. The circuit is implemented in a TSMC 0.35-μm CMOS process. To evaluate the output duty-cycle accuracy, a single-sideband mixing measurement technique is adopted. This circuit operates from 70 MHz to 490 MHz, and accommodates input duty cycles ranging from 10% to 90%. The output signal is corrected to 50% ± 2%. Operated from a 3.3-V supply, the circuit dissipates 8 mA at 490 MHz.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132878346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357866
Yang Kun, Zhang Chun, Du Guoze, Xie Jiangxiang, W. Zhihua
A single chip decoder SOC for H.264 baseline profile, called OR264 (OR1K based H264 decoder), is presented in this paper. The chip has mixed hardware/software architecture to combine performance and flexibility. It is partitioned that the hardware is used to boost the performance and efficiency of key operations in H.264 decoder while the software is used to control the decoding flow and to synchronize the hardware modules. All hardware units operate in parallel. The hardware can decode a MB in 851 clock cycles under ideal condition. The chip is fabricated using UMC 0.18-mum 6-layers metal CMOS process. It contains 1.5 M transistors and 176k bits embedded SRAM. The die size is 4.8 mm x 4.8 mm and the critical path is 10 ns.
本文提出了一种用于H.264基线配置的单片解码器SOC，称为OR264(基于OR1K的H264解码器)。该芯片采用混合硬件/软件架构，将性能和灵活性结合起来。硬件部分主要用于提高H.264解码器关键操作的性能和效率，软件部分主要用于控制解码流程和实现各硬件模块的同步。所有硬件单元并行运行。在理想情况下，硬件可以在851个时钟周期内解码一个MB。该芯片采用UMC 0.18-mum 6层金属CMOS工艺制造。它包含1.5 M晶体管和176k位嵌入式SRAM。模具尺寸为4.8 mm × 4.8 mm，关键路径为10ns。
{"title":"A Hardware-Software Co-design for H.264/AVG Decoder","authors":"Yang Kun, Zhang Chun, Du Guoze, Xie Jiangxiang, W. Zhihua","doi":"10.1109/ASSCC.2006.357866","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357866","url":null,"abstract":"A single chip decoder SOC for H.264 baseline profile, called OR264 (OR1K based H264 decoder), is presented in this paper. The chip has mixed hardware/software architecture to combine performance and flexibility. It is partitioned that the hardware is used to boost the performance and efficiency of key operations in H.264 decoder while the software is used to control the decoding flow and to synchronize the hardware modules. All hardware units operate in parallel. The hardware can decode a MB in 851 clock cycles under ideal condition. The chip is fabricated using UMC 0.18-mum 6-layers metal CMOS process. It contains 1.5 M transistors and 176k bits embedded SRAM. The die size is 4.8 mm x 4.8 mm and the critical path is 10 ns.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132906771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357940
Yong Liu, Hakho Lee, R. Westervelt, D. Ham
There are burgeoning efforts to use CMOS ICs for biotechnology. This paper reviews one such effort, development of a CMOS/Microfluidic hybrid system for magnetic manipulation of biological cells originally reported by the authors in H. Lee et al. (2005, 2006). Programmable magnetic field patterns produced by a CMOS microcoil array IC efficiently manipulate individual cells (tagged by magnetic beads) inside a microfluidic system fabricated on top of the IC.
{"title":"CMOS Meets Bio","authors":"Yong Liu, Hakho Lee, R. Westervelt, D. Ham","doi":"10.1109/ASSCC.2006.357940","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357940","url":null,"abstract":"There are burgeoning efforts to use CMOS ICs for biotechnology. This paper reviews one such effort, development of a CMOS/Microfluidic hybrid system for magnetic manipulation of biological cells originally reported by the authors in H. Lee et al. (2005, 2006). Programmable magnetic field patterns produced by a CMOS microcoil array IC efficiently manipulate individual cells (tagged by magnetic beads) inside a microfluidic system fabricated on top of the IC.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133749656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357898
R.D. Singh, Kyung-Wan Yu
A biasing scheme that improves the linearity of linear mode power amplifiers (PA) is presented. This technique employs adding feedback to a current mirror bias to enhance the linearity of the amplifier by compensating the nonlinear input capacitance of the core transistor. The technique is verified with simulations and implemented in a prototype 2.4 GHz PA for WLAN application. The PA is fabricated in a 0.35-mum CMOS and achieves a small-signal gain of 25.4 dB, output P1dB of 25.1 dBm, and a power-added efficiency (PAE) of 40%.
提出了一种提高线性型功率放大器线性度的偏置方案。该技术采用在电流反射镜偏置上增加反馈，通过补偿核心晶体管的非线性输入电容来增强放大器的线性度。通过仿真验证了该技术，并在一个用于WLAN应用的2.4 GHz PA样机中实现了该技术。该放大器采用0.35 μ m CMOS制造，小信号增益为25.4 dB，输出P1dB为25.1 dBm，功率附加效率(PAE)为40%。
{"title":"A Linear Mode CMOS Power Amplifier with Self-Linearizing Bias","authors":"R.D. Singh, Kyung-Wan Yu","doi":"10.1109/ASSCC.2006.357898","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357898","url":null,"abstract":"A biasing scheme that improves the linearity of linear mode power amplifiers (PA) is presented. This technique employs adding feedback to a current mirror bias to enhance the linearity of the amplifier by compensating the nonlinear input capacitance of the core transistor. The technique is verified with simulations and implemented in a prototype 2.4 GHz PA for WLAN application. The PA is fabricated in a 0.35-mum CMOS and achieves a small-signal gain of 25.4 dB, output P1dB of 25.1 dBm, and a power-added efficiency (PAE) of 40%.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123243757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357881
M. Motoyoshi, Minoru Fujishima
A harmonic injection-locked divider (HILD) is effective for realizing a low-power phase-locked loop (PLL) circuit because the high-frequency output of a voltage-controlled oscillator (VCO) is down-converted into a low-frequency signal instantaneously. Conventional resonator-based HILDs, however, occupy a large chip area and exhibit a narrow locking range because either an LC or short-stub resonator is required. Ring-oscillator-based HILDs, on the other hand, operate at a relatively low frequency, again with a narrow locking range. In this study, a new HILD based on three-phase harmonic injection locking is proposed, which realizes a small chip area, a low power consumption, and a wide locking range. As a result of fabrication with 0.18 μm CMOS, a divide-by-three HILD is realized with a power consumption of 43 μW, a maximum operating frequency of 6 GHz, and a locking range of 80% at a supply voltage of 0.7 V. The core size is 10.8 μm x 10.5 μm.
{"title":"43μW 6GHz CMOS Divide-by-3 Frequency Divider Based on Three-Phase Harmonic Injection Locking","authors":"M. Motoyoshi, Minoru Fujishima","doi":"10.1109/ASSCC.2006.357881","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357881","url":null,"abstract":"A harmonic injection-locked divider (HILD) is effective for realizing a low-power phase-locked loop (PLL) circuit because the high-frequency output of a voltage-controlled oscillator (VCO) is down-converted into a low-frequency signal instantaneously. Conventional resonator-based HILDs, however, occupy a large chip area and exhibit a narrow locking range because either an LC or short-stub resonator is required. Ring-oscillator-based HILDs, on the other hand, operate at a relatively low frequency, again with a narrow locking range. In this study, a new HILD based on three-phase harmonic injection locking is proposed, which realizes a small chip area, a low power consumption, and a wide locking range. As a result of fabrication with 0.18 μm CMOS, a divide-by-three HILD is realized with a power consumption of 43 μW, a maximum operating frequency of 6 GHz, and a locking range of 80% at a supply voltage of 0.7 V. The core size is 10.8 μm x 10.5 μm.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129248910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357843
A. Leon, D. Sheahan
Throughput computing represents a new paradigm in processor design focusing on maximizing overall throughput of commercial workloads while addressing increasing demands for improved power and cooling in today's data centers. The first generation of "Niagara" SPARC processors implements a power-efficient chip multithreading (CMT) architecture, which combines eight 4-threaded 64 b cores, a high bandwidth interconnect crossbar, a shared 3 MB L2 Cache and four double-width DDR2 DRAM interfaces. Implemented in 90 nm CMOS technology, the 378 mm2 die consumes only 63 W at 1.2 GHz. The UltraSPARC Tl based systems are oriented to a wide variety of applications, including WebServers, data and application servers, Java applications, search, streaming video and Telco applications.
{"title":"The U1traSPARC T1: A Power-Efficient High-Throughput 32-Thread SPARC Processor","authors":"A. Leon, D. Sheahan","doi":"10.1109/ASSCC.2006.357843","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357843","url":null,"abstract":"Throughput computing represents a new paradigm in processor design focusing on maximizing overall throughput of commercial workloads while addressing increasing demands for improved power and cooling in today's data centers. The first generation of \"Niagara\" SPARC processors implements a power-efficient chip multithreading (CMT) architecture, which combines eight 4-threaded 64 b cores, a high bandwidth interconnect crossbar, a shared 3 MB L2 Cache and four double-width DDR2 DRAM interfaces. Implemented in 90 nm CMOS technology, the 378 mm2 die consumes only 63 W at 1.2 GHz. The UltraSPARC Tl based systems are oriented to a wide variety of applications, including WebServers, data and application servers, Java applications, search, streaming video and Telco applications.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125349981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357879
Chih-Chang Lee, Tzu-Yi Yang
We propose a common-mode variable voltage (CMW) method to improve the bandwidth of low pass filter for ultra-wideband (UWB) transmitter. It is based on leap-frog structure to design a 250 MHz 8th -order GM-C Chebyshev low pass filter. In the analytic results, tuning the common-mode reference voltage (VCM) of common-mode feedback circuits of transconductor, the cutoff frequency of filter can be calibrated to overcome the process variation and temperature dependencies. This approach can effectively reduce the chip size and do not need excess circuits. The filter combines a resistor network and 4times13 decoder to program the gain of filter and is implemented in a CMOS 0.18 mum process and power dissipation is 18 mW under 1.8 V power supply. Measurement results show that the filter can be reformed 50% bandwidth and the gain can be programmed from -14 dB to -38 dB with 2 dB step. The attenuation at 285 MHz and 330 MHz is 16 dB and 32 dB, respectively, and the total harmonic distortion (THD) of programmable gain filter is -37 dBc for 1Vpp differential input signal at 150 MHz.
{"title":"A Tuning Technique for Bandwidth of Programmable Gain Filter","authors":"Chih-Chang Lee, Tzu-Yi Yang","doi":"10.1109/ASSCC.2006.357879","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357879","url":null,"abstract":"We propose a common-mode variable voltage (CMW) method to improve the bandwidth of low pass filter for ultra-wideband (UWB) transmitter. It is based on leap-frog structure to design a 250 MHz 8th -order GM-C Chebyshev low pass filter. In the analytic results, tuning the common-mode reference voltage (VCM) of common-mode feedback circuits of transconductor, the cutoff frequency of filter can be calibrated to overcome the process variation and temperature dependencies. This approach can effectively reduce the chip size and do not need excess circuits. The filter combines a resistor network and 4times13 decoder to program the gain of filter and is implemented in a CMOS 0.18 mum process and power dissipation is 18 mW under 1.8 V power supply. Measurement results show that the filter can be reformed 50% bandwidth and the gain can be programmed from -14 dB to -38 dB with 2 dB step. The attenuation at 285 MHz and 330 MHz is 16 dB and 32 dB, respectively, and the total harmonic distortion (THD) of programmable gain filter is -37 dBc for 1Vpp differential input signal at 150 MHz.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125354011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357884
I. Lai, Y. Kambayashi, M. Fujishima
A cascade CMOS mixer is fabricated to exploit the unlicensed band around 60 GHz. This topology avoids the need for area-consuming power combining and uses simple matching with slow-wave transmission lines (SWTL). SWTL has a higher quality factor and allows area reduction. The circuit is fabricated in standard digital 90-nm CMOS and has a radio frequency (RF) return-loss more than 10 dB between 46 GHz and 64 GHz. At RF of 60 GHz, intermediate frequency (IF) of 4 GHz and local oscillator (LO) power of 1.5 dBm, the conversion loss is 1.2 dB and an input-referred 1-dB compression point of 0.5 dBm was measured. The length reduction of the transmission lines achieved is 47% and the resulting chip occupies an area of 0.61 mm x 0.80 mm with comparable performance to other works.
制作了级联CMOS混频器来利用60 GHz左右的未授权频段。这种拓扑结构避免了占用面积的功率组合，并与慢波传输线(SWTL)进行简单匹配。SWTL具有更高的质量因子，并允许缩小面积。该电路采用标准的数字90纳米CMOS制造，在46 GHz和64 GHz之间的射频(RF)回波损耗大于10 dB。在RF为60 GHz，中频为4 GHz，本振功率为1.5 dBm时，转换损耗为1.2 dB，测量到输入参考1 dB压缩点为0.5 dBm。传输线长度减少了47%，芯片面积为0.61 mm x 0.80 mm，性能与其他产品相当。
{"title":"60-GHz CMOS Down-Conversion Mixer with Slow-Wave Matching Transmission Lines","authors":"I. Lai, Y. Kambayashi, M. Fujishima","doi":"10.1109/ASSCC.2006.357884","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357884","url":null,"abstract":"A cascade CMOS mixer is fabricated to exploit the unlicensed band around 60 GHz. This topology avoids the need for area-consuming power combining and uses simple matching with slow-wave transmission lines (SWTL). SWTL has a higher quality factor and allows area reduction. The circuit is fabricated in standard digital 90-nm CMOS and has a radio frequency (RF) return-loss more than 10 dB between 46 GHz and 64 GHz. At RF of 60 GHz, intermediate frequency (IF) of 4 GHz and local oscillator (LO) power of 1.5 dBm, the conversion loss is 1.2 dB and an input-referred 1-dB compression point of 0.5 dBm was measured. The length reduction of the transmission lines achieved is 47% and the resulting chip occupies an area of 0.61 mm x 0.80 mm with comparable performance to other works.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"77 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120843486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357894
Hui Zheng, H. Luong
A 36/44-MHz wide-band switched-capacitor (SC) band-pass filter is proposed for cable-TV tuner systems. The 14th-order SC biquadratic filter employs 2-path technique to achieve high attenuation and wide bandwidth at high frequency. Implemented in a 0.18-mum CMOS process, the filter measures center frequencies of 36 MHz and 44 MHz with a bandwidth of 5.0 MHz and 6.2 MHz, respectively. Adjacent-channel attenuation of -58 dBc and pass-band ripple of less than 0.6 dB are achieved.
{"title":"A 36/44 MHz Switched-capacitor Bandpass Filter for Cable-TV Tuner Application","authors":"Hui Zheng, H. Luong","doi":"10.1109/ASSCC.2006.357894","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357894","url":null,"abstract":"A 36/44-MHz wide-band switched-capacitor (SC) band-pass filter is proposed for cable-TV tuner systems. The 14th-order SC biquadratic filter employs 2-path technique to achieve high attenuation and wide bandwidth at high frequency. Implemented in a 0.18-mum CMOS process, the filter measures center frequencies of 36 MHz and 44 MHz with a bandwidth of 5.0 MHz and 6.2 MHz, respectively. Adjacent-channel attenuation of -58 dBc and pass-band ripple of less than 0.6 dB are achieved.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123650204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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