Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357938
J. Woo, Hyunjoong Lee, Woo-Yeol Shin, Heesoo Song, D. Jeong, Suhwan Kim
This paper presents the design of a phase-locked loop (PLL) based clock and data recovery (CDR) circuit that meets fast locking and low jitter. We reduce the locking time of a CDR circuit using a new autonomously reconfigurable charge pump and loop filter in a 1.25 Gb/s CDR circuit. An experimental prototype was implemented in a 0.18 mum standard CMOS technology. A receiver that incorporates our CDR circuit has an active area of 380 mum times 350 mum.
{"title":"A Fast-Locking CDR Circuit with an Autonomously Reconfigurable Charge Pump and Loop Filter","authors":"J. Woo, Hyunjoong Lee, Woo-Yeol Shin, Heesoo Song, D. Jeong, Suhwan Kim","doi":"10.1109/ASSCC.2006.357938","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357938","url":null,"abstract":"This paper presents the design of a phase-locked loop (PLL) based clock and data recovery (CDR) circuit that meets fast locking and low jitter. We reduce the locking time of a CDR circuit using a new autonomously reconfigurable charge pump and loop filter in a 1.25 Gb/s CDR circuit. An experimental prototype was implemented in a 0.18 mum standard CMOS technology. A receiver that incorporates our CDR circuit has an active area of 380 mum times 350 mum.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125590997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357859
Tsung-Hsien Lin, Chao-Ching Chi
This paper presents a 50% duty-cycle correction (DCC) circuit. The proposed DCC circuit consists of a clock generator and a delay detector. The clock generator is edge-triggered by the input and produces an output signal whose pulse width is controlled by the delay detector to half of the input signal period. Meanwhile, the input phase information is preserved owing to the edge-trigger nature. The circuit is implemented in a TSMC 0.35-μm CMOS process. To evaluate the output duty-cycle accuracy, a single-sideband mixing measurement technique is adopted. This circuit operates from 70 MHz to 490 MHz, and accommodates input duty cycles ranging from 10% to 90%. The output signal is corrected to 50% ± 2%. Operated from a 3.3-V supply, the circuit dissipates 8 mA at 490 MHz.
{"title":"A 70-490 MHz 50% Duty-Cycle Correction Circuit in 0.3-μm CMOS","authors":"Tsung-Hsien Lin, Chao-Ching Chi","doi":"10.1109/ASSCC.2006.357859","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357859","url":null,"abstract":"This paper presents a 50% duty-cycle correction (DCC) circuit. The proposed DCC circuit consists of a clock generator and a delay detector. The clock generator is edge-triggered by the input and produces an output signal whose pulse width is controlled by the delay detector to half of the input signal period. Meanwhile, the input phase information is preserved owing to the edge-trigger nature. The circuit is implemented in a TSMC 0.35-μm CMOS process. To evaluate the output duty-cycle accuracy, a single-sideband mixing measurement technique is adopted. This circuit operates from 70 MHz to 490 MHz, and accommodates input duty cycles ranging from 10% to 90%. The output signal is corrected to 50% ± 2%. Operated from a 3.3-V supply, the circuit dissipates 8 mA at 490 MHz.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132878346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357940
Yong Liu, Hakho Lee, R. Westervelt, D. Ham
There are burgeoning efforts to use CMOS ICs for biotechnology. This paper reviews one such effort, development of a CMOS/Microfluidic hybrid system for magnetic manipulation of biological cells originally reported by the authors in H. Lee et al. (2005, 2006). Programmable magnetic field patterns produced by a CMOS microcoil array IC efficiently manipulate individual cells (tagged by magnetic beads) inside a microfluidic system fabricated on top of the IC.
{"title":"CMOS Meets Bio","authors":"Yong Liu, Hakho Lee, R. Westervelt, D. Ham","doi":"10.1109/ASSCC.2006.357940","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357940","url":null,"abstract":"There are burgeoning efforts to use CMOS ICs for biotechnology. This paper reviews one such effort, development of a CMOS/Microfluidic hybrid system for magnetic manipulation of biological cells originally reported by the authors in H. Lee et al. (2005, 2006). Programmable magnetic field patterns produced by a CMOS microcoil array IC efficiently manipulate individual cells (tagged by magnetic beads) inside a microfluidic system fabricated on top of the IC.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133749656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357866
Yang Kun, Zhang Chun, Du Guoze, Xie Jiangxiang, W. Zhihua
A single chip decoder SOC for H.264 baseline profile, called OR264 (OR1K based H264 decoder), is presented in this paper. The chip has mixed hardware/software architecture to combine performance and flexibility. It is partitioned that the hardware is used to boost the performance and efficiency of key operations in H.264 decoder while the software is used to control the decoding flow and to synchronize the hardware modules. All hardware units operate in parallel. The hardware can decode a MB in 851 clock cycles under ideal condition. The chip is fabricated using UMC 0.18-mum 6-layers metal CMOS process. It contains 1.5 M transistors and 176k bits embedded SRAM. The die size is 4.8 mm x 4.8 mm and the critical path is 10 ns.
本文提出了一种用于H.264基线配置的单片解码器SOC，称为OR264(基于OR1K的H264解码器)。该芯片采用混合硬件/软件架构，将性能和灵活性结合起来。硬件部分主要用于提高H.264解码器关键操作的性能和效率，软件部分主要用于控制解码流程和实现各硬件模块的同步。所有硬件单元并行运行。在理想情况下，硬件可以在851个时钟周期内解码一个MB。该芯片采用UMC 0.18-mum 6层金属CMOS工艺制造。它包含1.5 M晶体管和176k位嵌入式SRAM。模具尺寸为4.8 mm × 4.8 mm，关键路径为10ns。
{"title":"A Hardware-Software Co-design for H.264/AVG Decoder","authors":"Yang Kun, Zhang Chun, Du Guoze, Xie Jiangxiang, W. Zhihua","doi":"10.1109/ASSCC.2006.357866","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357866","url":null,"abstract":"A single chip decoder SOC for H.264 baseline profile, called OR264 (OR1K based H264 decoder), is presented in this paper. The chip has mixed hardware/software architecture to combine performance and flexibility. It is partitioned that the hardware is used to boost the performance and efficiency of key operations in H.264 decoder while the software is used to control the decoding flow and to synchronize the hardware modules. All hardware units operate in parallel. The hardware can decode a MB in 851 clock cycles under ideal condition. The chip is fabricated using UMC 0.18-mum 6-layers metal CMOS process. It contains 1.5 M transistors and 176k bits embedded SRAM. The die size is 4.8 mm x 4.8 mm and the critical path is 10 ns.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132906771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357898
R.D. Singh, Kyung-Wan Yu
A biasing scheme that improves the linearity of linear mode power amplifiers (PA) is presented. This technique employs adding feedback to a current mirror bias to enhance the linearity of the amplifier by compensating the nonlinear input capacitance of the core transistor. The technique is verified with simulations and implemented in a prototype 2.4 GHz PA for WLAN application. The PA is fabricated in a 0.35-mum CMOS and achieves a small-signal gain of 25.4 dB, output P1dB of 25.1 dBm, and a power-added efficiency (PAE) of 40%.
提出了一种提高线性型功率放大器线性度的偏置方案。该技术采用在电流反射镜偏置上增加反馈，通过补偿核心晶体管的非线性输入电容来增强放大器的线性度。通过仿真验证了该技术，并在一个用于WLAN应用的2.4 GHz PA样机中实现了该技术。该放大器采用0.35 μ m CMOS制造，小信号增益为25.4 dB，输出P1dB为25.1 dBm，功率附加效率(PAE)为40%。
{"title":"A Linear Mode CMOS Power Amplifier with Self-Linearizing Bias","authors":"R.D. Singh, Kyung-Wan Yu","doi":"10.1109/ASSCC.2006.357898","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357898","url":null,"abstract":"A biasing scheme that improves the linearity of linear mode power amplifiers (PA) is presented. This technique employs adding feedback to a current mirror bias to enhance the linearity of the amplifier by compensating the nonlinear input capacitance of the core transistor. The technique is verified with simulations and implemented in a prototype 2.4 GHz PA for WLAN application. The PA is fabricated in a 0.35-mum CMOS and achieves a small-signal gain of 25.4 dB, output P1dB of 25.1 dBm, and a power-added efficiency (PAE) of 40%.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123243757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357894
Hui Zheng, H. Luong
A 36/44-MHz wide-band switched-capacitor (SC) band-pass filter is proposed for cable-TV tuner systems. The 14th-order SC biquadratic filter employs 2-path technique to achieve high attenuation and wide bandwidth at high frequency. Implemented in a 0.18-mum CMOS process, the filter measures center frequencies of 36 MHz and 44 MHz with a bandwidth of 5.0 MHz and 6.2 MHz, respectively. Adjacent-channel attenuation of -58 dBc and pass-band ripple of less than 0.6 dB are achieved.
{"title":"A 36/44 MHz Switched-capacitor Bandpass Filter for Cable-TV Tuner Application","authors":"Hui Zheng, H. Luong","doi":"10.1109/ASSCC.2006.357894","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357894","url":null,"abstract":"A 36/44-MHz wide-band switched-capacitor (SC) band-pass filter is proposed for cable-TV tuner systems. The 14th-order SC biquadratic filter employs 2-path technique to achieve high attenuation and wide bandwidth at high frequency. Implemented in a 0.18-mum CMOS process, the filter measures center frequencies of 36 MHz and 44 MHz with a bandwidth of 5.0 MHz and 6.2 MHz, respectively. Adjacent-channel attenuation of -58 dBc and pass-band ripple of less than 0.6 dB are achieved.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123650204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357877
Tien-Yu Lo, C. Hung
A novel configuration of linearized Operational Transconductance Amplifier (OTA) for low-voltage and high frequency applications is proposed. By using double differential pairs and the source degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability, and thus reduces distortion caused by common-mode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about -60dB third-order inter- modulation (IM3) distortion for up to 0.9 VPP at 40 MHz. Ths OTA was fabricated by the TSMC 180-nm Deep N-WELL CMOS process. It occupies a small area of 15.1 x 10-3 mm2 and the power consumption is 9.5 mW under a 1.5-V supply voltage.
{"title":"1.5-V Linear CMOS OTA with -60dB IM3 for High Frequency Applications","authors":"Tien-Yu Lo, C. Hung","doi":"10.1109/ASSCC.2006.357877","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357877","url":null,"abstract":"A novel configuration of linearized Operational Transconductance Amplifier (OTA) for low-voltage and high frequency applications is proposed. By using double differential pairs and the source degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability, and thus reduces distortion caused by common-mode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about -60dB third-order inter- modulation (IM3) distortion for up to 0.9 VPP at 40 MHz. Ths OTA was fabricated by the TSMC 180-nm Deep N-WELL CMOS process. It occupies a small area of 15.1 x 10-3 mm2 and the power consumption is 9.5 mW under a 1.5-V supply voltage.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114449251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357941
D. Fang, R. Roberts, B. Nikolić
A parallel, 12 mum-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3 mum x 3 mum analog DRAM cells in a 2.5/1 V 90 nm CMOS process, with an application in maskless lithography. An innovative self-calibrating compensation circuit limits the effect of charge leakage and capacitive process mismatch to less than 0.5 LSB over 100 ms of data hold time. A 2 mm x 2 mm test chip implements a mixed-signal interface with 32 DACs driving four 32 times 256 analog DRAM arrays.
一种并联、12 μ m间距、低功耗6-b分段数模转换器(DAC)阵列在2.5/1 V 90nm CMOS工艺中驱动3 μ m x 3 μ m模拟DRAM单元阵列，应用于无掩模光刻。创新的自校准补偿电路将电荷泄漏和电容过程失配的影响限制在100 ms数据保持时间内小于0.5 LSB。一个2mm × 2mm的测试芯片实现了一个混合信号接口，32个dac驱动4个32 × 256模拟DRAM阵列。
{"title":"A 6-b DAC and Analog DRAM for a Maskiess Lithography Interface in 90 nm CMOS","authors":"D. Fang, R. Roberts, B. Nikolić","doi":"10.1109/ASSCC.2006.357941","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357941","url":null,"abstract":"A parallel, 12 mum-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3 mum x 3 mum analog DRAM cells in a 2.5/1 V 90 nm CMOS process, with an application in maskless lithography. An innovative self-calibrating compensation circuit limits the effect of charge leakage and capacitive process mismatch to less than 0.5 LSB over 100 ms of data hold time. A 2 mm x 2 mm test chip implements a mixed-signal interface with 32 DACs driving four 32 times 256 analog DRAM arrays.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129506913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357867
M. Hariyama, N. Yokoyama, M. Kameyama
This paper presents a 1000-frame/sec stereo-matching VLSI for adaptive window-size control. To reduce the computational amount, the algorithm uses images divided into non-overlapping regions. The matching result is iteratively refined by reducing a window size. Window-parallel and pixel-parallel architecture is proposed to achieve to exploit the potential parallelism.
{"title":"1000 frame/sec Stereo Matching VLSI Processor with Adaptive Window-Size Control","authors":"M. Hariyama, N. Yokoyama, M. Kameyama","doi":"10.1109/ASSCC.2006.357867","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357867","url":null,"abstract":"This paper presents a 1000-frame/sec stereo-matching VLSI for adaptive window-size control. To reduce the computational amount, the algorithm uses images divided into non-overlapping regions. The matching result is iteratively refined by reducing a window size. Window-parallel and pixel-parallel architecture is proposed to achieve to exploit the potential parallelism.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125310798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/ASSCC.2006.357843
A. Leon, D. Sheahan
Throughput computing represents a new paradigm in processor design focusing on maximizing overall throughput of commercial workloads while addressing increasing demands for improved power and cooling in today's data centers. The first generation of "Niagara" SPARC processors implements a power-efficient chip multithreading (CMT) architecture, which combines eight 4-threaded 64 b cores, a high bandwidth interconnect crossbar, a shared 3 MB L2 Cache and four double-width DDR2 DRAM interfaces. Implemented in 90 nm CMOS technology, the 378 mm2 die consumes only 63 W at 1.2 GHz. The UltraSPARC Tl based systems are oriented to a wide variety of applications, including WebServers, data and application servers, Java applications, search, streaming video and Telco applications.
{"title":"The U1traSPARC T1: A Power-Efficient High-Throughput 32-Thread SPARC Processor","authors":"A. Leon, D. Sheahan","doi":"10.1109/ASSCC.2006.357843","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357843","url":null,"abstract":"Throughput computing represents a new paradigm in processor design focusing on maximizing overall throughput of commercial workloads while addressing increasing demands for improved power and cooling in today's data centers. The first generation of \"Niagara\" SPARC processors implements a power-efficient chip multithreading (CMT) architecture, which combines eight 4-threaded 64 b cores, a high bandwidth interconnect crossbar, a shared 3 MB L2 Cache and four double-width DDR2 DRAM interfaces. Implemented in 90 nm CMOS technology, the 378 mm2 die consumes only 63 W at 1.2 GHz. The UltraSPARC Tl based systems are oriented to a wide variety of applications, including WebServers, data and application servers, Java applications, search, streaming video and Telco applications.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125349981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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