Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517448
M. L. Lovejoy, G. Patrizi, P. Enquist, R. F. Carson, D. Craft, R. Shul
An ultra-low-power, long-wavelength photoreceiver based on InGaAs-InP heterojunction bipolar transistors is reported. The photoreceivers were designed for massively parallel applications where low-power density is necessary for both electrical and thermal reasons. We demonstrate two-dimensional, four-by-four arrays of photoreceivers for free-space optical data links that interface directly with 3.3 V CMOS ASICs and dissipate less than 12 mW/channel; lower power is possible. Propagation delays of /spl sim/1 nsec were measured and large signal operation to 800 Mbits/sec is demonstrated. The array is on a 500 /spl mu/m pitch and can be easily scaled to much higher density. The photoreceivers can be utilized in both free-space and guided-wave applications.
报道了一种基于InGaAs-InP异质结双极晶体管的超低功耗长波光接收机。光电接收器是为大规模并行应用而设计的，在这些应用中，由于电和热原因，低功率密度是必要的。我们展示了用于自由空间光数据链路的二维四乘四光电接收器阵列，该阵列直接与3.3 V CMOS asic接口，功耗小于12 mW/通道;更低的功率是可能的。测量了/spl sim/1 nsec的传输延迟，并演示了800 mbit /sec的大信号处理。该阵列的间距为500 /spl亩/米，可以轻松缩放到更高的密度。该光电接收器可用于自由空间和导波应用。
{"title":"Ultra-low-power, long-wavelength photoreceivers for massively-parallel optical data links","authors":"M. L. Lovejoy, G. Patrizi, P. Enquist, R. F. Carson, D. Craft, R. Shul","doi":"10.1109/ECTC.1996.517448","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517448","url":null,"abstract":"An ultra-low-power, long-wavelength photoreceiver based on InGaAs-InP heterojunction bipolar transistors is reported. The photoreceivers were designed for massively parallel applications where low-power density is necessary for both electrical and thermal reasons. We demonstrate two-dimensional, four-by-four arrays of photoreceivers for free-space optical data links that interface directly with 3.3 V CMOS ASICs and dissipate less than 12 mW/channel; lower power is possible. Propagation delays of /spl sim/1 nsec were measured and large signal operation to 800 Mbits/sec is demonstrated. The array is on a 500 /spl mu/m pitch and can be easily scaled to much higher density. The photoreceivers can be utilized in both free-space and guided-wave applications.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122864130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517386
J. Bartley
In todays packaging environment, we are constantly faced with an array of technology choices for our applications. When new technology is involved there is almost always the point in the development project when the designers ask themselves, "Is it worth it?" or "Did we make the right choices?" It is from this process we learn and look for more efficient ways of doing business in the future. This paper describes why we chose Multi-Chip Modules with Thin-Film wiring (MCM-D on C) for our latest AS/400 processor package. The package consists of 5 layers (2 power, 2 signal, 1 mounting/repair) of thin-film metal applied to the surface of a 30 layer ceramic substrate. The paper specifically addresses design aspects of this module such as the electrical, thermal, mechanical requirements and why this version of MCM packaging was necessary. Included is a discussion on what advantages (real and wished-for) were derived from utilizing the thin-film wiring. A comparison is provided of the actual package performance to the design requirements from the application perspective. The paper also addresses such topics as design methodology, noise analysis (power and signal), test, concurrent process development, and debug/repair strategies that burden the development process of using MCMs.
在当今的包装环境中，我们不断面临着一系列的技术选择。当涉及到新技术时，在开发项目中设计师总是会问自己:“这值得吗?”或者“我们是否做出了正确的选择?”正是从这个过程中，我们学习并寻找未来更有效的经营方式。本文描述了我们为最新的AS/400处理器封装选择带有薄膜布线的多芯片模块(MCM-D on C)的原因。该封装由5层(2层电源，2层信号，1层安装/修复)薄膜金属应用于30层陶瓷基板的表面。本文特别介绍了该模块的设计方面，如电气、热、机械要求，以及为什么需要这个版本的MCM封装。本文还讨论了利用薄膜布线的优点(实际的和期望的)。从应用程序的角度将实际的包性能与设计需求进行比较。本文还讨论了诸如设计方法、噪声分析(功率和信号)、测试、并发过程开发以及调试/修复策略等问题，这些问题加重了使用mcm的开发过程。
{"title":"A user's view of MCM-D/C packaging: is it worth the trouble?","authors":"J. Bartley","doi":"10.1109/ECTC.1996.517386","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517386","url":null,"abstract":"In todays packaging environment, we are constantly faced with an array of technology choices for our applications. When new technology is involved there is almost always the point in the development project when the designers ask themselves, \"Is it worth it?\" or \"Did we make the right choices?\" It is from this process we learn and look for more efficient ways of doing business in the future. This paper describes why we chose Multi-Chip Modules with Thin-Film wiring (MCM-D on C) for our latest AS/400 processor package. The package consists of 5 layers (2 power, 2 signal, 1 mounting/repair) of thin-film metal applied to the surface of a 30 layer ceramic substrate. The paper specifically addresses design aspects of this module such as the electrical, thermal, mechanical requirements and why this version of MCM packaging was necessary. Included is a discussion on what advantages (real and wished-for) were derived from utilizing the thin-film wiring. A comparison is provided of the actual package performance to the design requirements from the application perspective. The paper also addresses such topics as design methodology, noise analysis (power and signal), test, concurrent process development, and debug/repair strategies that burden the development process of using MCMs.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124418067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517417
A. Reyes, S. El-Ghazaly, S. Dorn, M. Dydyk, D. Schroder, H. Patterson
Silicon has many advantages as a system substrate material including low cost and a mature technology. However, Si has not been demonstrated as a good microwave substrate compared to semi-insulating GaAs or quartz. The aim of this paper is to evaluate the potential of using high-resistivity silicon as a low-cost low-loss microwave substrate through an experimental comparative study. Coplanar waveguides fabricated on Si, GaAs and quartz substrates are tested and their characteristics are compared. Microwave spiral inductors and meander lines are also fabricated on various substrates, and their performance is also analyzed. The results demonstrate that the losses of a coplanar transmission line (CPW) realized on high-resistivity (3 k to 7 k /spl Omega/-cm) silicon substrates are comparable to the losses of a CPW realized on a GaAs substrate covered with insulator. Furthermore, measured unloaded Q's of microwave inductive structures on high-resistivity silicon substrates are comparable to the measured unloaded Q's of the same structures on GaAs and on quartz. The measured results are explained using both microwave and semiconductor physics theory. This paper demonstrates that high-resistivity Si can be used as a microwave substrate.
硅作为系统衬底材料具有成本低、技术成熟等优点。然而，与半绝缘的砷化镓或石英相比，硅尚未被证明是一种良好的微波衬底。本文的目的是通过实验对比研究来评估高电阻硅作为低成本低损耗微波衬底的潜力。测试了在硅、砷化镓和石英衬底上制备的共面波导，并比较了它们的特性。在不同的衬底上制作了微波螺旋电感器和弯曲线，并对其性能进行了分析。结果表明，在高电阻率(3 k ~ 7 k /spl ω /-cm)硅衬底上实现的共面传输线损耗与在覆盖绝缘体的砷化镓衬底上实现的共面传输线损耗相当。此外，在高电阻硅衬底上测量的微波感应结构的空载Q值与在砷化镓和石英上测量的相同结构的空载Q值相当。用微波和半导体物理理论对测量结果进行了解释。本文论证了高电阻率硅可以用作微波衬底。
{"title":"High resistivity Si as a microwave substrate","authors":"A. Reyes, S. El-Ghazaly, S. Dorn, M. Dydyk, D. Schroder, H. Patterson","doi":"10.1109/ECTC.1996.517417","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517417","url":null,"abstract":"Silicon has many advantages as a system substrate material including low cost and a mature technology. However, Si has not been demonstrated as a good microwave substrate compared to semi-insulating GaAs or quartz. The aim of this paper is to evaluate the potential of using high-resistivity silicon as a low-cost low-loss microwave substrate through an experimental comparative study. Coplanar waveguides fabricated on Si, GaAs and quartz substrates are tested and their characteristics are compared. Microwave spiral inductors and meander lines are also fabricated on various substrates, and their performance is also analyzed. The results demonstrate that the losses of a coplanar transmission line (CPW) realized on high-resistivity (3 k to 7 k /spl Omega/-cm) silicon substrates are comparable to the losses of a CPW realized on a GaAs substrate covered with insulator. Furthermore, measured unloaded Q's of microwave inductive structures on high-resistivity silicon substrates are comparable to the measured unloaded Q's of the same structures on GaAs and on quartz. The measured results are explained using both microwave and semiconductor physics theory. This paper demonstrates that high-resistivity Si can be used as a microwave substrate.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128142091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550764
K.D. Ellacott, K.P. Stone
DC-DC power converters, also referred to as Point-of-Use Power Supplies (PUPS), which mount directly to a printed circuit board are a commonly available commercial device. These devices come in a multitude of shapes and sizes from a wide range of manufacturers. As the key interface between the incoming battery feed voltage and the complex electronics which make up today's telecommunication products, reliable power converters are critical to uninterrupted system operation. In light of the fact that factors relating to the design and manufacture of these devices are out of Nortel's direct control, a systematic approach was developed to aid in assessing the quality and robustness of product being purchased by Nortel. This paper will describe the process used by Nortel to evaluate DC-DC power converters.
{"title":"A practical test method for DC-DC converter qualification","authors":"K.D. Ellacott, K.P. Stone","doi":"10.1109/ECTC.1996.550764","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550764","url":null,"abstract":"DC-DC power converters, also referred to as Point-of-Use Power Supplies (PUPS), which mount directly to a printed circuit board are a commonly available commercial device. These devices come in a multitude of shapes and sizes from a wide range of manufacturers. As the key interface between the incoming battery feed voltage and the complex electronics which make up today's telecommunication products, reliable power converters are critical to uninterrupted system operation. In light of the fact that factors relating to the design and manufacture of these devices are out of Nortel's direct control, a systematic approach was developed to aid in assessing the quality and robustness of product being purchased by Nortel. This paper will describe the process used by Nortel to evaluate DC-DC power converters.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126372383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550503
M. Ellsworth, H. Hamel, E. Perfecto, T. Wassick
This paper describes a state-of-the-art seven chip MCM-D/C package currently under production for use as a processor module for the high end of IBM's AS/400 Advanced Series with PowerPC technology. Physical design, process, and electrical design (characterization) is described, and trade-offs made between them are discussed.
{"title":"A high density, high performance MCM-D/C package: a design, electrical, and process perspective","authors":"M. Ellsworth, H. Hamel, E. Perfecto, T. Wassick","doi":"10.1109/ECTC.1996.550503","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550503","url":null,"abstract":"This paper describes a state-of-the-art seven chip MCM-D/C package currently under production for use as a processor module for the high end of IBM's AS/400 Advanced Series with PowerPC technology. Physical design, process, and electrical design (characterization) is described, and trade-offs made between them are discussed.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124824371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517444
S.K. Kang, R. Rai, S. Purushothaman
Electrically conducting adhesive technology is one of the alternatives being actively investigated for the possibility of replacing the solder interconnection technology used for microelectronics applications. An isotropically conducting adhesive consists of metallic filler particles dispersed in the matrix of a polymer resin. Silver-filled epoxy resin is commonly used for thermal conduction in die attach applications. Silver particles can provide electrical and/or thermal conduction, while epoxy provides adhesive bonding of the components to a substrate. This material has several limitations when it is-considered as a replacement for solder interconnections, such as low electrical conductivity, low joint strength, increase in contact resistance upon thermal cycling, lack of reworkability, and silver migration. In order to overcome these limitations, a new formulation is proposed based on alternative Pb-free conducting filler powder and tailored polymer resins. The conducting filler particles are coated with low melting point, non-toxic metals which can be fused to achieve metallurgical bonding between adjacent particles as well as to a substrate. This new conductive adhesive material has shown improved electrical and mechanical properties over the existing silver-filled epoxy materials.
{"title":"Development of high conductivity lead (Pb)-free conducting adhesives","authors":"S.K. Kang, R. Rai, S. Purushothaman","doi":"10.1109/ECTC.1996.517444","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517444","url":null,"abstract":"Electrically conducting adhesive technology is one of the alternatives being actively investigated for the possibility of replacing the solder interconnection technology used for microelectronics applications. An isotropically conducting adhesive consists of metallic filler particles dispersed in the matrix of a polymer resin. Silver-filled epoxy resin is commonly used for thermal conduction in die attach applications. Silver particles can provide electrical and/or thermal conduction, while epoxy provides adhesive bonding of the components to a substrate. This material has several limitations when it is-considered as a replacement for solder interconnections, such as low electrical conductivity, low joint strength, increase in contact resistance upon thermal cycling, lack of reworkability, and silver migration. In order to overcome these limitations, a new formulation is proposed based on alternative Pb-free conducting filler powder and tailored polymer resins. The conducting filler particles are coated with low melting point, non-toxic metals which can be fused to achieve metallurgical bonding between adjacent particles as well as to a substrate. This new conductive adhesive material has shown improved electrical and mechanical properties over the existing silver-filled epoxy materials.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124128536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550490
C. Huang, M. Çelik, J. Prince
This paper presents a fast and accurate methodology for Simultaneous Switching Noise (SSN) simulation for thin film packaging structures using a macro-modeling technique. The combination of interconnect macromodels and SPICE simulation for nonlinear drivers make this technique attractive for large SSN simulation. This technique results in one order of magnitude improvement in the simulation speed for SSN when compared with conventional SPICE run time.
{"title":"Simultaneous switching noise simulation for thin film packages using macromodeling technique","authors":"C. Huang, M. Çelik, J. Prince","doi":"10.1109/ECTC.1996.550490","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550490","url":null,"abstract":"This paper presents a fast and accurate methodology for Simultaneous Switching Noise (SSN) simulation for thin film packaging structures using a macro-modeling technique. The combination of interconnect macromodels and SPICE simulation for nonlinear drivers make this technique attractive for large SSN simulation. This technique results in one order of magnitude improvement in the simulation speed for SSN when compared with conventional SPICE run time.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123672421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517382
T. Lenihan, L. Schaper, Y. Shi, G. Morcan, J. Parkerson
The High Density Electronics Center (HiDEC) at the University of Arkansas is working with the Sheldahl MCM-L Consortium and Rensselaer Polytechnic Institute (RPI) to develop low-cost embedded resistors, capacitors, and inductors in flexible polyimide films under an ARPA contract. Embedding thin-film passive devices into polyimide layers as part of a Multichip Module (MCM) system is new. The design concept allows fabrication and testing of embedded passive devices before assembling them into an MCM-L substrate. Embedded passive devices are needed as an enhancement to present day MCM-L and MCM-D technologies. The ability to remove devices such as terminating resistors and decoupling capacitors from the surfaces of PCB boards and MCMs into a flexible film, at low cost, would be a break-through for MCM technology. The devices are made into a flexible MCM package using a 2 layer interconnect system called the Interconnected Mesh Power System (IMPS) developed and patented at the University of Arkansas. The IMPS interconnection topology incorporates fine line lithography and batch via generation to allow planar power and ground distribution, and dense signal interconnection, on only two metal layers. The materials being used are NiCr, TaN, and CrSi for the resistors and Ta/sub x/O/sub y/ and BaTiO/sub x/ for the capacitors. Contacts, interconnecting signal lines, and power lines are made with Cu metallurgy. The devices are made on a 25 /spl mu/m or 50 /spl mu/m thick polyimide film and are encapsulated with the same polyimide.
{"title":"Embedded thin film resistors, capacitors and inductors in flexible polyimide films","authors":"T. Lenihan, L. Schaper, Y. Shi, G. Morcan, J. Parkerson","doi":"10.1109/ECTC.1996.517382","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517382","url":null,"abstract":"The High Density Electronics Center (HiDEC) at the University of Arkansas is working with the Sheldahl MCM-L Consortium and Rensselaer Polytechnic Institute (RPI) to develop low-cost embedded resistors, capacitors, and inductors in flexible polyimide films under an ARPA contract. Embedding thin-film passive devices into polyimide layers as part of a Multichip Module (MCM) system is new. The design concept allows fabrication and testing of embedded passive devices before assembling them into an MCM-L substrate. Embedded passive devices are needed as an enhancement to present day MCM-L and MCM-D technologies. The ability to remove devices such as terminating resistors and decoupling capacitors from the surfaces of PCB boards and MCMs into a flexible film, at low cost, would be a break-through for MCM technology. The devices are made into a flexible MCM package using a 2 layer interconnect system called the Interconnected Mesh Power System (IMPS) developed and patented at the University of Arkansas. The IMPS interconnection topology incorporates fine line lithography and batch via generation to allow planar power and ground distribution, and dense signal interconnection, on only two metal layers. The materials being used are NiCr, TaN, and CrSi for the resistors and Ta/sub x/O/sub y/ and BaTiO/sub x/ for the capacitors. Contacts, interconnecting signal lines, and power lines are made with Cu metallurgy. The devices are made on a 25 /spl mu/m or 50 /spl mu/m thick polyimide film and are encapsulated with the same polyimide.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125592855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517404
M. Lebby, C. Gaw, Wenbin Jiang, P. Kiely, C. Shieh, P. Claisse, J. Ramdani, D. H. Hartman, D. Schwartz, J. Grula
The use of vertical cavity surface emitting lasers (VCSELs)in a parallel optical interconnect for Motorola's OPTOBUS/sup TM/ interconnect was made public over 1 year ago. This was the first time VCSELs were introduced into a product which took advantage of the excellent qualities of VCSELs over edge-emitting lasers. Motorola's OPTOBUS/sup TM/ interconnect is a ten channel parallel bi-directional data link based on two 10 channel multimode fiber ribbons. One of the key differences in this type of interconnect compared with previous data link designs is the use of the VCSELs as the optical source for the link's fiber optic transmitter. A single 1/spl times/10 VCSEL array from a GaAs wafer is die attached to a 10 channel GUIDECAST/sup TM/ optical interface unit which couples the emission from each laser device to its corresponding fiber ribbon channel and thus negates the use of expensive manufacturing techniques such as active alignment and pigtailing. The OPTOBUS/sup TM/ interconnect achieves its performance goals (which include low cost) via the unique characteristics of the GaAs VCSELs arrays. For example, the 850 nm devices produce a circular symmetric beam with a half angle of about 10 degrees allowing the coupling loss into the waveguide to be less than 3 dB. In addition, to maintain low manufacturing costs, each VCSEL array is individually and automatically probe tested (just as in the silicon industry) to verify that each VCSEL achieves the OPTOBUS/sup TM/ interconnect's stringent electrical, optical, thermal and mechanical specifications. Typical computer generated wafer maps from automated production tooling and statistical parametric results are discussed. The combination of low threshold currents with superior thermal and optical performance allow the devices to be modulated under fixed bias conditions. Typical drive currents of 3X threshold are used to obtain nominal FDA Class 1 safety optical power levels from the GUIDECAST/sup TM/ optical interface unit.
{"title":"Characteristics of VCSEL arrays for parallel optical interconnects","authors":"M. Lebby, C. Gaw, Wenbin Jiang, P. Kiely, C. Shieh, P. Claisse, J. Ramdani, D. H. Hartman, D. Schwartz, J. Grula","doi":"10.1109/ECTC.1996.517404","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517404","url":null,"abstract":"The use of vertical cavity surface emitting lasers (VCSELs)in a parallel optical interconnect for Motorola's OPTOBUS/sup TM/ interconnect was made public over 1 year ago. This was the first time VCSELs were introduced into a product which took advantage of the excellent qualities of VCSELs over edge-emitting lasers. Motorola's OPTOBUS/sup TM/ interconnect is a ten channel parallel bi-directional data link based on two 10 channel multimode fiber ribbons. One of the key differences in this type of interconnect compared with previous data link designs is the use of the VCSELs as the optical source for the link's fiber optic transmitter. A single 1/spl times/10 VCSEL array from a GaAs wafer is die attached to a 10 channel GUIDECAST/sup TM/ optical interface unit which couples the emission from each laser device to its corresponding fiber ribbon channel and thus negates the use of expensive manufacturing techniques such as active alignment and pigtailing. The OPTOBUS/sup TM/ interconnect achieves its performance goals (which include low cost) via the unique characteristics of the GaAs VCSELs arrays. For example, the 850 nm devices produce a circular symmetric beam with a half angle of about 10 degrees allowing the coupling loss into the waveguide to be less than 3 dB. In addition, to maintain low manufacturing costs, each VCSEL array is individually and automatically probe tested (just as in the silicon industry) to verify that each VCSEL achieves the OPTOBUS/sup TM/ interconnect's stringent electrical, optical, thermal and mechanical specifications. Typical computer generated wafer maps from automated production tooling and statistical parametric results are discussed. The combination of low threshold currents with superior thermal and optical performance allow the devices to be modulated under fixed bias conditions. Typical drive currents of 3X threshold are used to obtain nominal FDA Class 1 safety optical power levels from the GUIDECAST/sup TM/ optical interface unit.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130539349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550511
T. Evans
As the number of available package types expand to include Plastic Ball Grid Array (PBGA), and performance limitations become more apparent, vast amounts of new information must be properly utilized to make the best design choices at a package level. PBGAs can theoretically satisfy many packaging requirements, but present themselves as a greater risk since they have not yet been thoroughly characterized. Specifically, new product development is jeopardized by integrated circuit performance that can be limited by PBGA, printed circuit board, and system level design, so a critical need is approaching for concurrent engineering design techniques and modeling tools. A design, performance, and application matrix is discussed and may be the first step in focusing these new methods of evaluation on PBGA package technology.
{"title":"Practical considerations for the design, performance, and application of plastic BGA packages","authors":"T. Evans","doi":"10.1109/ECTC.1996.550511","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550511","url":null,"abstract":"As the number of available package types expand to include Plastic Ball Grid Array (PBGA), and performance limitations become more apparent, vast amounts of new information must be properly utilized to make the best design choices at a package level. PBGAs can theoretically satisfy many packaging requirements, but present themselves as a greater risk since they have not yet been thoroughly characterized. Specifically, new product development is jeopardized by integrated circuit performance that can be limited by PBGA, printed circuit board, and system level design, so a critical need is approaching for concurrent engineering design techniques and modeling tools. A design, performance, and application matrix is discussed and may be the first step in focusing these new methods of evaluation on PBGA package technology.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123093970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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