Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550504
L. Yip, T. Massingill, H. Naini
Ball Grid Array (BGA) packages have been gaining popularity due to the increasing demand for greater interconnect density. For high I/O applications, plastic BGA (PBGA) and tape BGA (TBGA) are attractive alternatives to fine-pitch quad flat pack and pin grid array packages because of their relative low cost, ease of surface mount assembly, and smaller board space requirement. However, since PBGA and TBGA are non-hermetic packages, they are vulnerable to moisture-induced damage during the surface mount assembly process. An evaluation was performed to investigate the impact of moisture on package delamination and cracking during the solder reflow process and the reliability of PBGA and TBGA packages. Based on our study using scanning acoustic microscopy and reliability stress tests, both PBGA and TBGA can be safely surface mounted if proper storage and handling guidelines are followed.
{"title":"Moisture sensitivity evaluation of ball grid array packages","authors":"L. Yip, T. Massingill, H. Naini","doi":"10.1109/ECTC.1996.550504","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550504","url":null,"abstract":"Ball Grid Array (BGA) packages have been gaining popularity due to the increasing demand for greater interconnect density. For high I/O applications, plastic BGA (PBGA) and tape BGA (TBGA) are attractive alternatives to fine-pitch quad flat pack and pin grid array packages because of their relative low cost, ease of surface mount assembly, and smaller board space requirement. However, since PBGA and TBGA are non-hermetic packages, they are vulnerable to moisture-induced damage during the surface mount assembly process. An evaluation was performed to investigate the impact of moisture on package delamination and cracking during the solder reflow process and the reliability of PBGA and TBGA packages. Based on our study using scanning acoustic microscopy and reliability stress tests, both PBGA and TBGA can be safely surface mounted if proper storage and handling guidelines are followed.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131944951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517438
O. Strand
Automated fiber pigtailing machines (AFPMs) have been designed and built under an ARPA-funded project The AFPM enables many of the critical technologies to perform automated sub-micron fiber pigtailing compatible with a low-cost manufacturing environment. These technologies include low-cost high-precision stages, computer vision to replace the labor-intensive coarse alignment, and many details of parts handling and feeding. Subsequent generations of the AFPM may build upon the design concepts developed here to pigtail fibers to OE devices in more complicated geometries. For example, all applications for this project use epoxy to attach the fibers, so no applications using solder or laser welding have been considered. Also, the stages to manipulate the fibers provide only three axes of translation, so no rotational degrees of freedom are available, including the very important roll axis for polarization-dependent applications. The third AFPM at LLNL will be used to develop some of these capabilities.
{"title":"Low-cost automated fiber pigtailing machine","authors":"O. Strand","doi":"10.1109/ECTC.1996.517438","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517438","url":null,"abstract":"Automated fiber pigtailing machines (AFPMs) have been designed and built under an ARPA-funded project The AFPM enables many of the critical technologies to perform automated sub-micron fiber pigtailing compatible with a low-cost manufacturing environment. These technologies include low-cost high-precision stages, computer vision to replace the labor-intensive coarse alignment, and many details of parts handling and feeding. Subsequent generations of the AFPM may build upon the design concepts developed here to pigtail fibers to OE devices in more complicated geometries. For example, all applications for this project use epoxy to attach the fibers, so no applications using solder or laser welding have been considered. Also, the stages to manipulate the fibers provide only three axes of translation, so no rotational degrees of freedom are available, including the very important roll axis for polarization-dependent applications. The third AFPM at LLNL will be used to develop some of these capabilities.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131409582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550514
D. Divekar, R. Raghuram, F. Balistreri, N. Matsui
Simulation of frequency dependence of conductor losses is important for getting accurate electrical performance data of interconnects. The method of characteristics is extended to take into account this effect. The method is well suited for incorporating into a general purpose circuit analysis program for time domain simulation. This enables the analysis of interconnects connected in any arbitrary topology along with the associated nonlinear circuits for high speed digital and analog systems.
{"title":"Simulation of frequency dependent conductor loss in interconnects","authors":"D. Divekar, R. Raghuram, F. Balistreri, N. Matsui","doi":"10.1109/ECTC.1996.550514","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550514","url":null,"abstract":"Simulation of frequency dependence of conductor losses is important for getting accurate electrical performance data of interconnects. The method of characteristics is extended to take into account this effect. The method is well suited for incorporating into a general purpose circuit analysis program for time domain simulation. This enables the analysis of interconnects connected in any arbitrary topology along with the associated nonlinear circuits for high speed digital and analog systems.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116944642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550756
M. R. Cooper
Stress screening during design, development, and production of electronic hardware is a quality improvement technique which can be employed to reduce defects in a product. However, due to the variety of electronic hardware types which may be screened and the number of stresses which may be applied for screening, there are no commercial standards which describe how to develop an effective stress screen. This paper describes a non-product-specific screen development technique which utilizes statistical analysis methods to achieve an effective and efficient stress screen. Statistical applications for various aspects of stress screen development are suggested, including Pareto analysis, Exploratory Data Analysis (EDA), Weibull analysis of time-to-failure data, comparison of means, analysis of variance (ANOVA), use of statistical process control charts (CUSUM, X-bar R), Duane plots of reliability growth, and use of the Poisson distribution for determining sample screen sizes. The techniques outlined involve test and analytical activities applied throughout product development; from first prototypes through to volume production. The use of statistical methods allows for development of an effective screen to remove defects and for an effective risk assessment of the effect of defects through numerical quantification of defect probabilities.
{"title":"Statistical methods for stress screen development","authors":"M. R. Cooper","doi":"10.1109/ECTC.1996.550756","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550756","url":null,"abstract":"Stress screening during design, development, and production of electronic hardware is a quality improvement technique which can be employed to reduce defects in a product. However, due to the variety of electronic hardware types which may be screened and the number of stresses which may be applied for screening, there are no commercial standards which describe how to develop an effective stress screen. This paper describes a non-product-specific screen development technique which utilizes statistical analysis methods to achieve an effective and efficient stress screen. Statistical applications for various aspects of stress screen development are suggested, including Pareto analysis, Exploratory Data Analysis (EDA), Weibull analysis of time-to-failure data, comparison of means, analysis of variance (ANOVA), use of statistical process control charts (CUSUM, X-bar R), Duane plots of reliability growth, and use of the Poisson distribution for determining sample screen sizes. The techniques outlined involve test and analytical activities applied throughout product development; from first prototypes through to volume production. The use of statistical methods allows for development of an effective screen to remove defects and for an effective risk assessment of the effect of defects through numerical quantification of defect probabilities.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"198 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113967053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517402
G. de Pestel, A. Picard, J. Vandewege, D. Morlion, Q. Tan, J. Van Koetsem, F. Migom, P. Vetter
A novel interconnection technology based on the integration of glass optical fibres in a standard printed circuit board is presented to overcome the interconnection bottleneck in the nest generation of broad band switching fabrics. Within these systems, the parallel electro-optical modules will be: integrated on the switching board itself which has a switching capacity of 20 Gbit/s. A robust and automated technology is used for the realisation of optical interconnections between these electro-optical (E/O) modules and the off-board connectors at the edge of the board. Dedicated surface optical contacts have been developed, capable of handling 16 parallel channels. These surface optical contacts can be integrated everywhere on the board and can be used for mounting an electro-optical module or a multifibre connector compatible with this technology. Electro-optical modules (8 channel transmitters and 4 channel receivers) and multifibre optical back panel connectors have been integrated on an engineering prototype for the evaluation of the technology. Off-board links, over 200 m MM (graded index) fibre, and on-board links are operational at 622 Mbit/s. The boards have been subjected to reliability tests and preliminary results reveal no degradation of the board after thermal cycling. Precision moulding techniques are presented to make the proposed technology more cost-effective and suitable for volume production.
{"title":"Parallel optical interconnections for future broad band systems, based on the \"fibre in board technology\"","authors":"G. de Pestel, A. Picard, J. Vandewege, D. Morlion, Q. Tan, J. Van Koetsem, F. Migom, P. Vetter","doi":"10.1109/ECTC.1996.517402","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517402","url":null,"abstract":"A novel interconnection technology based on the integration of glass optical fibres in a standard printed circuit board is presented to overcome the interconnection bottleneck in the nest generation of broad band switching fabrics. Within these systems, the parallel electro-optical modules will be: integrated on the switching board itself which has a switching capacity of 20 Gbit/s. A robust and automated technology is used for the realisation of optical interconnections between these electro-optical (E/O) modules and the off-board connectors at the edge of the board. Dedicated surface optical contacts have been developed, capable of handling 16 parallel channels. These surface optical contacts can be integrated everywhere on the board and can be used for mounting an electro-optical module or a multifibre connector compatible with this technology. Electro-optical modules (8 channel transmitters and 4 channel receivers) and multifibre optical back panel connectors have been integrated on an engineering prototype for the evaluation of the technology. Off-board links, over 200 m MM (graded index) fibre, and on-board links are operational at 622 Mbit/s. The boards have been subjected to reliability tests and preliminary results reveal no degradation of the board after thermal cycling. Precision moulding techniques are presented to make the proposed technology more cost-effective and suitable for volume production.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115898708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517442
N. Koopman, S. Nangalia, V. Rogers
MCNC has developed a radically new fluxless, no-clean process which has shown considerable success with assembly of a variety of flip chip configurations. The process, called PADS (Plasma Assisted Fluxless Soldering) relies on a pretreatment which enables the subsequent solder reflow in inert ambients. Conventional mass production soldering tools can be used, just eliminating the flux dispense and flux cleaning steps, and adding the pretreatment step. Highlights of the applications studies are presented. Examples include high lead (97Pb3Sn) bumped flip chips joined to multilayer ceramic substrates with Mo/Mi/Au microsockets at 350/spl deg/C in nitrogen, eutectic tin/lead solder bumped flip chips joined at 250/spl deg/C to bare copper, 95/5 lead/tin bumped flip chips joined to eutectic dipped FR4 printed circuit boards, joining of 90/10 lead tin bumps to each other at 350/spl deg/C, unique MEMS (Micro Electrical Mechanical Systems) devices joined with the dry fluxless process, and solder bumped flip chips joined to flexible circuits. Other related topics to be discussed include tacking, self alignment and its measurement, balling reflow, and rework operations including hot chip pull and site dress. Other areas of application of the fluxless process are highlighted including hermetic seal band attachment, joining of flexible circuit TAB leads to insulator substrates, and joining to solid solder deposits on FR4.
{"title":"Fluxless no-clean assembly of solder bumped flip chips","authors":"N. Koopman, S. Nangalia, V. Rogers","doi":"10.1109/ECTC.1996.517442","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517442","url":null,"abstract":"MCNC has developed a radically new fluxless, no-clean process which has shown considerable success with assembly of a variety of flip chip configurations. The process, called PADS (Plasma Assisted Fluxless Soldering) relies on a pretreatment which enables the subsequent solder reflow in inert ambients. Conventional mass production soldering tools can be used, just eliminating the flux dispense and flux cleaning steps, and adding the pretreatment step. Highlights of the applications studies are presented. Examples include high lead (97Pb3Sn) bumped flip chips joined to multilayer ceramic substrates with Mo/Mi/Au microsockets at 350/spl deg/C in nitrogen, eutectic tin/lead solder bumped flip chips joined at 250/spl deg/C to bare copper, 95/5 lead/tin bumped flip chips joined to eutectic dipped FR4 printed circuit boards, joining of 90/10 lead tin bumps to each other at 350/spl deg/C, unique MEMS (Micro Electrical Mechanical Systems) devices joined with the dry fluxless process, and solder bumped flip chips joined to flexible circuits. Other related topics to be discussed include tacking, self alignment and its measurement, balling reflow, and rework operations including hot chip pull and site dress. Other areas of application of the fluxless process are highlighted including hermetic seal band attachment, joining of flexible circuit TAB leads to insulator substrates, and joining to solid solder deposits on FR4.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116839673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550904
N. Hwang, G. Joo, Sang-Hwan Lee, Seong-Su Park, H. Cho, Min-Kyu Song, K. Pyun
The purpose of this paper is to demonstrate reliability analysis of 1.3 /spl mu/m InGaAsP/InP MQW-PHB laser diodes (LD) for high speed optical communication systems. We have accelerated aging tests and compared the assessment of 1.3 /spl mu/m InGaAsP/InP strain-compensated MQW PBH-LD's with different numbers of quantum well (N/sub QW/) and active width (W/sub A/). The experimental results show that /spl Delta/I/sub th/ is related with W/sub A/ rather than with N/sub QW/. For the same W/sub A/, we have observed that the variation of N/sub QW/ has less effect on /spl Delta/I/sub th/ which is primarily due to the limitation of the fabrication process in controlling the uniformity and homogeneity in the MQW layer.
{"title":"Structure-dependent reliability assessment of 1.3 /spl mu/m InGaAsP/InP uncooled laser diodes by accelerated aging test","authors":"N. Hwang, G. Joo, Sang-Hwan Lee, Seong-Su Park, H. Cho, Min-Kyu Song, K. Pyun","doi":"10.1109/ECTC.1996.550904","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550904","url":null,"abstract":"The purpose of this paper is to demonstrate reliability analysis of 1.3 /spl mu/m InGaAsP/InP MQW-PHB laser diodes (LD) for high speed optical communication systems. We have accelerated aging tests and compared the assessment of 1.3 /spl mu/m InGaAsP/InP strain-compensated MQW PBH-LD's with different numbers of quantum well (N/sub QW/) and active width (W/sub A/). The experimental results show that /spl Delta/I/sub th/ is related with W/sub A/ rather than with N/sub QW/. For the same W/sub A/, we have observed that the variation of N/sub QW/ has less effect on /spl Delta/I/sub th/ which is primarily due to the limitation of the fabrication process in controlling the uniformity and homogeneity in the MQW layer.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117191606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517460
D. Liang
This paper describes a warpage study on LSI Logic's cavity up 40/spl times/10 mm 503 EPBGA and 35/spl times/35 mm 313 EPBGA packages. The main objectives of this study are to evaluate the impacts of the major assembly process on the package warpage, and to determine the impact significance of die size, encapsulation size, encapsulation height and substrate thickness on the package warpage. The package construction and assembly processes are reviewed first. The packages are single tier, 4 layer laminate chip carriers with glob top encapsulation. The assembly processes include die attach, encapsulation, ball attach and marking. Full factorial experiments were designed with both 503 EPBGA and 313 EPBGA packages. Package warpages were measured after each major assembly process. The warpage mode was monitored, and the final package warpages after marking were used for experiment analysis. At LSI Logic, this study has been used to identify the variables to minimize warpage. This was possible without significant change to the overall package construction. LSI Logic is able to meet coplanarity requirement on the low cost 4 layer package structure.
本文对LSI Logic的腔体翘曲进行了40/spl倍/10 mm 503 EPBGA和35/spl倍/35 mm 313 EPBGA封装的研究。本研究的主要目的是评估主要组装工艺对封装翘曲的影响，并确定模具尺寸、封装尺寸、封装高度和衬底厚度对封装翘曲的影响意义。首先回顾了包装的结构和装配过程。封装为单层，4层层压芯片载体，采用球形顶部封装。装配过程包括贴模、封装、贴球和打标。采用503 EPBGA和313 EPBGA包装设计全因子实验。在每个主要装配过程后测量包装翘曲。对翘曲模式进行监测，并将打标后的最终包装翘曲量用于实验分析。在LSI Logic，这项研究已被用于识别变量，以尽量减少翘曲。这是可能的，而不需要对整个包结构进行重大更改。LSI Logic能够满足低成本4层封装结构的共平面性要求。
{"title":"Warpage study of glob top cavity-up EPBGA packages","authors":"D. Liang","doi":"10.1109/ECTC.1996.517460","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517460","url":null,"abstract":"This paper describes a warpage study on LSI Logic's cavity up 40/spl times/10 mm 503 EPBGA and 35/spl times/35 mm 313 EPBGA packages. The main objectives of this study are to evaluate the impacts of the major assembly process on the package warpage, and to determine the impact significance of die size, encapsulation size, encapsulation height and substrate thickness on the package warpage. The package construction and assembly processes are reviewed first. The packages are single tier, 4 layer laminate chip carriers with glob top encapsulation. The assembly processes include die attach, encapsulation, ball attach and marking. Full factorial experiments were designed with both 503 EPBGA and 313 EPBGA packages. Package warpages were measured after each major assembly process. The warpage mode was monitored, and the final package warpages after marking were used for experiment analysis. At LSI Logic, this study has been used to identify the variables to minimize warpage. This was possible without significant change to the overall package construction. LSI Logic is able to meet coplanarity requirement on the low cost 4 layer package structure.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115334042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517410
A. A. Gallo, C. Bischof, K. Howard, S. D. Dunmead, S. A. Anderson
A patented moisture resistant aluminum nitride filler has been developed for use in high thermal conductivity microelectronic molding compounds. Molding compounds based on biphenyl resin and using this filler show high thermal conductivity (4.5 W/mK), low coefficient of thermal expansion (16 ppm //spl deg/C), good flowability, high strength, moderate abrasion, and device reliability comparable to standard fused silica systems. Finite Element Analysis of a TO220 device using transient thermal stress shows approximately a 41% and 64% reduction respectively for Theta ja and Theta jc, assuming an aluminum nitride molding compound of 3.2 W/mK. Experimental thermal measurements on a 208 lead PQFP (no heat sink) molded with an ECN based molding compound (3.4 W/mK) yielded a 21% reduction in Theta ja and a 61% reduction in Theta jc.
{"title":"Moisture resistant aluminum nitride filler for high thermal conductivity microelectronic molding compounds","authors":"A. A. Gallo, C. Bischof, K. Howard, S. D. Dunmead, S. A. Anderson","doi":"10.1109/ECTC.1996.517410","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517410","url":null,"abstract":"A patented moisture resistant aluminum nitride filler has been developed for use in high thermal conductivity microelectronic molding compounds. Molding compounds based on biphenyl resin and using this filler show high thermal conductivity (4.5 W/mK), low coefficient of thermal expansion (16 ppm //spl deg/C), good flowability, high strength, moderate abrasion, and device reliability comparable to standard fused silica systems. Finite Element Analysis of a TO220 device using transient thermal stress shows approximately a 41% and 64% reduction respectively for Theta ja and Theta jc, assuming an aluminum nitride molding compound of 3.2 W/mK. Experimental thermal measurements on a 208 lead PQFP (no heat sink) molded with an ECN based molding compound (3.4 W/mK) yielded a 21% reduction in Theta ja and a 61% reduction in Theta jc.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115377206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517375
Qazi Mudassar Ilyas, M. Potter
Moisture induced failures of surface mount plastic electronic packages during solder reflow is investigated experimentally for various package designs and different levels of moisture. Testing was carried out in connection with the development of guidelines for experimental qualifications and reliability monitoring programs for Metal Oxide Semiconductor (MOS) Integrated Circuit (IC) in plastic packages. Based on the obtained data, we developed recommendations for the selection of the appropriate moisture preconditioning parameters. The recommendations can be helpful to engineers associated with handling and storage of plastic packages of IC devices in and out of dry bags, as well as to quality control specialists, factory personnel, and customers involved in the manufacturing of surface mount plastic packages.
{"title":"Experimental evaluation of moisture-induced failures of surface mount plastic packages","authors":"Qazi Mudassar Ilyas, M. Potter","doi":"10.1109/ECTC.1996.517375","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517375","url":null,"abstract":"Moisture induced failures of surface mount plastic electronic packages during solder reflow is investigated experimentally for various package designs and different levels of moisture. Testing was carried out in connection with the development of guidelines for experimental qualifications and reliability monitoring programs for Metal Oxide Semiconductor (MOS) Integrated Circuit (IC) in plastic packages. Based on the obtained data, we developed recommendations for the selection of the appropriate moisture preconditioning parameters. The recommendations can be helpful to engineers associated with handling and storage of plastic packages of IC devices in and out of dry bags, as well as to quality control specialists, factory personnel, and customers involved in the manufacturing of surface mount plastic packages.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122585503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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