Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517436
M. Shahid, R.A. Roil
A Z-axis assembly process was described for producing optical fiber based connectorized optical interconnection circuits (COICs). The required split connectors were injection molded from heavily filled PPS material. Reproducible mechanized fiber stripping as part of the Z-axis assembly process was incorporated and successfully tested with good results. The COICs have shown good uniform optical loss performance. It is expected that the integrated Z-axis assembly as described in this paper would prove cost effective in producing the much needed optical backplanes for large and wide-band switching, communication and computing systems.
{"title":"Optical fiber interconnections","authors":"M. Shahid, R.A. Roil","doi":"10.1109/ECTC.1996.517436","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517436","url":null,"abstract":"A Z-axis assembly process was described for producing optical fiber based connectorized optical interconnection circuits (COICs). The required split connectors were injection molded from heavily filled PPS material. Reproducible mechanized fiber stripping as part of the Z-axis assembly process was incorporated and successfully tested with good results. The COICs have shown good uniform optical loss performance. It is expected that the integrated Z-axis assembly as described in this paper would prove cost effective in producing the much needed optical backplanes for large and wide-band switching, communication and computing systems.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123900978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550509
D. Walshak, H. Hashemi, P. Mehrotra
To meet the need for future compact, efficient, high-frequency power supplies, a joint R&D effort between Harris Semiconductor and MCC was established to study the enabling technologies necessary to design a Few-Chip Module incorporating a DC-to-DC distributed power supply component set. The module consists of a Harris Power ASIC (PASIC) chip, a Schottky diode, and 12 discrete multilayer ceramic capacitors (MLCs). The package configuration discussed in this paper is a 120-lead 28/spl times/28 mm thermally-enhanced quad flat package (QFP). The package design is briefly reviewed and the thermal characterization results of the QFP implementation are discussed in detail.
为了满足未来对紧凑、高效、高频电源的需求，哈里斯半导体和中控集团建立了一项联合研发计划，研究设计包含dc - dc分布式电源组件集的少芯片模块所需的使能技术。该模块由一个Harris Power ASIC (PASIC)芯片、一个肖特基二极管和12个分立多层陶瓷电容器(mlc)组成。本文讨论的封装配置是120引脚28/spl次/ 28mm热增强四平面封装(QFP)。简要回顾了封装设计，并详细讨论了QFP实现的热表征结果。
{"title":"Thermal modeling of a few-chip module housing a DC-DC power supply","authors":"D. Walshak, H. Hashemi, P. Mehrotra","doi":"10.1109/ECTC.1996.550509","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550509","url":null,"abstract":"To meet the need for future compact, efficient, high-frequency power supplies, a joint R&D effort between Harris Semiconductor and MCC was established to study the enabling technologies necessary to design a Few-Chip Module incorporating a DC-to-DC distributed power supply component set. The module consists of a Harris Power ASIC (PASIC) chip, a Schottky diode, and 12 discrete multilayer ceramic capacitors (MLCs). The package configuration discussed in this paper is a 120-lead 28/spl times/28 mm thermally-enhanced quad flat package (QFP). The package design is briefly reviewed and the thermal characterization results of the QFP implementation are discussed in detail.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124065202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517406
K. H. Hahn, K.S. Giboney, R. E. Wilson, J. Straznicky, E. Wong, M. Tan, R. Kaneshiro, D. Dolfi, E. H. Mueller, A. Plotts, D. D. Murray, J. Marchegiano, B. Booth, B. Sano, B. Madhaven, B. Raghavan, A. Levi
The progress in the development of the 10 channel POLO (Parallel Optical Link Organization) module is described. The POLO program is a consortium of Hewlett-Packard, AMP, Du Pont, SDL, and the University of Southern California to develop low cost, high performance parallel optical data links for computer clusters, multimedia, and switching systems. The design and initial performance of the 1st generation POLO module (POLO-I) have been previously reported. In this paper, we discuss the overall results of the POLO-1 module as well as the design and implementation of the 2nd generation (POLO-2) parallel optical data link.
{"title":"Gigabyte/s data communications with the POLO parallel optical link","authors":"K. H. Hahn, K.S. Giboney, R. E. Wilson, J. Straznicky, E. Wong, M. Tan, R. Kaneshiro, D. Dolfi, E. H. Mueller, A. Plotts, D. D. Murray, J. Marchegiano, B. Booth, B. Sano, B. Madhaven, B. Raghavan, A. Levi","doi":"10.1109/ECTC.1996.517406","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517406","url":null,"abstract":"The progress in the development of the 10 channel POLO (Parallel Optical Link Organization) module is described. The POLO program is a consortium of Hewlett-Packard, AMP, Du Pont, SDL, and the University of Southern California to develop low cost, high performance parallel optical data links for computer clusters, multimedia, and switching systems. The design and initial performance of the 1st generation POLO module (POLO-I) have been previously reported. In this paper, we discuss the overall results of the POLO-1 module as well as the design and implementation of the 2nd generation (POLO-2) parallel optical data link.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129715223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517457
V. Gross, S. Voldman, W. Guthrie
Electrostatic discharge (ESD) standards, qualification and testing techniques are not keeping pace with the wide proliferation of product and package types, chip architectures, digital/analog mixed signal applications, multichip module (MCM) packages, and three-dimensional silicon packages. ESD test standards are primarily focused on impulse wave forms and testers and are not addressing the pace and changing trend of the semiconductor industry. For example, most ESD event simulators are not adequately addressing product with high pin counts, high-volume testing, and software needs. This paper discusses our perspective of those adjustments needed to drive ESD learning on product chips and of new package environments. Also discussed are ESD testing methodologies, wafer-level test systems, packaging effects, simulation, and MCM ESD testing.
{"title":"ESD qualification and testing of semiconductor electronic components","authors":"V. Gross, S. Voldman, W. Guthrie","doi":"10.1109/ECTC.1996.517457","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517457","url":null,"abstract":"Electrostatic discharge (ESD) standards, qualification and testing techniques are not keeping pace with the wide proliferation of product and package types, chip architectures, digital/analog mixed signal applications, multichip module (MCM) packages, and three-dimensional silicon packages. ESD test standards are primarily focused on impulse wave forms and testers and are not addressing the pace and changing trend of the semiconductor industry. For example, most ESD event simulators are not adequately addressing product with high pin counts, high-volume testing, and software needs. This paper discusses our perspective of those adjustments needed to drive ESD learning on product chips and of new package environments. Also discussed are ESD testing methodologies, wafer-level test systems, packaging effects, simulation, and MCM ESD testing.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127311484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550513
A. Mathis, A. Peterson
Frequently multichip modules (MCM) have perforated ground and power planes as opposed to solid ground and power planes. The periodic apertures in the planes alter how electromagnetic waves propagate in the system, and therefore must be taken into account when analyzing the system. The characteristic behavior of interconnects above a perforated ground plane is affected by the size, shape, and orientation of the apertures. To accurately model the interconnects over perforated ground planes requires the use of the periodic 3D Green's function. The Green's functions comprises two infinite series both of which converge extremely slowly, and this slow convergence of the periodic Green's function has hampered previous analysis. To overcome this obstacle a mixed domain representation of the Green's function based on the error function transformation is used. This representation of the Green's function converges exponentially in both the spatial and spectral domains. Using this representation, the Green's function can be computed accurately and in a short amount of time. Modeling the gridded ground plane is just the first step in modeling an entire system. In addition to being able to accurately model the ground plane, one must be able to model a wide variety of structures, such as multiple interconnects, discontinuities, and conformal vias. All of these models need to be verified with measurements of actual devices. Finally, in order to be effective in post-layout verification, the developed models must interface with a circuit simulator.
{"title":"Modeling and analysis of interconnects within a package incorporating vias and a perforated ground plane","authors":"A. Mathis, A. Peterson","doi":"10.1109/ECTC.1996.550513","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550513","url":null,"abstract":"Frequently multichip modules (MCM) have perforated ground and power planes as opposed to solid ground and power planes. The periodic apertures in the planes alter how electromagnetic waves propagate in the system, and therefore must be taken into account when analyzing the system. The characteristic behavior of interconnects above a perforated ground plane is affected by the size, shape, and orientation of the apertures. To accurately model the interconnects over perforated ground planes requires the use of the periodic 3D Green's function. The Green's functions comprises two infinite series both of which converge extremely slowly, and this slow convergence of the periodic Green's function has hampered previous analysis. To overcome this obstacle a mixed domain representation of the Green's function based on the error function transformation is used. This representation of the Green's function converges exponentially in both the spatial and spectral domains. Using this representation, the Green's function can be computed accurately and in a short amount of time. Modeling the gridded ground plane is just the first step in modeling an entire system. In addition to being able to accurately model the ground plane, one must be able to model a wide variety of structures, such as multiple interconnects, discontinuities, and conformal vias. All of these models need to be verified with measurements of actual devices. Finally, in order to be effective in post-layout verification, the developed models must interface with a circuit simulator.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130003129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517422
C. Le Gall, J. Qu, D. McDowell
In this paper, finite element analyses of delamination in flip chip assemblies are described. The objectives of this study were to investigate delamination at the encapsulant/chip interface along the thickness of the chip under thermal loading, and to determine the potential for interconnection failures resulting from this type of delamination. Under operating conditions, the mismatch in thermal expansion between the silicon chip of a flip chip assembly and an organic substrate subjects the solder joints to extremely large strains, which may result in premature failure of the solder connections. Although underfill encapsulation can reduce the strains in the solder joints, it results in the potential for cracking at the chip-underfill-substrate interfaces during temperature cycling. Due to the CTE mismatch, a strong interfacial shear stress concentration develops near the free edge; when this stress exceeds the bonding strength between the encapsulant and the silicon, an interface crack will initiate, may further propagate toward the encapsulated corner of the chip, and then continue along the active face of the chip. Once this adhesion is lost, the solder joints are subjected directly to the strain resulting from the CTE mismatch, and are likely to crack under thermal cycling conditions. In the model, a crack was introduced along the chip edge/encapsulant interface. The crack tip driving force was studied for chips of different sizes. The finite element method was used in the analyses in conjunction with the theory of interfacial fracture mechanics.
{"title":"Delamination cracking in encapsulated flip chips","authors":"C. Le Gall, J. Qu, D. McDowell","doi":"10.1109/ECTC.1996.517422","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517422","url":null,"abstract":"In this paper, finite element analyses of delamination in flip chip assemblies are described. The objectives of this study were to investigate delamination at the encapsulant/chip interface along the thickness of the chip under thermal loading, and to determine the potential for interconnection failures resulting from this type of delamination. Under operating conditions, the mismatch in thermal expansion between the silicon chip of a flip chip assembly and an organic substrate subjects the solder joints to extremely large strains, which may result in premature failure of the solder connections. Although underfill encapsulation can reduce the strains in the solder joints, it results in the potential for cracking at the chip-underfill-substrate interfaces during temperature cycling. Due to the CTE mismatch, a strong interfacial shear stress concentration develops near the free edge; when this stress exceeds the bonding strength between the encapsulant and the silicon, an interface crack will initiate, may further propagate toward the encapsulated corner of the chip, and then continue along the active face of the chip. Once this adhesion is lost, the solder joints are subjected directly to the strain resulting from the CTE mismatch, and are likely to crack under thermal cycling conditions. In the model, a crack was introduced along the chip edge/encapsulant interface. The crack tip driving force was studied for chips of different sizes. The finite element method was used in the analyses in conjunction with the theory of interfacial fracture mechanics.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129026352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517378
C. Lee, Won Chin, H. Pape
The transition from through-hole packages to plastic surface mount packages has witnessed the emergence of pop-corn cracking phenomenon. Despite recent improvements in packaging materials, package designs and manufacturing technologies, the pop-corn problem is still widespread throughout the semiconductor industry. This paper reports the findings of a new leadframe design as one of the synergistic factors towards improving pop-corn performance of plastic packages. The test package was a 28/spl times/28/spl times/2.4 mm moisture sensitive 144L Quad Flat Pack (QFP) employing copper-alloy as a leadframe material. The effect of plasma cleaning on the new leadframe design was investigated for improved pop-corn performance. An atomic force microscope (AFM) and contact angle method were used to characterise surfaces of leadframe and chip backside in the uncleaned acid plasma cleaned surfaces. Finite element analysis revealed that stresses in the die-attach layer can be significantly reduced by up to 70% in the new leadframe design. Compared to standard leadframe design, package measurements showed that the warpage values were 47% lower in packages assembled with the new leadframe design. Thermal performance of package was characterised by thermal resistance (O/sub JA/) measurements. The measured O/sub JA/ was similar for both standard and new leadframe designs at about 31 K/W for large chip size (12/spl times/12 mm/sup 2/). Decreasing the chip size to 8/spl times/8 mm/sup 2/ has the effect of increasing O/sub JA/ by 8% to 35 K/W for standard designs and 36% to 42 K/W for new leadframe designs. Furthermore, results showed that delamination at the interface of die-pad/moulding compound and chip backside/moulding compound after temperature cycling, pressure cooker and AE3 test were substantially reduced and/or prevented. More importantly, by simply substituting the standard leadframe design with the new leadframe design, packages can achieve IPC level 3 moisture sensitive classification with or without plasma cleaning.
{"title":"A new leadframe design solution for improved pop-corn cracking performance","authors":"C. Lee, Won Chin, H. Pape","doi":"10.1109/ECTC.1996.517378","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517378","url":null,"abstract":"The transition from through-hole packages to plastic surface mount packages has witnessed the emergence of pop-corn cracking phenomenon. Despite recent improvements in packaging materials, package designs and manufacturing technologies, the pop-corn problem is still widespread throughout the semiconductor industry. This paper reports the findings of a new leadframe design as one of the synergistic factors towards improving pop-corn performance of plastic packages. The test package was a 28/spl times/28/spl times/2.4 mm moisture sensitive 144L Quad Flat Pack (QFP) employing copper-alloy as a leadframe material. The effect of plasma cleaning on the new leadframe design was investigated for improved pop-corn performance. An atomic force microscope (AFM) and contact angle method were used to characterise surfaces of leadframe and chip backside in the uncleaned acid plasma cleaned surfaces. Finite element analysis revealed that stresses in the die-attach layer can be significantly reduced by up to 70% in the new leadframe design. Compared to standard leadframe design, package measurements showed that the warpage values were 47% lower in packages assembled with the new leadframe design. Thermal performance of package was characterised by thermal resistance (O/sub JA/) measurements. The measured O/sub JA/ was similar for both standard and new leadframe designs at about 31 K/W for large chip size (12/spl times/12 mm/sup 2/). Decreasing the chip size to 8/spl times/8 mm/sup 2/ has the effect of increasing O/sub JA/ by 8% to 35 K/W for standard designs and 36% to 42 K/W for new leadframe designs. Furthermore, results showed that delamination at the interface of die-pad/moulding compound and chip backside/moulding compound after temperature cycling, pressure cooker and AE3 test were substantially reduced and/or prevented. More importantly, by simply substituting the standard leadframe design with the new leadframe design, packages can achieve IPC level 3 moisture sensitive classification with or without plasma cleaning.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125653719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517381
N. Takahashi, N. Senba, Y. Shimada, I. Morizaki, K. Tokuno
Demand has recently increased for high packaging density and memory capacity of memory modules for electronic equipment. Our new 3-Dimensional Memory (3DM) Module satisfies this demand. This module has almost the same size as single memory packages (TSOPs: 17.4/spl times/9.22/spl times/1.2 mm) currently being used, and a package density 4 times as large. Electrical performance is better than that of TSOPs because the length of its wires is about half that of TSOP's wires. Moreover, the cost to fabricate this module is low. This paper reports the module's characteristics and fabrication process. The design concept is that next-generation memory devices will be produced by casing current mass-produced memory devices.
{"title":"3-dimensional memory module","authors":"N. Takahashi, N. Senba, Y. Shimada, I. Morizaki, K. Tokuno","doi":"10.1109/ECTC.1996.517381","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517381","url":null,"abstract":"Demand has recently increased for high packaging density and memory capacity of memory modules for electronic equipment. Our new 3-Dimensional Memory (3DM) Module satisfies this demand. This module has almost the same size as single memory packages (TSOPs: 17.4/spl times/9.22/spl times/1.2 mm) currently being used, and a package density 4 times as large. Electrical performance is better than that of TSOPs because the length of its wires is about half that of TSOP's wires. Moreover, the cost to fabricate this module is low. This paper reports the module's characteristics and fabrication process. The design concept is that next-generation memory devices will be produced by casing current mass-produced memory devices.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130653390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517466
E. Games, U. Shrivastava, J. Liao
This paper describes a method for evaluating simultaneous switching noise (SSN) of microprocessors. To control the switching of I/O buffers, the boundary scan architecture implemented on processors is employed. For this experiment, the on die periphery power supply noise was measured with up to 130 simultaneously switching output buffers. The method of exercising the device is described and the results of SSN measurement are presented.
{"title":"Package switching noise evaluation using boundary scan circuitry","authors":"E. Games, U. Shrivastava, J. Liao","doi":"10.1109/ECTC.1996.517466","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517466","url":null,"abstract":"This paper describes a method for evaluating simultaneous switching noise (SSN) of microprocessors. To control the switching of I/O buffers, the boundary scan architecture implemented on processors is employed. For this experiment, the on die periphery power supply noise was measured with up to 130 simultaneously switching output buffers. The method of exercising the device is described and the results of SSN measurement are presented.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127915246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550807
D. Shih
This paper discusses the yield analysis of the thin film wiring layers fabricated on the 127 mm multichip glass ceramic modules (MCM-D), currently used on the IBM Enterprise System/9000/sup TM/ family of computer processors. To select a suitable polyimide (PI) for the thin film wiring layer, modules were fabricated with either the BTDA-APB or the PMDA-ODA polyimide. By keeping all other processing parameters and structures the same, the wiring layers fabricated with the PMDA-ODA polyimide exhibited significantly better yield than those made of the BTDA-APB PI. The yield loss in the modules fabricated with the BTDA-APB PI occurred during thermal processing, where some of the transmission lines fabricated atop the PI were found cracked. Further investigations indicate that, during lift-off processing, the presence of a small contaminant, such as a fiber, metal flake, a particle, or polishing scratches can expose the PI to the hot N-methylpyrollidinone (NMP) solvent. Depending on the polyimide used for thin film processing, the diffusion and swelling of the PI by the low molecular weight organic solvent can potentially produce significant damage to the polyimide/Cu wiring structure and the consequent yield loss of the modules due to line opens. The magnitude of the damage was found to depend on the rate of solvent diffusion, process temperature, lift-off time and the amount of PI swelling during processing.
{"title":"Effect of polyimide processing on multichip glass ceramic module fabrications","authors":"D. Shih","doi":"10.1109/ECTC.1996.550807","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550807","url":null,"abstract":"This paper discusses the yield analysis of the thin film wiring layers fabricated on the 127 mm multichip glass ceramic modules (MCM-D), currently used on the IBM Enterprise System/9000/sup TM/ family of computer processors. To select a suitable polyimide (PI) for the thin film wiring layer, modules were fabricated with either the BTDA-APB or the PMDA-ODA polyimide. By keeping all other processing parameters and structures the same, the wiring layers fabricated with the PMDA-ODA polyimide exhibited significantly better yield than those made of the BTDA-APB PI. The yield loss in the modules fabricated with the BTDA-APB PI occurred during thermal processing, where some of the transmission lines fabricated atop the PI were found cracked. Further investigations indicate that, during lift-off processing, the presence of a small contaminant, such as a fiber, metal flake, a particle, or polishing scratches can expose the PI to the hot N-methylpyrollidinone (NMP) solvent. Depending on the polyimide used for thin film processing, the diffusion and swelling of the PI by the low molecular weight organic solvent can potentially produce significant damage to the polyimide/Cu wiring structure and the consequent yield loss of the modules due to line opens. The magnitude of the damage was found to depend on the rate of solvent diffusion, process temperature, lift-off time and the amount of PI swelling during processing.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131302859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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