Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517403
Y. Wong, D. Muehlner, C. C. Faudskar, M. Fishteyn, J. Gates, P. Anthony, G. Cyr, J. Choi, J. Crow, D. Kuchta, P. Pepeljugoski, K. Stawiasz, W. Nation, D. Engebretsen, B. Whitlock, R. Morgan, M. Hibbs-Brenner, J. Lehman, R. Walterson, E. Kalweit, T. Marta
This paper discusses the present state of the art of components, systems, and application technology related to parallel optical data links (ODL) as demonstrated by the OptoElectronic Technology Consortium (OETC). Parallel ODL technology is poised for large volume commercialization despite some uncertainties in industrial standards and system applications. This is fueled by the demand for high-bandwidth to support the upcoming information age. To meet the need for low-cost, broadband digital multimedia services, parallel ODL technology faces the challenge of providing reasonable cost/performance ratios when compared with other established technologies. Responding to this challenge has required the integration of a number of state-of-the-art component technologies (e.g. VCSEL, monolithic integrated photoreceiver, MCM, GaAs IC, optical array connector and cable) with system designs and applications.
{"title":"OptoElectronic Technology Consortium (OETC) parallel optical data link: components, system applications, and simulation tools","authors":"Y. Wong, D. Muehlner, C. C. Faudskar, M. Fishteyn, J. Gates, P. Anthony, G. Cyr, J. Choi, J. Crow, D. Kuchta, P. Pepeljugoski, K. Stawiasz, W. Nation, D. Engebretsen, B. Whitlock, R. Morgan, M. Hibbs-Brenner, J. Lehman, R. Walterson, E. Kalweit, T. Marta","doi":"10.1109/ECTC.1996.517403","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517403","url":null,"abstract":"This paper discusses the present state of the art of components, systems, and application technology related to parallel optical data links (ODL) as demonstrated by the OptoElectronic Technology Consortium (OETC). Parallel ODL technology is poised for large volume commercialization despite some uncertainties in industrial standards and system applications. This is fueled by the demand for high-bandwidth to support the upcoming information age. To meet the need for low-cost, broadband digital multimedia services, parallel ODL technology faces the challenge of providing reasonable cost/performance ratios when compared with other established technologies. Responding to this challenge has required the integration of a number of state-of-the-art component technologies (e.g. VCSEL, monolithic integrated photoreceiver, MCM, GaAs IC, optical array connector and cable) with system designs and applications.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129261583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550878
E. Chan, M. Beranek, K. W. Davido, H. Hager, C. Hong, R.L. St. Pierre
The commercial and military avionics/aerospace environment presents formidable challenges for developing and manufacturing low-cost avionics/aerospace-grade optoelectronic modules. Because manufacturing volume is relatively low, the economies of scale advantage enjoyed by commercial datacom optoelectronic module producers has yet to be realized. Currently the harsh avionics/aerospace environment obligates the hybrid designer to place highest priority on achieving very high performance and reliability, thus imposing stringent constraints for implementing potentially low-cost optoelectronic module designs in today's military/aerospace hybrid manufacturing plant. Boeing's collaborative R&D programs with commercial sector optoelectronics producers provides a solution for reducing optoelectronic module design and manufacturing production costs for future avionics/aerospace optoelectronic module applications.
{"title":"Challenges for developing low-cost avionics/aerospace-grade optoelectronic modules","authors":"E. Chan, M. Beranek, K. W. Davido, H. Hager, C. Hong, R.L. St. Pierre","doi":"10.1109/ECTC.1996.550878","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550878","url":null,"abstract":"The commercial and military avionics/aerospace environment presents formidable challenges for developing and manufacturing low-cost avionics/aerospace-grade optoelectronic modules. Because manufacturing volume is relatively low, the economies of scale advantage enjoyed by commercial datacom optoelectronic module producers has yet to be realized. Currently the harsh avionics/aerospace environment obligates the hybrid designer to place highest priority on achieving very high performance and reliability, thus imposing stringent constraints for implementing potentially low-cost optoelectronic module designs in today's military/aerospace hybrid manufacturing plant. Boeing's collaborative R&D programs with commercial sector optoelectronics producers provides a solution for reducing optoelectronic module design and manufacturing production costs for future avionics/aerospace optoelectronic module applications.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129496458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550751
J. Phillips, G. Margaritis, B. Afshari
Thermal cycling of non-underfilled C4 assemblies with polyimide shows that they are more reliable than C4 without polyimide. However, the reliability of underfilled assemblies of C4 with or without polyimide appears to be the same under thermal cycling conditions. The reason is that in non-underfilled assemblies without polyimide, the failure mode is adhesive failure of the UBM/passivation interface, with subsequent silicon cracking. In all other cases the failure mode is solder fatigue cracking. Finite Element Method analysis indicates that polyimide has no advantage over non-polyimide C4 in stress reduction at the interface. Thus, it is inferred that polyimide must enhance the adhesive strength of the system. However, such enhancement is unnecessary in underfilled systems, due to the significant decrease in the stresses from the presence of the underfill.
{"title":"An interim report on the comparisons of polymide to non-polyimide reliability for C4","authors":"J. Phillips, G. Margaritis, B. Afshari","doi":"10.1109/ECTC.1996.550751","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550751","url":null,"abstract":"Thermal cycling of non-underfilled C4 assemblies with polyimide shows that they are more reliable than C4 without polyimide. However, the reliability of underfilled assemblies of C4 with or without polyimide appears to be the same under thermal cycling conditions. The reason is that in non-underfilled assemblies without polyimide, the failure mode is adhesive failure of the UBM/passivation interface, with subsequent silicon cracking. In all other cases the failure mode is solder fatigue cracking. Finite Element Method analysis indicates that polyimide has no advantage over non-polyimide C4 in stress reduction at the interface. Thus, it is inferred that polyimide must enhance the adhesive strength of the system. However, such enhancement is unnecessary in underfilled systems, due to the significant decrease in the stresses from the presence of the underfill.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130559167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550806
P. Tehrani, Yuzbe Chen, J. Fang
A method for extraction and simulation of transient behavioral models of state transition of digital I/O buffers is introduced. This scheme increases the speed of chip interconnect simulations with large number of simultaneous switching devices, while maintaining good accuracy compared to corresponding transistor level models. This paper covers the derivation procedures of such transient state transition behavioral models from IBIS modeling data. A comparison of simulation results between these models and transistor level models (SPICE models) is also included.
{"title":"Extraction of transient behavioral model of digital I/O buffers from IBIS","authors":"P. Tehrani, Yuzbe Chen, J. Fang","doi":"10.1109/ECTC.1996.550806","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550806","url":null,"abstract":"A method for extraction and simulation of transient behavioral models of state transition of digital I/O buffers is introduced. This scheme increases the speed of chip interconnect simulations with large number of simultaneous switching devices, while maintaining good accuracy compared to corresponding transistor level models. This paper covers the derivation procedures of such transient state transition behavioral models from IBIS modeling data. A comparison of simulation results between these models and transistor level models (SPICE models) is also included.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131236893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517397
H. Chan
Corrosive contaminants left on a circuit from assembly and manufacturing processes present reliability problems. Contemporary SIR measurement procedures consist of daily resistance measurements across a comb pattern on samples that age in environmental chambers. Yet these tests lack information on the corrosiveness of the contaminants and often exhibit inconsistency as quantitative measures. A DC continuous measurement method is used here to study the fundamental science behind these measurements for ionic contaminants on a printed circuit board. For ionic contaminants, such as those left from low-solids-fluxes (LSF), the SIR values exhibited continuous and irreversible changes during the test. The DC voltage causes mobile ions to migrate towards the electrodes and are thus being depleted from the insulating surface. Hence, only the initial measurement on a virgin sample gives the true quantitative measure of these contaminants. The subsequent rise in SIR value should not be interpreted as an improvement in reliability but rather be indicative of the presence of mobile ions which might be corrosive. Once the board is depleted of ions, reversing the applied voltage polarity cannot restore the initially low SIR value, but only gives a very slow drop followed by a very slow rise in the SIR value. These changes are responsible for many measurement anomaly commonly observed under various DC biasing schemes where the SIR values are recorded only once daily. An alternate SIR methodology using AC measurement is shown to give more consistent results. The AC voltage causes no net ion migration but may still cause voltage-accelerated aging. While this work uses printed circuit board as a test vehicle, the fundamental science is applicable to Hibrid IC and to other processes where cleanliness is needed for reliability.
{"title":"Is the current surface insulation resistance (SIR) methodology appropriate to today's manufacturing technology?","authors":"H. Chan","doi":"10.1109/ECTC.1996.517397","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517397","url":null,"abstract":"Corrosive contaminants left on a circuit from assembly and manufacturing processes present reliability problems. Contemporary SIR measurement procedures consist of daily resistance measurements across a comb pattern on samples that age in environmental chambers. Yet these tests lack information on the corrosiveness of the contaminants and often exhibit inconsistency as quantitative measures. A DC continuous measurement method is used here to study the fundamental science behind these measurements for ionic contaminants on a printed circuit board. For ionic contaminants, such as those left from low-solids-fluxes (LSF), the SIR values exhibited continuous and irreversible changes during the test. The DC voltage causes mobile ions to migrate towards the electrodes and are thus being depleted from the insulating surface. Hence, only the initial measurement on a virgin sample gives the true quantitative measure of these contaminants. The subsequent rise in SIR value should not be interpreted as an improvement in reliability but rather be indicative of the presence of mobile ions which might be corrosive. Once the board is depleted of ions, reversing the applied voltage polarity cannot restore the initially low SIR value, but only gives a very slow drop followed by a very slow rise in the SIR value. These changes are responsible for many measurement anomaly commonly observed under various DC biasing schemes where the SIR values are recorded only once daily. An alternate SIR methodology using AC measurement is shown to give more consistent results. The AC voltage causes no net ion migration but may still cause voltage-accelerated aging. While this work uses printed circuit board as a test vehicle, the fundamental science is applicable to Hibrid IC and to other processes where cleanliness is needed for reliability.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128875545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517407
Y.S. Liu, R. Wojnarowski, W. Hennessy, J. Bristow, Yue Liu, A. Peczalski, J. Rowlette, A. Plotts, J. Stack, M. Kadar-Kallen, J. Yardley, L. Eldada, R. Osgood, R. Scarmozzino, S.H. Lee, V. Ozgus, S. Patra
The Polymer Optical interconnect Technology (POINT) is a collaborative program among GE, Honeywell, AMP, AlliedSignal, Columbia University and University of California at San Diego (UCSD), sponsored by ARPA, in developing affordable optoelectronic packaging and interconnect technologies for board- and backplane-level optical interconnect applications. The POINT program leverages on the existing electronic design, processing, fabrication and MCM packaging technologies to optoelectronic packaging. The POINT program also incorporates several state-of-the-art optoelectronic technologies that include: high speed VCSEL for multi-channel data transmission; flexible optical polymer waveguides and low-loss polymers for board and backplane interconnects; low-cost diffractive optical elements (DOE) for board-to-backplane interconnect; and use of molded MT-type connectors to reduce weight and size. In addition, to further reduce design and fabrication cycle times, CAD tools for multimode optical waveguide modelling, and for mechanical modelling of optoelectronic packaging will be employed to aid the technology development.
{"title":"Polymer optical interconnect technology (POINT) optoelectronic packaging and interconnect for board and backplane applications","authors":"Y.S. Liu, R. Wojnarowski, W. Hennessy, J. Bristow, Yue Liu, A. Peczalski, J. Rowlette, A. Plotts, J. Stack, M. Kadar-Kallen, J. Yardley, L. Eldada, R. Osgood, R. Scarmozzino, S.H. Lee, V. Ozgus, S. Patra","doi":"10.1109/ECTC.1996.517407","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517407","url":null,"abstract":"The Polymer Optical interconnect Technology (POINT) is a collaborative program among GE, Honeywell, AMP, AlliedSignal, Columbia University and University of California at San Diego (UCSD), sponsored by ARPA, in developing affordable optoelectronic packaging and interconnect technologies for board- and backplane-level optical interconnect applications. The POINT program leverages on the existing electronic design, processing, fabrication and MCM packaging technologies to optoelectronic packaging. The POINT program also incorporates several state-of-the-art optoelectronic technologies that include: high speed VCSEL for multi-channel data transmission; flexible optical polymer waveguides and low-loss polymers for board and backplane interconnects; low-cost diffractive optical elements (DOE) for board-to-backplane interconnect; and use of molded MT-type connectors to reduce weight and size. In addition, to further reduce design and fabrication cycle times, CAD tools for multimode optical waveguide modelling, and for mechanical modelling of optoelectronic packaging will be employed to aid the technology development.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123767563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517435
G. Grimes, J. Markush, Y. Wong, P. Anthony, W. R. Holland, E.G. Priest, C. J. Sherman, S. Peck, D. Muehlner, C. C. Faudskar, J.S. Nyquist, J.S. Helton, G.L. Sonnier, J. Gates, W. Honea, J. R. Bortolini
The topic of this paper is a description of how we replaced the discrete optoelectronic and passive optics devices of the optical interconnection system of a DAGS VI-2000 with parallel optical components developed by the OETC. We have demonstrated that the use of parallel optics components, including high density laser transmitters, high density receivers and high density multifiber backplane connectors are compatible with standard electronic packaging technologies for large telecommunications platforms. We have further demonstrated that the use of parallel optics can dramatically increase system capacity with minimal impact on system physical architecture.
{"title":"Photonic packaging using laser/receiver arrays and flexible optical circuits","authors":"G. Grimes, J. Markush, Y. Wong, P. Anthony, W. R. Holland, E.G. Priest, C. J. Sherman, S. Peck, D. Muehlner, C. C. Faudskar, J.S. Nyquist, J.S. Helton, G.L. Sonnier, J. Gates, W. Honea, J. R. Bortolini","doi":"10.1109/ECTC.1996.517435","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517435","url":null,"abstract":"The topic of this paper is a description of how we replaced the discrete optoelectronic and passive optics devices of the optical interconnection system of a DAGS VI-2000 with parallel optical components developed by the OETC. We have demonstrated that the use of parallel optics components, including high density laser transmitters, high density receivers and high density multifiber backplane connectors are compatible with standard electronic packaging technologies for large telecommunications platforms. We have further demonstrated that the use of parallel optics can dramatically increase system capacity with minimal impact on system physical architecture.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124350342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517413
B. Daigle
Designers are moving towards material systems which can be fabricated using conventional epoxy/glass printed circuit board (PCB) processes. This allows microwave circuits to be built using the vast fabrication infrastructure available for digital circuits. This paper provides basic background information about substrate material characteristics and design considerations, which are critical for wireless applications. Material characteristics discussed include dissipation factor, dielectric constant tolerances and stability. Design and material options which allow microwave circuits to be manufactured by conventional FR4 fabricators are emphasized.
{"title":"Printed circuit board material and design considerations for wireless applications","authors":"B. Daigle","doi":"10.1109/ECTC.1996.517413","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517413","url":null,"abstract":"Designers are moving towards material systems which can be fabricated using conventional epoxy/glass printed circuit board (PCB) processes. This allows microwave circuits to be built using the vast fabrication infrastructure available for digital circuits. This paper provides basic background information about substrate material characteristics and design considerations, which are critical for wireless applications. Material characteristics discussed include dissipation factor, dielectric constant tolerances and stability. Design and material options which allow microwave circuits to be manufactured by conventional FR4 fabricators are emphasized.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127837965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517454
S. Kadakia, A. Agrawal
The objective of this paper is to focus on design considerations and on design methodology for high performance packages. Discussion will be restricted to Single Chip Packages only. Wirebond and Flip chip packages in Pin Grid and Ball Grid I/Os are described here. As shown here design considerations are primarily driven by customer input followed by electrical modeling and process modeling to guarantee performance and cost. The electrical performance of the package is analyzed by evaluating the parasitic parameters.
{"title":"Design trade-offs in high performance packages","authors":"S. Kadakia, A. Agrawal","doi":"10.1109/ECTC.1996.517454","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517454","url":null,"abstract":"The objective of this paper is to focus on design considerations and on design methodology for high performance packages. Discussion will be restricted to Single Chip Packages only. Wirebond and Flip chip packages in Pin Grid and Ball Grid I/Os are described here. As shown here design considerations are primarily driven by customer input followed by electrical modeling and process modeling to guarantee performance and cost. The electrical performance of the package is analyzed by evaluating the parasitic parameters.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127916150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517371
Q. Tan, Y.C. Lee
Soldering technology for optoelectronic packaging is reviewed by studying modules in four categories: solder assembly with no precision self-alignments, and self-aligned solder assembly with no, one or two mechanical stops. There have been at least 60 papers and 8 U.S. patents published between 1990 and 1995. In addition to die-attachments, soldering technology has been successfully demonstrated for precision alignments. However, some packaging issues may hamper the progress of its manufacturing insertion for wide applications. Four of the issues to be discussed are solder materials, fluxless reflow, design, and reliability. More studies on these issues are needed to support the advancement of optoelectronic packaging for low-cost, high-performance and high-reliability modules.
{"title":"Soldering technology for optoelectronic packaging","authors":"Q. Tan, Y.C. Lee","doi":"10.1109/ECTC.1996.517371","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517371","url":null,"abstract":"Soldering technology for optoelectronic packaging is reviewed by studying modules in four categories: solder assembly with no precision self-alignments, and self-aligned solder assembly with no, one or two mechanical stops. There have been at least 60 papers and 8 U.S. patents published between 1990 and 1995. In addition to die-attachments, soldering technology has been successfully demonstrated for precision alignments. However, some packaging issues may hamper the progress of its manufacturing insertion for wide applications. Four of the issues to be discussed are solder materials, fluxless reflow, design, and reliability. More studies on these issues are needed to support the advancement of optoelectronic packaging for low-cost, high-performance and high-reliability modules.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133988993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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