Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550757
T. Cho, Kyujin Lee, Min-Ho Lee, Seung-Ho Ahn, S. Oh
The influence of die pad design and die attach adhesive on the resistance of a thin small out line package (TSOP) to reflow cracking has been investigated. Mechanisms of reflow cracking were studied using scanning acoustic tomography (SAT) and scanning electron micrography (SEM). For more precise analysis, computational calculations of stress were conducted. In the case of dimpled die pad, an experimental die adhesive with lower moisture absorption and higher adhesion strength showed excellent resistance to reflow cracking, resulting in crack-free performance in level I preconditioning tests. However,packages with the slot lead frame failed in level I preconditioning tests. The failure was due to the interfacial delamination between the bottom surface of die and the epoxy molding compound (EMC). SAT showed that the delamination initiated at the periphery of the slot during temperature cycling in preconditioning. During the subsequent soaking and IR reflow, moisture condensed at the delaminated interface generated the high vapour pressure that exceeded the fracture strength of the EMC. In other words, the interfacial integrity between the bottom surface of die and the molding compound is critical to the reflow cracking in packages with slot lead frame.
{"title":"An improvement in reflow performance of plastic packages","authors":"T. Cho, Kyujin Lee, Min-Ho Lee, Seung-Ho Ahn, S. Oh","doi":"10.1109/ECTC.1996.550757","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550757","url":null,"abstract":"The influence of die pad design and die attach adhesive on the resistance of a thin small out line package (TSOP) to reflow cracking has been investigated. Mechanisms of reflow cracking were studied using scanning acoustic tomography (SAT) and scanning electron micrography (SEM). For more precise analysis, computational calculations of stress were conducted. In the case of dimpled die pad, an experimental die adhesive with lower moisture absorption and higher adhesion strength showed excellent resistance to reflow cracking, resulting in crack-free performance in level I preconditioning tests. However,packages with the slot lead frame failed in level I preconditioning tests. The failure was due to the interfacial delamination between the bottom surface of die and the epoxy molding compound (EMC). SAT showed that the delamination initiated at the periphery of the slot during temperature cycling in preconditioning. During the subsequent soaking and IR reflow, moisture condensed at the delaminated interface generated the high vapour pressure that exceeded the fracture strength of the EMC. In other words, the interfacial integrity between the bottom surface of die and the molding compound is critical to the reflow cracking in packages with slot lead frame.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126713781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550496
A. Tay, T.Y. Lin
Some studies have indicated that "popcorn" cracking of plastic IC packages during solder reflow is due to excessive stress caused by the vaporization of moisture in the interface between the die pad and the plastic encapsulant. The numerical stress analyses done to date, however, have assumed that the vapor pressure in the delaminated pad-encapsulant is equal to the saturation pressure corresponding to the temperature at the interface during solder reflow. In fact, this vapor pressure in the delamination is developed gradually by the diffusion of moisture into the delamination. In this paper, this transient pressure rise at the delaminated pad-encapsulant interface is obtained using finite element simulation of the heat and moisture diffusion processes that occur simultaneously. It is shown that the maximum vapor pressure developed in the delamination is much lower than the saturation pressure values assumed by other researchers. However, even at this lower vapor pressure, it is shown using finite element analysis employing a crack-tip element, that the maximum principal stress developed in the encapsulant exceeds its strength. Thus, cracking of the encapsulant would still occur. It is also shown that delamination of the pad-encapsulant interface is necessary condition for package cracking. More significantly, it is established that the primary effect of moisture in "popcorn" cracking is the degradation of the adhesion of the pad-encapsulant interface, and not so much the increase in stress due to moisture vaporizing in the delaminated interface.
{"title":"Effects of moisture and delamination on cracking of plastic IC packages during solder reflow","authors":"A. Tay, T.Y. Lin","doi":"10.1109/ECTC.1996.550496","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550496","url":null,"abstract":"Some studies have indicated that \"popcorn\" cracking of plastic IC packages during solder reflow is due to excessive stress caused by the vaporization of moisture in the interface between the die pad and the plastic encapsulant. The numerical stress analyses done to date, however, have assumed that the vapor pressure in the delaminated pad-encapsulant is equal to the saturation pressure corresponding to the temperature at the interface during solder reflow. In fact, this vapor pressure in the delamination is developed gradually by the diffusion of moisture into the delamination. In this paper, this transient pressure rise at the delaminated pad-encapsulant interface is obtained using finite element simulation of the heat and moisture diffusion processes that occur simultaneously. It is shown that the maximum vapor pressure developed in the delamination is much lower than the saturation pressure values assumed by other researchers. However, even at this lower vapor pressure, it is shown using finite element analysis employing a crack-tip element, that the maximum principal stress developed in the encapsulant exceeds its strength. Thus, cracking of the encapsulant would still occur. It is also shown that delamination of the pad-encapsulant interface is necessary condition for package cracking. More significantly, it is established that the primary effect of moisture in \"popcorn\" cracking is the degradation of the adhesion of the pad-encapsulant interface, and not so much the increase in stress due to moisture vaporizing in the delaminated interface.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126881630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517418
J. Scalise
Microcircuit package qualification testing is used to establish the reliability of integrated circuit processes and devices as they relate to part packaging. This paper presents the results of package qualification tests conducted on plastic encapsulated microcircuits (PEMs) and plastic discrete devices (diodes, transistors) used in avionics applications. Highly Accelerated Stress Test (HAST) and temperature cycle (TC) test results, including part failure mechanisms and associated failure rates, are provided. A variety of plastic package styles and integrated circuit functions have been tested. Examples of package styles tested include: small outline (SO), plastic leaded chip carrier (PLCC), thin small outline package (TSOP), plastic quad flat package (PQFP), and plastic dual-in-line (PDIP). Manufacturers' devices have been evaluated and various plastic compounds have been compared to determine which provide optimum reliability. The testing showed that package qualification performance of PEMs is affected by: type of compound, passivation (including die coat), and die size. HAST failures are caused by moisture penetration of the package while temperature cycle failures result from coefficient of thermal expansion (CTE) mismatch effects.
{"title":"Plastic encapsulated microcircuits (PEM) qualification testing","authors":"J. Scalise","doi":"10.1109/ECTC.1996.517418","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517418","url":null,"abstract":"Microcircuit package qualification testing is used to establish the reliability of integrated circuit processes and devices as they relate to part packaging. This paper presents the results of package qualification tests conducted on plastic encapsulated microcircuits (PEMs) and plastic discrete devices (diodes, transistors) used in avionics applications. Highly Accelerated Stress Test (HAST) and temperature cycle (TC) test results, including part failure mechanisms and associated failure rates, are provided. A variety of plastic package styles and integrated circuit functions have been tested. Examples of package styles tested include: small outline (SO), plastic leaded chip carrier (PLCC), thin small outline package (TSOP), plastic quad flat package (PQFP), and plastic dual-in-line (PDIP). Manufacturers' devices have been evaluated and various plastic compounds have been compared to determine which provide optimum reliability. The testing showed that package qualification performance of PEMs is affected by: type of compound, passivation (including die coat), and die size. HAST failures are caused by moisture penetration of the package while temperature cycle failures result from coefficient of thermal expansion (CTE) mismatch effects.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126901753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550891
C. K. Yeo, S. Mhaisalkar, H. Pang
In this paper, a comprehensive experimental and numerical study of the solder joint reliability for 256 pin, 0.4 mm pitch Plastic Quad Flat Packs (PQFPs) are presented. The reliability of solder joints were assessed through accelerated lifetime testing under the temperature range of -55/spl deg/C to 125/spl deg/C. Sample were progressively taken out at 1000 cycles intervals to study the change in microstructure such as grain coarsening, growth of intermetallics, initiation and propagation of thermal fatigue cracks. Temperature cycling results were modeled by 3-parameter Weibull distribution. The deformation history of solder joints was analyzed by three dimensional non-linear finite element method (FEM) involving thermal elastic-plastic-creep simulation. The plastic and creep strain ranges were used in life prediction models and compared to the experimental results. Satisfactory correlation was observed.
{"title":"Solder joint reliability study of 256 pin, 0.4 mm pitch, PQFP","authors":"C. K. Yeo, S. Mhaisalkar, H. Pang","doi":"10.1109/ECTC.1996.550891","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550891","url":null,"abstract":"In this paper, a comprehensive experimental and numerical study of the solder joint reliability for 256 pin, 0.4 mm pitch Plastic Quad Flat Packs (PQFPs) are presented. The reliability of solder joints were assessed through accelerated lifetime testing under the temperature range of -55/spl deg/C to 125/spl deg/C. Sample were progressively taken out at 1000 cycles intervals to study the change in microstructure such as grain coarsening, growth of intermetallics, initiation and propagation of thermal fatigue cracks. Temperature cycling results were modeled by 3-parameter Weibull distribution. The deformation history of solder joints was analyzed by three dimensional non-linear finite element method (FEM) involving thermal elastic-plastic-creep simulation. The plastic and creep strain ranges were used in life prediction models and compared to the experimental results. Satisfactory correlation was observed.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123194937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550765
S. Nimmagadda, J. Dillon, A. Moncayo
A bus with a novel modularity and termination scheme is described. The modular bus, referred to as the Y Channel, provides a bandwidth of 533 MBits/sec/wire and operates with either single or double parallel termination. Y Channel has a termination on the mother board and another termination on the optional expansion module. The impedance of the bus changes when the module is inserted. To maintain a constant voltage swing on the bus in both the cases (i.e. with and without the module), the device currents are automatically scaled. This scheme eliminates the need for dummy terminator modules that are normally used in high speed buses as place holders for future expansion. Y Channel has been verified through Spice simulations and with test hardware and has been successfully implemented in real system applications.
{"title":"A 533 MBits/sec/wire modular bus with single or double parallel termination","authors":"S. Nimmagadda, J. Dillon, A. Moncayo","doi":"10.1109/ECTC.1996.550765","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550765","url":null,"abstract":"A bus with a novel modularity and termination scheme is described. The modular bus, referred to as the Y Channel, provides a bandwidth of 533 MBits/sec/wire and operates with either single or double parallel termination. Y Channel has a termination on the mother board and another termination on the optional expansion module. The impedance of the bus changes when the module is inserted. To maintain a constant voltage swing on the bus in both the cases (i.e. with and without the module), the device currents are automatically scaled. This scheme eliminates the need for dummy terminator modules that are normally used in high speed buses as place holders for future expansion. Y Channel has been verified through Spice simulations and with test hardware and has been successfully implemented in real system applications.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121461588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517380
Seung-Ho Ahn, T. Cho, Yoon-Soo Kim, S. Oh
One of the methods to prevent the moisture concentration, which can promote the corrosion of aluminum is to remove the space around the aluminum bonding pad. In other words, the perfect adhesion without delamination between the integrated circuit chip and the molding compound would not allow the electrolyte formation, and the aluminum pad corrosion. UV/ozone cleaning of the chip was thought to be able to strengthen the chip-molding compound adhesion. In this work, the effectiveness of UV/ozone cleaning in the prevention of aluminum pad corrosion, and the relationship between the delamination and the corrosion were investigated.
{"title":"Prevention of aluminum pad corrosion by UV/ozone cleaning","authors":"Seung-Ho Ahn, T. Cho, Yoon-Soo Kim, S. Oh","doi":"10.1109/ECTC.1996.517380","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517380","url":null,"abstract":"One of the methods to prevent the moisture concentration, which can promote the corrosion of aluminum is to remove the space around the aluminum bonding pad. In other words, the perfect adhesion without delamination between the integrated circuit chip and the molding compound would not allow the electrolyte formation, and the aluminum pad corrosion. UV/ozone cleaning of the chip was thought to be able to strengthen the chip-molding compound adhesion. In this work, the effectiveness of UV/ozone cleaning in the prevention of aluminum pad corrosion, and the relationship between the delamination and the corrosion were investigated.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"17 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113943792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550882
B. Chandran, W. F. Schmidt, M. Gordon
Thermal expansion mismatch between electronic devices and their substrates induces stresses in the assembly during bonding and operation. These stresses in extreme cases cause cracking of the electronic device during bonding. For GaAs devices back-side bonded to a high conductivity artificial diamond substrate using Au-Sn solder, analytical and numerical analyses were conducted to determine the bonding stresses in the GaAs die. Bonding experiments were conducted to study the effect of varying cooling rates on die failure. Experimental data demonstrate that only smaller sized dice (1 mm/spl times/1 mm and 2 mm/spl times/2 mm) survived bonding without cracking. This observation was corroborated by analytical and numerical studies which show that the stress induced in the larger dice exceeded the strength of the material. Slow (/spl ap/2/spl deg/C/min) but continuous cooling from the bonding temperature did not improve the survival rate of the dice significantly. A new cooling scheme was developed utilizing the high temperature creep properties of the Au-Sn solder. This cooling scheme incorporates solder layer creep at high temperatures to relieve the stresses in the attached die. Bonding experiments with sizes up to 10 mm/spl times/10 mm and thicknesses down to 4 mils were performed with a 100% survival rate of the dice.
{"title":"A novel bonding technique to bond CTE mismatched devices","authors":"B. Chandran, W. F. Schmidt, M. Gordon","doi":"10.1109/ECTC.1996.550882","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550882","url":null,"abstract":"Thermal expansion mismatch between electronic devices and their substrates induces stresses in the assembly during bonding and operation. These stresses in extreme cases cause cracking of the electronic device during bonding. For GaAs devices back-side bonded to a high conductivity artificial diamond substrate using Au-Sn solder, analytical and numerical analyses were conducted to determine the bonding stresses in the GaAs die. Bonding experiments were conducted to study the effect of varying cooling rates on die failure. Experimental data demonstrate that only smaller sized dice (1 mm/spl times/1 mm and 2 mm/spl times/2 mm) survived bonding without cracking. This observation was corroborated by analytical and numerical studies which show that the stress induced in the larger dice exceeded the strength of the material. Slow (/spl ap/2/spl deg/C/min) but continuous cooling from the bonding temperature did not improve the survival rate of the dice significantly. A new cooling scheme was developed utilizing the high temperature creep properties of the Au-Sn solder. This cooling scheme incorporates solder layer creep at high temperatures to relieve the stresses in the attached die. Bonding experiments with sizes up to 10 mm/spl times/10 mm and thicknesses down to 4 mils were performed with a 100% survival rate of the dice.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121826749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517368
W. Hunziker, W. Vogt, H. Melchior, R. Germann, C. Harder
A passive self-aligned packaging technique for semiconductor laser arrays has been realized. Alignment trenches on the laser chip are introduced to enable self-alignment to optical fibers during flip-chip mounting on a structured Si motherboard. The use of the etched Si sidewalls for alignment results in a self-positioning effect, reducing device placing precision, and allows larger tolerances in the motherboard processing. Arrays of 4, 8 and 12 lasers have been flip-chip mounted with a coupling efficiency of -3.4/spl plusmn/0.2 dB to cleaved 50/125 /spl mu/m multimode fiber (MMF) ribbons. The excess loss due to the optical mounting process is <0.3 dB. Coupling to lensed MMF's results in 1.3/spl plusmn/0.2 dB coupling loss. The laser characteristics, such as threshold current and efficiency remain unchanged during packaging and show a very low temperature dependence. A characteristic temperature of 170 K in the range of 25/spl deg/C to 75/spl deg/C opens the possibility for applications of these laser modules without active temperature control. Together with the short assembly times of the passive self-alignment, the described technology is very promising for low-cost laser array modules.
{"title":"Low cost packaging of semiconductor laser arrays using passive self-aligned flip-chip technique on Si motherboard","authors":"W. Hunziker, W. Vogt, H. Melchior, R. Germann, C. Harder","doi":"10.1109/ECTC.1996.517368","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517368","url":null,"abstract":"A passive self-aligned packaging technique for semiconductor laser arrays has been realized. Alignment trenches on the laser chip are introduced to enable self-alignment to optical fibers during flip-chip mounting on a structured Si motherboard. The use of the etched Si sidewalls for alignment results in a self-positioning effect, reducing device placing precision, and allows larger tolerances in the motherboard processing. Arrays of 4, 8 and 12 lasers have been flip-chip mounted with a coupling efficiency of -3.4/spl plusmn/0.2 dB to cleaved 50/125 /spl mu/m multimode fiber (MMF) ribbons. The excess loss due to the optical mounting process is <0.3 dB. Coupling to lensed MMF's results in 1.3/spl plusmn/0.2 dB coupling loss. The laser characteristics, such as threshold current and efficiency remain unchanged during packaging and show a very low temperature dependence. A characteristic temperature of 170 K in the range of 25/spl deg/C to 75/spl deg/C opens the possibility for applications of these laser modules without active temperature control. Together with the short assembly times of the passive self-alignment, the described technology is very promising for low-cost laser array modules.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115829963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517377
Y. Inoue, K. Sawada, N. Kawamura, T. Sudo
A synthetic criterion to provide guidance for the high-reliability structure design for the level-1 crack-free package is introduced. The criterion reflects a consideration of both delamination and package cracking. According to the criterion, to prevent delamination is the most effective means to realize the level-1 crack-free package for large chips (ex. 15 mm square). Therefore, a new package structure, a chip side support (CSS) structure which eliminates a die-pad is proposed and reliability tests are carried out. The CSS package realizes the level-1 crack-free package without moisture-proof packing.
{"title":"A synthetic criterion for level-1 crack-free package-proposal of a superior package structure","authors":"Y. Inoue, K. Sawada, N. Kawamura, T. Sudo","doi":"10.1109/ECTC.1996.517377","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517377","url":null,"abstract":"A synthetic criterion to provide guidance for the high-reliability structure design for the level-1 crack-free package is introduced. The criterion reflects a consideration of both delamination and package cracking. According to the criterion, to prevent delamination is the most effective means to realize the level-1 crack-free package for large chips (ex. 15 mm square). Therefore, a new package structure, a chip side support (CSS) structure which eliminates a die-pad is proposed and reliability tests are carried out. The CSS package realizes the level-1 crack-free package without moisture-proof packing.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131446832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517392
J. Parry, H. Rosten, G. Kromann
Thermal resistance networks or "compact" models of the PowerPC 603 and PowerPC 604 microprocessors in controlled-collapsed-chip-connection/ceramic-ball-grid-array (C4/CBGA) single-chip package are derived from "detailed" three-dimensional conduction models of the parts by both analytical and data fitting techniques. The behavioral correctness of these models is assessed by comparing the die-junction temperatures predicted for the compact model with the detailed model results for a range of boundary conditions applied at the surfaces of the package. The performance of these models is then verified by comparing the detailed and compact models in an application-specific environment (a wind tunnel) using a computational-fluid dynamics program. The interaction between the package and its environment is also discussed. The work reported here forms part of a long term European research program to create and validate generic thermal models of a range of electronic parts.
{"title":"The development of component-level thermal compact models of a C4/CBGA interconnect technology: the Motorola PowerPC 603/sup TM/ and PowerPC 604/sup TM/ RISC microprocessors","authors":"J. Parry, H. Rosten, G. Kromann","doi":"10.1109/ECTC.1996.517392","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517392","url":null,"abstract":"Thermal resistance networks or \"compact\" models of the PowerPC 603 and PowerPC 604 microprocessors in controlled-collapsed-chip-connection/ceramic-ball-grid-array (C4/CBGA) single-chip package are derived from \"detailed\" three-dimensional conduction models of the parts by both analytical and data fitting techniques. The behavioral correctness of these models is assessed by comparing the die-junction temperatures predicted for the compact model with the detailed model results for a range of boundary conditions applied at the surfaces of the package. The performance of these models is then verified by comparing the detailed and compact models in an application-specific environment (a wind tunnel) using a computational-fluid dynamics program. The interaction between the package and its environment is also discussed. The work reported here forms part of a long term European research program to create and validate generic thermal models of a range of electronic parts.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131517548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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