Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517370
Y. Nakasuga, T. Hashimoto, Y. Yamada, H. Terui, M. Yanagisawa, K. Moriwaki, Y. Akahori, Y. Tohmori, K. Kato, S. Sekine, M. Horiguchi
A multi-chip hybrid integration technique on a planar lightwave circuit (PLC) platform achieves bonding accuracy of better than 1.0 /spl mu/m and adequate bonding strength. This procedure consists of a chip-by-chip alignment step and a simultaneous solder reflowing step. In the chip-by-chip assembly step, opto-electronic chips were successively placed at their optimum positions by passive alignment while keeping the platform temperature below the solder melting point. In the solder reflowing step, all chips were bonded simultaneously by reflowing the solder. This procedure was used to Fabricate a transceiver module consisting of a Y-branch PLC and three optical devices: a spot-size converted laser diode as a transmitter, a monitor photodetector, and a waveguide photodetector as a receiver. These chips were integrated in a small area of only 1.3 mm/spl times/2.0 mm with an accuracy of 1.0 /spl mu/m. This demonstrates the potential of this procedure for fabricating highly functional and low-cost optical modules.
{"title":"Multi-chip hybrid integration on PLC platform using passive alignment technique","authors":"Y. Nakasuga, T. Hashimoto, Y. Yamada, H. Terui, M. Yanagisawa, K. Moriwaki, Y. Akahori, Y. Tohmori, K. Kato, S. Sekine, M. Horiguchi","doi":"10.1109/ECTC.1996.517370","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517370","url":null,"abstract":"A multi-chip hybrid integration technique on a planar lightwave circuit (PLC) platform achieves bonding accuracy of better than 1.0 /spl mu/m and adequate bonding strength. This procedure consists of a chip-by-chip alignment step and a simultaneous solder reflowing step. In the chip-by-chip assembly step, opto-electronic chips were successively placed at their optimum positions by passive alignment while keeping the platform temperature below the solder melting point. In the solder reflowing step, all chips were bonded simultaneously by reflowing the solder. This procedure was used to Fabricate a transceiver module consisting of a Y-branch PLC and three optical devices: a spot-size converted laser diode as a transmitter, a monitor photodetector, and a waveguide photodetector as a receiver. These chips were integrated in a small area of only 1.3 mm/spl times/2.0 mm with an accuracy of 1.0 /spl mu/m. This demonstrates the potential of this procedure for fabricating highly functional and low-cost optical modules.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129658851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517414
L. Schaper, G. Morcan
The increased frequency operation of CMOS microprocessors and other circuitry places severe demands on power distribution systems to supply stable, noise-free power. Particularly in MCMs, where short signal line lengths allow fast off-chip switching, improved decoupling capacitors are required for short-term charge storage to reduce dI/dt noise. This paper examines the relative parasitic contributions of off-chip connections, MCM power distribution planes, and decoupling capacitors, and the effect of these parasitics on power distribution integrity. It is shown that the effect of the inductances of chip-to-substrate interconnections can be minimized by using multiple interconnections and careful design both in a wirebond or in a flip chip environment. Similarly, the intrinsic inductance and resistance of power distribution planes, either solid, perforated, or the new IMPS (Interconnected Mesh Power System), is extremely low and does not determine the effectiveness of power distribution.
{"title":"High frequency characteristics of MCM decoupling capacitors","authors":"L. Schaper, G. Morcan","doi":"10.1109/ECTC.1996.517414","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517414","url":null,"abstract":"The increased frequency operation of CMOS microprocessors and other circuitry places severe demands on power distribution systems to supply stable, noise-free power. Particularly in MCMs, where short signal line lengths allow fast off-chip switching, improved decoupling capacitors are required for short-term charge storage to reduce dI/dt noise. This paper examines the relative parasitic contributions of off-chip connections, MCM power distribution planes, and decoupling capacitors, and the effect of these parasitics on power distribution integrity. It is shown that the effect of the inductances of chip-to-substrate interconnections can be minimized by using multiple interconnections and careful design both in a wirebond or in a flip chip environment. Similarly, the intrinsic inductance and resistance of power distribution planes, either solid, perforated, or the new IMPS (Interconnected Mesh Power System), is extremely low and does not determine the effectiveness of power distribution.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129696478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.551419
B. Rosner, J. Liu, Z. Lai
In this paper results of investigations concerning the reliability of adhesive bumps are presented. These bumps interconnect test flip chips with different sizes to both Al/sub 2/O/sub 3/ and FR4 substrates. The samples have been exposed to thermal cycling. The transition resistance of the bumps [TRR], and the resistance of daisy chains as criteria of the interconnection's quality, have been measured at different time instances of the environmental stress. Ag migration investigations were also carried out. This study shows that there is no reliable adhesive bump interconnection without the use of underfill material.
{"title":"Flip chip bonding using isotropically conductive adhesives","authors":"B. Rosner, J. Liu, Z. Lai","doi":"10.1109/ECTC.1996.551419","DOIUrl":"https://doi.org/10.1109/ECTC.1996.551419","url":null,"abstract":"In this paper results of investigations concerning the reliability of adhesive bumps are presented. These bumps interconnect test flip chips with different sizes to both Al/sub 2/O/sub 3/ and FR4 substrates. The samples have been exposed to thermal cycling. The transition resistance of the bumps [TRR], and the resistance of daisy chains as criteria of the interconnection's quality, have been measured at different time instances of the environmental stress. Ag migration investigations were also carried out. This study shows that there is no reliable adhesive bump interconnection without the use of underfill material.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130318064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517439
T. Wu, Y. Tsukada, W.T. Chen
The strength of flip chip organic packaging technology rests upon the knowledge and manufacturing base of C4 solder bump chip interconnection, and printed circuit technology infrastructure. The key innovation was the underfill encapsulation between the chip and the laminate which overcame the road-block of low cycle fatigue of C4 solder bump due to large CTE difference between silicon and laminate. The advent of SLC (surface laminar circuit) innovation extends the flip chip technology to higher solder bump density and larger chip I/O expected for future generations of semiconductors. The flip chip packages contain new materials, interfaces, and new processes which in turn govern the mechanical integrity of the packaging module and module card assembly. The increasing pervasiveness of electronic packages requires meeting new sets of environments. It is important to have a good understanding of materials, interface, metrology and mechanics issues related to organic packages, and how to apply this understanding in the modelling of design, process and reliability of flip chip. This paper will deliver an overview of some of the key technical challenges associated with materials and mechanics in FCA (flip-chip attach) assembly on organic carriers.
{"title":"Materials and mechanics issues in flip-chip organic packaging","authors":"T. Wu, Y. Tsukada, W.T. Chen","doi":"10.1109/ECTC.1996.517439","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517439","url":null,"abstract":"The strength of flip chip organic packaging technology rests upon the knowledge and manufacturing base of C4 solder bump chip interconnection, and printed circuit technology infrastructure. The key innovation was the underfill encapsulation between the chip and the laminate which overcame the road-block of low cycle fatigue of C4 solder bump due to large CTE difference between silicon and laminate. The advent of SLC (surface laminar circuit) innovation extends the flip chip technology to higher solder bump density and larger chip I/O expected for future generations of semiconductors. The flip chip packages contain new materials, interfaces, and new processes which in turn govern the mechanical integrity of the packaging module and module card assembly. The increasing pervasiveness of electronic packages requires meeting new sets of environments. It is important to have a good understanding of materials, interface, metrology and mechanics issues related to organic packages, and how to apply this understanding in the modelling of design, process and reliability of flip chip. This paper will deliver an overview of some of the key technical challenges associated with materials and mechanics in FCA (flip-chip attach) assembly on organic carriers.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124316257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550501
D. Zheng, J. Constable
High resolution electrical resistance measurements were used to monitor interconnection failures on PCMCIA test cards. The cards were clamped at the connector end by a fixture which was attached to a shaker. The shaker was excited at the card's first resonant mode to induce interconnect failures. During the vibration, electrical resistance of the interconnects was monitored with sufficient resolution to measure the strain induced resistance change. Three daisy-chained modules on the PCMCIA test card were studied. These modules were: a 176 lead QFP, a 40 lead Type II TSOP, and a 40 lead Type I TSOP. The resistance measuring technique used has been called resistance spectroscopy and had a resolution of better than 1 /spl mu//spl Omega/. Resistance measurements were made on nine test cards, and partial measurements were made on another eleven. A finite element analysis of the surface strain on the card was used to estimate the relative contributions to the measured resistance from the solder joints, leads, and card traces.
{"title":"Analysis of electrical resistance monitoring of PCMCIA interconnection failures","authors":"D. Zheng, J. Constable","doi":"10.1109/ECTC.1996.550501","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550501","url":null,"abstract":"High resolution electrical resistance measurements were used to monitor interconnection failures on PCMCIA test cards. The cards were clamped at the connector end by a fixture which was attached to a shaker. The shaker was excited at the card's first resonant mode to induce interconnect failures. During the vibration, electrical resistance of the interconnects was monitored with sufficient resolution to measure the strain induced resistance change. Three daisy-chained modules on the PCMCIA test card were studied. These modules were: a 176 lead QFP, a 40 lead Type II TSOP, and a 40 lead Type I TSOP. The resistance measuring technique used has been called resistance spectroscopy and had a resolution of better than 1 /spl mu//spl Omega/. Resistance measurements were made on nine test cards, and partial measurements were made on another eleven. A finite element analysis of the surface strain on the card was used to estimate the relative contributions to the measured resistance from the solder joints, leads, and card traces.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125675418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550808
D. Shi, J. Carbin
This paper focuses on significant advances in flip-chip underfill materials via a thorough characterization of the uncured and cured material properties. These characteristics are then translated into what amounts to substantial gains in productivity and reliability. A unique method for determining material flow rates is presented. The data demonstrate the critical relationship between viscosity and flow rate as a function of time and temperature. Material cure rates as a function of time and temperature are also presented using results derived from differential scanning calorimetry or DSC. In addition, the dielectric constant and dissipation factor during the cure process are also measured as an added, more sensitive gauge of the degree of cure. The data from both measurement tools demonstrates what the optimum cure time and temperature parameters are, so as to achieve the optimum glass transition temperature (Tg, generated using DSC). Another critical thermal mechanical property of the underfill material, the linear coefficient of thermal expansion, is characterized with results generated using thermomechanical analysis or TMA. The data is then summarized and translated in terms of its actual impact on manufacturing productivity and component reliability.
{"title":"Advances in flip-chip underfill flow and cure rates and their enhancement of manufacturing processes and component reliability","authors":"D. Shi, J. Carbin","doi":"10.1109/ECTC.1996.550808","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550808","url":null,"abstract":"This paper focuses on significant advances in flip-chip underfill materials via a thorough characterization of the uncured and cured material properties. These characteristics are then translated into what amounts to substantial gains in productivity and reliability. A unique method for determining material flow rates is presented. The data demonstrate the critical relationship between viscosity and flow rate as a function of time and temperature. Material cure rates as a function of time and temperature are also presented using results derived from differential scanning calorimetry or DSC. In addition, the dielectric constant and dissipation factor during the cure process are also measured as an added, more sensitive gauge of the degree of cure. The data from both measurement tools demonstrates what the optimum cure time and temperature parameters are, so as to achieve the optimum glass transition temperature (Tg, generated using DSC). Another critical thermal mechanical property of the underfill material, the linear coefficient of thermal expansion, is characterized with results generated using thermomechanical analysis or TMA. The data is then summarized and translated in terms of its actual impact on manufacturing productivity and component reliability.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134027006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550499
J. Kar, R. Shukla, B. Bhattacharyya
In this paper we have shown a method to evaluate various interconnect technologies by circuit simulations. Two different BGA packages with organic and ceramic substrate, mounted on conventional FR4 board are under consideration. We also have taken a configuration by using MCM interconnect where all the chips are mounted by C4 technology directly on copper polymide on ceramic substrate that has small design features, 25 micron line width and 50 micron space. We have considered the performance of the two different substrates, organic and ceramic substrates with BGA packages compared to MCM interconnect in both T and BUS design.
{"title":"A method to determine the frequency performance and noise margin of various interconnect technologies","authors":"J. Kar, R. Shukla, B. Bhattacharyya","doi":"10.1109/ECTC.1996.550499","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550499","url":null,"abstract":"In this paper we have shown a method to evaluate various interconnect technologies by circuit simulations. Two different BGA packages with organic and ceramic substrate, mounted on conventional FR4 board are under consideration. We also have taken a configuration by using MCM interconnect where all the chips are mounted by C4 technology directly on copper polymide on ceramic substrate that has small design features, 25 micron line width and 50 micron space. We have considered the performance of the two different substrates, organic and ceramic substrates with BGA packages compared to MCM interconnect in both T and BUS design.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132919616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517389
Zemo Yang, Young Kwon
Accurate estimation of the operating temperature of a semiconductor IC device encapsulated within an electronic package is necessary to ensure reliable performance over the life of the product. The common lumped constant Theata JA (/spl phi/ja) characterized in laboratory setups, was found to be too dependent on mounting and environmental conditions to be effective in practical system applications. Two improved compact models of electronic package thermal characteristics, the Bar-Cohen and Lasance, were analyzed for accuracy in particular situations. A further refinement of the Bar-Cohen and Lasance compact models proposed in this paper was found to be more robust and valid in complicated system applications. The less used but effective lumped constant, Theata JL (/spl phi/jl), which describes the junction to package lead relationship, was also studied. It was found to be useful for quick determination of junction temperature in equilibrium system mounted operating condition. Also covered in this work is a discussion from the theoretical network point of view as well as suggestions of modeling methodologies for board mounted plastic packages.
准确估计封装在电子封装中的半导体IC器件的工作温度对于确保产品在整个使用寿命期间的可靠性能是必要的。在实验室设置中常见的集总常数Theata JA (/spl phi/ JA)被发现过于依赖于安装和环境条件而无法在实际系统应用中有效。对Bar-Cohen和Lasance两种改进的电子封装热特性紧凑模型在特定情况下的准确性进行了分析。本文提出的Bar-Cohen和Lasance紧模型的进一步改进在复杂系统应用中具有更强的鲁棒性和有效性。还研究了较少使用但有效的集总常数Theata JL (/spl phi/ JL)，它描述了结与封装引线的关系。结果表明，该方法可用于平衡系统安装工作条件下结温的快速测定。这项工作还涵盖了从理论网络角度的讨论，以及对板安装塑料封装的建模方法的建议。
{"title":"Validation study of compact thermal resistance models of IC packages","authors":"Zemo Yang, Young Kwon","doi":"10.1109/ECTC.1996.517389","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517389","url":null,"abstract":"Accurate estimation of the operating temperature of a semiconductor IC device encapsulated within an electronic package is necessary to ensure reliable performance over the life of the product. The common lumped constant Theata JA (/spl phi/ja) characterized in laboratory setups, was found to be too dependent on mounting and environmental conditions to be effective in practical system applications. Two improved compact models of electronic package thermal characteristics, the Bar-Cohen and Lasance, were analyzed for accuracy in particular situations. A further refinement of the Bar-Cohen and Lasance compact models proposed in this paper was found to be more robust and valid in complicated system applications. The less used but effective lumped constant, Theata JL (/spl phi/jl), which describes the junction to package lead relationship, was also studied. It was found to be useful for quick determination of junction temperature in equilibrium system mounted operating condition. Also covered in this work is a discussion from the theoretical network point of view as well as suggestions of modeling methodologies for board mounted plastic packages.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132195115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550502
R. Dunne, S. Sitaraman
This paper presents parametric studies to assess the thermomechanical reliability of a novel "sandwich" substrate with integrated passives under thermal shock testing. A thermoelastic-plastic finite element analysis is done where FR4 is treated as elastic and orthotropic (with temperature-dependent material properties), and the dielectric polymer and Copper are treated as bilinear elastic-plastic materials. The effect of some geometric and material parameters-FR4 base layer height and insulating layer material-on board warpage and the thermal stress/strain field is discussed, and design guidelines for improved thermo-mechanical integrity of the substrate are suggested.
{"title":"Thermo-mechanical modeling of a novel MCM-DL technology","authors":"R. Dunne, S. Sitaraman","doi":"10.1109/ECTC.1996.550502","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550502","url":null,"abstract":"This paper presents parametric studies to assess the thermomechanical reliability of a novel \"sandwich\" substrate with integrated passives under thermal shock testing. A thermoelastic-plastic finite element analysis is done where FR4 is treated as elastic and orthotropic (with temperature-dependent material properties), and the dielectric polymer and Copper are treated as bilinear elastic-plastic materials. The effect of some geometric and material parameters-FR4 base layer height and insulating layer material-on board warpage and the thermal stress/strain field is discussed, and design guidelines for improved thermo-mechanical integrity of the substrate are suggested.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128839895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517399
M.R. Stiteler, C. Ume, B. Leutz
An automated on-line warpage measurement system for printed wiring boards (PWBs) and printed wiring board assemblies (PWBAs) has been developed. The system is capable of simulating a variety of soldering processes, including the wave soldering process, and performing real-time PWB/PWBA warpage measurements using the shadow moire technique. The system can be used to characterize the warpage behaviour of virtually any PWB/PWBA during the soldering process. Using this system, warpage of PWB test vehicles was measured during simulated wave soldering. The measured warpage varied significantly during wave soldering from that observed both before and after wave soldering. These results help us to understand how the board deforms at every stage of the soldering process.
{"title":"In-process board warpage measurement in a lab scale wave soldering oven","authors":"M.R. Stiteler, C. Ume, B. Leutz","doi":"10.1109/ECTC.1996.517399","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517399","url":null,"abstract":"An automated on-line warpage measurement system for printed wiring boards (PWBs) and printed wiring board assemblies (PWBAs) has been developed. The system is capable of simulating a variety of soldering processes, including the wave soldering process, and performing real-time PWB/PWBA warpage measurements using the shadow moire technique. The system can be used to characterize the warpage behaviour of virtually any PWB/PWBA during the soldering process. Using this system, warpage of PWB test vehicles was measured during simulated wave soldering. The measured warpage varied significantly during wave soldering from that observed both before and after wave soldering. These results help us to understand how the board deforms at every stage of the soldering process.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115809981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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