Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550902
M. Rassaian, M. Beranek
Stress analysis of optical fiber solder bond joints on silicon substrates under thermal cycle loadings was investigated using 2-D and 3-D finite element analyses. Finite element simulations were carried out to investigate the effect of the distance between the fiber and the silicon wall for planar and v-groove solder attachment geometries. It was found that the maximum stress-strain along the interface of the solder and silicon substrate increases as the distance between the fiber and substrate decreases for both geometries. The solder bond strength under thermal loading was also examined to determine the influence of alternative solder material. Favorable results were obtained for 96.5Sn3.5Ag solder as compared to 80Au20Sn solder. Additionally, the reliability of the v-groove geometry is projected to be significantly less than an optimally designed planar bond geometry.
{"title":"Quantitative characterization of optical fiber solder bond joints on silicon","authors":"M. Rassaian, M. Beranek","doi":"10.1109/ECTC.1996.550902","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550902","url":null,"abstract":"Stress analysis of optical fiber solder bond joints on silicon substrates under thermal cycle loadings was investigated using 2-D and 3-D finite element analyses. Finite element simulations were carried out to investigate the effect of the distance between the fiber and the silicon wall for planar and v-groove solder attachment geometries. It was found that the maximum stress-strain along the interface of the solder and silicon substrate increases as the distance between the fiber and substrate decreases for both geometries. The solder bond strength under thermal loading was also examined to determine the influence of alternative solder material. Favorable results were obtained for 96.5Sn3.5Ag solder as compared to 80Au20Sn solder. Additionally, the reliability of the v-groove geometry is projected to be significantly less than an optimally designed planar bond geometry.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128141498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517432
J. Sutherland, G. George, S. van der Green, J. Krusius
Alignment tolerance measurements for flip-chip mounted optoelectronic device substrates have been performed, including separation, tilt, and lateral misalignments. A test assembly was fabricated by joining two metallized and lithographically patterned glass substrates with an array of 76 /spl mu/m dia. 63%Sn-37%Pb solder balls. Measurements indicated poorer alignment than expected, with an average lateral misalignment of 9 /spl mu/m, and worst case height variation of /spl plusmn/8 /spl mu/m for laser diode sites interconnecting to a 12-fiber array. These misalignment values are acceptable for coupling to multimode optical fibers, but not single-mode optical fibers. Work is ongoing to improve the alignment tolerance test assembly to provide more accurate results. A multimode optical coupling model using an analytic beam propagation approach has been validated with measurements of multimode fiber-to-fiber coupling. The model is suitable for fiber-to-fiber, laser diode-to-fiber, fiber-to-rectangular waveguide and fiber-to-photodiode interconnections.
{"title":"Alignment tolerance measurements and optical coupling modeling for optoelectronic array interface assemblies","authors":"J. Sutherland, G. George, S. van der Green, J. Krusius","doi":"10.1109/ECTC.1996.517432","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517432","url":null,"abstract":"Alignment tolerance measurements for flip-chip mounted optoelectronic device substrates have been performed, including separation, tilt, and lateral misalignments. A test assembly was fabricated by joining two metallized and lithographically patterned glass substrates with an array of 76 /spl mu/m dia. 63%Sn-37%Pb solder balls. Measurements indicated poorer alignment than expected, with an average lateral misalignment of 9 /spl mu/m, and worst case height variation of /spl plusmn/8 /spl mu/m for laser diode sites interconnecting to a 12-fiber array. These misalignment values are acceptable for coupling to multimode optical fibers, but not single-mode optical fibers. Work is ongoing to improve the alignment tolerance test assembly to provide more accurate results. A multimode optical coupling model using an analytic beam propagation approach has been validated with measurements of multimode fiber-to-fiber coupling. The model is suitable for fiber-to-fiber, laser diode-to-fiber, fiber-to-rectangular waveguide and fiber-to-photodiode interconnections.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132534018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517445
M. Ohsono, T. Iwane, I. Uchida, N. Tajima, M. Kada
The tape carrier package (TCP) is a mainstream package of LCD driver ICs. With the advancement and proliferation of personal computers and software, it has been necessary to enlarge the LCD screens and improve display quality. The area around the edge of LCD screen must therefore be narrowed to allow the display area to increase and thus provide a maximum display screen within a predetermined module size. Furthermore, display pixels with finer pitch have been developed for higher resolution, since the TCP must have higher output, finer pitch, and be miniaturized for connection to the LCD panels. Thus, in order to reduce the size of the TCP, the chip should be made slimmer, and the pad and inner lead pitch made finer. In a scaled-down TCP, the distance between the I/O terminals and the resin has been reduced. The TCP undergoes shearing stress and heat during thermal bonding while being mounted in the panels, which may result in the encapsulation resin and the tape carrier separating. Consequently, the resin must have high mechanical strength, not only at room temperature but also at higher temperatures. We have developed a high-temperature-resistant, high-mechanical strength resin whose elasticity modulus at high temperatures does not decrease and which adheres well to a tape carrier, and is suitable for use in a 309-output LCD driver with a inner lead pitch of 50 /spl mu/m and able to be mass-produced.
{"title":"The development of a new resin with high mechanical strength at a high temperature for TCP's","authors":"M. Ohsono, T. Iwane, I. Uchida, N. Tajima, M. Kada","doi":"10.1109/ECTC.1996.517445","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517445","url":null,"abstract":"The tape carrier package (TCP) is a mainstream package of LCD driver ICs. With the advancement and proliferation of personal computers and software, it has been necessary to enlarge the LCD screens and improve display quality. The area around the edge of LCD screen must therefore be narrowed to allow the display area to increase and thus provide a maximum display screen within a predetermined module size. Furthermore, display pixels with finer pitch have been developed for higher resolution, since the TCP must have higher output, finer pitch, and be miniaturized for connection to the LCD panels. Thus, in order to reduce the size of the TCP, the chip should be made slimmer, and the pad and inner lead pitch made finer. In a scaled-down TCP, the distance between the I/O terminals and the resin has been reduced. The TCP undergoes shearing stress and heat during thermal bonding while being mounted in the panels, which may result in the encapsulation resin and the tape carrier separating. Consequently, the resin must have high mechanical strength, not only at room temperature but also at higher temperatures. We have developed a high-temperature-resistant, high-mechanical strength resin whose elasticity modulus at high temperatures does not decrease and which adheres well to a tape carrier, and is suitable for use in a 309-output LCD driver with a inner lead pitch of 50 /spl mu/m and able to be mass-produced.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133672219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517455
G. Kroman
This paper presents various thermal management options for a high-performance RISC microprocessor available for controlled-collapse-chip-connection (C4) die attached to a ceramic-ball-grid-array substrate (CBGA), as they apply to air-cooled systems. Computational-fluid dynamics (CFD) methods are used to solve the conjugate heat transfer problems and a thermal test vehicle mounted to a printed-circuit board was used to validate the models. The internal package's contribution is typically less than 18% of the overall junction-to-ambient temperature rise. Of this 18%, approximately 85% is associated with the thermal paste internally sealed; while, the lid and the silicon chip account for the other 15% (approximately equal). For moderate airflow applications in the 1 to 4 m/s, the PowerPC 620 microprocessor will require a relatively large heat sink, approximately 20 times that of the C4/CBGA package, to maintain its die-junction temperature. The proper selection of a thermal interface material is critical in minimizing the thermal contact resistance between the package and the heat sink. Considering, the low interface pressure, the synthetic grease offers the best performance.
{"title":"Thermal management of a C4/CBGA interconnect technology for a high-performance RISC microprocessor: the Motorola PowerPC 620/sup TM/ microprocessor","authors":"G. Kroman","doi":"10.1109/ECTC.1996.517455","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517455","url":null,"abstract":"This paper presents various thermal management options for a high-performance RISC microprocessor available for controlled-collapse-chip-connection (C4) die attached to a ceramic-ball-grid-array substrate (CBGA), as they apply to air-cooled systems. Computational-fluid dynamics (CFD) methods are used to solve the conjugate heat transfer problems and a thermal test vehicle mounted to a printed-circuit board was used to validate the models. The internal package's contribution is typically less than 18% of the overall junction-to-ambient temperature rise. Of this 18%, approximately 85% is associated with the thermal paste internally sealed; while, the lid and the silicon chip account for the other 15% (approximately equal). For moderate airflow applications in the 1 to 4 m/s, the PowerPC 620 microprocessor will require a relatively large heat sink, approximately 20 times that of the C4/CBGA package, to maintain its die-junction temperature. The proper selection of a thermal interface material is critical in minimizing the thermal contact resistance between the package and the heat sink. Considering, the low interface pressure, the synthetic grease offers the best performance.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133793394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550497
S. Ray, H. Hamel, H. Stoller
The recent trend in microprocessor technology is for high speed devices (200-400 MHz) with a large number of simultaneously switching drivers. Other than providing the capability of packaging these devices with high signal I/O, the package also has to provide a low inductance path between the on chip drivers and decoupling capacitors. This is required for a low voltage distribution noise. In this paper, a multi-layer ceramic package with a thin film mesh structure on top of the ceramic substrate is described. Electrical analysis is presented to show that about 20% reduction in voltage distribution noise can be achieved for a high speed, high I/O device utilizing this package.
{"title":"Thin film mesh: a novel approach for noise reduction in high density and high-speed single chip packages","authors":"S. Ray, H. Hamel, H. Stoller","doi":"10.1109/ECTC.1996.550497","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550497","url":null,"abstract":"The recent trend in microprocessor technology is for high speed devices (200-400 MHz) with a large number of simultaneously switching drivers. Other than providing the capability of packaging these devices with high signal I/O, the package also has to provide a low inductance path between the on chip drivers and decoupling capacitors. This is required for a low voltage distribution noise. In this paper, a multi-layer ceramic package with a thin film mesh structure on top of the ceramic substrate is described. Electrical analysis is presented to show that about 20% reduction in voltage distribution noise can be achieved for a high speed, high I/O device utilizing this package.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116144748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550815
K. Scheibner, C. Haynam, E. Worden, B. Esser
Lead, used throughout the electronics industries, typically contains small amounts of radioactive /sup 210/Pb (a daughter product of the planet's ubiquitous /sup 238/U) whose /sup 210/Po daughter emits an /spl alpha/-particle that is known to cause soft errors in electronic circuits. The /sup 210/Pb is not separable by chemical means. This paper describes the generic Atomic Vapor Laser Isotope Separation (AVLIS) process developed at the Lawrence Livermore National Laboratory (LLNL) over the last 20 years, with particular emphasis on recent efforts to develop the process physics and component technologies required to remove the offending /sup 210/Pb using lasers. We have constructed a developmental facility that includes a process laser development area and a test bed for the vaporizer and ion and product collectors. We will be testing much of the equipment and demonstrating pilot-scale AVLIS on a surrogate material later this year. Detection of the very low alpha emission even from commercially available low-alpha lead is challenging. LLNL's detection capabilities will be described. The goal of the development of lead purification technology is to demonstrate the capability in FY97, and to deploy a production machine capable of up to several MT/y of isotopically purified material, possibly beginning in FY98.
{"title":"Laser isotope purification of lead for use in semiconductor chip interconnects","authors":"K. Scheibner, C. Haynam, E. Worden, B. Esser","doi":"10.1109/ECTC.1996.550815","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550815","url":null,"abstract":"Lead, used throughout the electronics industries, typically contains small amounts of radioactive /sup 210/Pb (a daughter product of the planet's ubiquitous /sup 238/U) whose /sup 210/Po daughter emits an /spl alpha/-particle that is known to cause soft errors in electronic circuits. The /sup 210/Pb is not separable by chemical means. This paper describes the generic Atomic Vapor Laser Isotope Separation (AVLIS) process developed at the Lawrence Livermore National Laboratory (LLNL) over the last 20 years, with particular emphasis on recent efforts to develop the process physics and component technologies required to remove the offending /sup 210/Pb using lasers. We have constructed a developmental facility that includes a process laser development area and a test bed for the vaporizer and ion and product collectors. We will be testing much of the equipment and demonstrating pilot-scale AVLIS on a surrogate material later this year. Detection of the very low alpha emission even from commercially available low-alpha lead is challenging. LLNL's detection capabilities will be described. The goal of the development of lead purification technology is to demonstrate the capability in FY97, and to deploy a production machine capable of up to several MT/y of isotopically purified material, possibly beginning in FY98.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124927865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550812
C. Lassen
Flip chip technology includes any combination of techniques that directly mounts a silicon die with its active area face down to a substrate. Flip chip technology has been in use in the electronics industry for over thirty years. Worldwide less than ten companies practice the technology in volume. Over 90% of volume flip chip applications are low leadcount ones for watches, vehicle modules, displays and communications modules. Flip chip will be accelerated by three strong new market drivers: access to high leadcount single chip silicon; use in low profile portable products; proliferation of radio frequency devices. Electrolytic plating and solder reflow assembly techniques will remain dominant, but direct application of solder by stud bumping and related techniques must be carefully watched.
{"title":"Global technical and commercial developments with flip chip technology","authors":"C. Lassen","doi":"10.1109/ECTC.1996.550812","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550812","url":null,"abstract":"Flip chip technology includes any combination of techniques that directly mounts a silicon die with its active area face down to a substrate. Flip chip technology has been in use in the electronics industry for over thirty years. Worldwide less than ten companies practice the technology in volume. Over 90% of volume flip chip applications are low leadcount ones for watches, vehicle modules, displays and communications modules. Flip chip will be accelerated by three strong new market drivers: access to high leadcount single chip silicon; use in low profile portable products; proliferation of radio frequency devices. Electrolytic plating and solder reflow assembly techniques will remain dominant, but direct application of solder by stud bumping and related techniques must be carefully watched.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122038838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550895
S. Baba, Y. Tomita, M. Matsuo, H. Matsushima, N. Ueda, O. Nakagawa
A unique molded Chip Scale Package (CSP) associated 1024 pin counts has been developed. The design and process have been optimized in order to achieve high mount density, enhanced electrical characteristic and cost competitiveness. Also, the reliability testing was performed on thermal cycling and moisture induced crack resistivity. Finally, enhanced electrical and thermal characteristics were calculated.
{"title":"Molded chip scale package for high pin count","authors":"S. Baba, Y. Tomita, M. Matsuo, H. Matsushima, N. Ueda, O. Nakagawa","doi":"10.1109/ECTC.1996.550895","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550895","url":null,"abstract":"A unique molded Chip Scale Package (CSP) associated 1024 pin counts has been developed. The design and process have been optimized in order to achieve high mount density, enhanced electrical characteristic and cost competitiveness. Also, the reliability testing was performed on thermal cycling and moisture induced crack resistivity. Finally, enhanced electrical and thermal characteristics were calculated.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"335 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122134954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550875
M. Fukuda, F. Ichikawa, H. Sato, Y. Hibino, K. Moriwaki, S. Tohno, T. Sugie, J. Yoshida
Two kinds of plastic molded laser modules, the coaxial type and the board type, are developed aiming at lower cost laser modules. Under various environmental and endurance tests, these modules show potential for high reliability. The performance of these modules seem comparable to that of hermetically sealed modules used in commercial transmission systems. They are potentially suitable for low cost optical sources in transmission systems.
{"title":"Plastic packaging of semiconductor laser diodes","authors":"M. Fukuda, F. Ichikawa, H. Sato, Y. Hibino, K. Moriwaki, S. Tohno, T. Sugie, J. Yoshida","doi":"10.1109/ECTC.1996.550875","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550875","url":null,"abstract":"Two kinds of plastic molded laser modules, the coaxial type and the board type, are developed aiming at lower cost laser modules. Under various environmental and endurance tests, these modules show potential for high reliability. The performance of these modules seem comparable to that of hermetically sealed modules used in commercial transmission systems. They are potentially suitable for low cost optical sources in transmission systems.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114955424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517463
S. Mulgaonker, G. Hawkins, K. Ramakrishna, A. Mawer, E. Winkler
ULSI devices continue to evolve in the direction of higher pincounts, powers and clock speeds. Current usage of the (cavity up) PBGA has been limited to I/Os of 150-360 and powers of 2-3 W. There is a need to extend the performance characteristics of the PBGA as a low cost packaging alternative for evolving devices. This study reports on the thermal performance of a 400 I/O PBGA design for powers of 7-10 W for PC/Workstation applications. Thermal performance is improved by lowering the resistances to heat flow via junction to board (R/sub jb/), junction to case (R/sub jc/) and case to ambient (R/sub ca/). The case to ambient resistance is lowered by using a heat sink attached to the package, evaluated at forced air flow of 1 m/s, typical for workstation environments. A PBGA package has been developed for a 12.7 mm die on a 29 mm, 2 metal layer substrate. The design utilizes thermal vias to lower the R/sub jb/. R/sub jc/ is lowered by decreasing the mold compound thickness. Design parameters for these features are derived and optimized through finite element simulations. Attaching a heatsink to the package is critical for extending the power dissipation from 2-3 W to the 7+ W range. The peripheral area around the PBGA makes it naturally suited for a demountable heatsink attach. An easy clip-on method of heatsink attach is developed as an alternative to the current time-consuming practice of epoxy bonding. Spring loaded clip attach prototypes are designed to minimize interfacial resistance to 0.75/spl deg/C/W when the heatsink is in dry contact with the mold compound.
{"title":"PBGA for high power: extending the thermal envelope","authors":"S. Mulgaonker, G. Hawkins, K. Ramakrishna, A. Mawer, E. Winkler","doi":"10.1109/ECTC.1996.517463","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517463","url":null,"abstract":"ULSI devices continue to evolve in the direction of higher pincounts, powers and clock speeds. Current usage of the (cavity up) PBGA has been limited to I/Os of 150-360 and powers of 2-3 W. There is a need to extend the performance characteristics of the PBGA as a low cost packaging alternative for evolving devices. This study reports on the thermal performance of a 400 I/O PBGA design for powers of 7-10 W for PC/Workstation applications. Thermal performance is improved by lowering the resistances to heat flow via junction to board (R/sub jb/), junction to case (R/sub jc/) and case to ambient (R/sub ca/). The case to ambient resistance is lowered by using a heat sink attached to the package, evaluated at forced air flow of 1 m/s, typical for workstation environments. A PBGA package has been developed for a 12.7 mm die on a 29 mm, 2 metal layer substrate. The design utilizes thermal vias to lower the R/sub jb/. R/sub jc/ is lowered by decreasing the mold compound thickness. Design parameters for these features are derived and optimized through finite element simulations. Attaching a heatsink to the package is critical for extending the power dissipation from 2-3 W to the 7+ W range. The peripheral area around the PBGA makes it naturally suited for a demountable heatsink attach. An easy clip-on method of heatsink attach is developed as an alternative to the current time-consuming practice of epoxy bonding. Spring loaded clip attach prototypes are designed to minimize interfacial resistance to 0.75/spl deg/C/W when the heatsink is in dry contact with the mold compound.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125426148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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