Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757974
T. Baldauf, A. Wei, R. Illgen, S. Flachowsky, T. Herrmann, T. Feudel, J. Hontschel, M. Horstmann, W. Klix, R. Stenzel
A Tri-Gate structure built into a planar 22 nm bulk process was investigated by 3-D device simulations (Sentaurus D-2010). The planar process flow sequence was extended with extra Tri-Gate patterning, but otherwise all implants were shared, as could be done in simultaneous processing of planar and Tri-Gate CMOS. A comparison of planar and Tri-Gate transistors with the same planar dopant profiles shows a substantial improvement of subthreshold slope, DIBL, and VT-rolloff for Tri-Gates. The electrical behavior of the Tri-Gate transistor has been studied for various Tri-Gate heights and widths. A large space of Tri-Gate dimensions outperformed planar in terms of electrostatics and ION-IOFF characteristics.
{"title":"Simulation and optimization of Tri-Gates in a 22 nm hybrid Tri-Gate/planar process","authors":"T. Baldauf, A. Wei, R. Illgen, S. Flachowsky, T. Herrmann, T. Feudel, J. Hontschel, M. Horstmann, W. Klix, R. Stenzel","doi":"10.1109/ULIS.2011.5757974","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757974","url":null,"abstract":"A Tri-Gate structure built into a planar 22 nm bulk process was investigated by 3-D device simulations (Sentaurus D-2010). The planar process flow sequence was extended with extra Tri-Gate patterning, but otherwise all implants were shared, as could be done in simultaneous processing of planar and Tri-Gate CMOS. A comparison of planar and Tri-Gate transistors with the same planar dopant profiles shows a substantial improvement of subthreshold slope, DIBL, and VT-rolloff for Tri-Gates. The electrical behavior of the Tri-Gate transistor has been studied for various Tri-Gate heights and widths. A large space of Tri-Gate dimensions outperformed planar in terms of electrostatics and ION-IOFF characteristics.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124422428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758006
T. Holtij, M. Schwarz, A. Kloes, B. Iñíguez
Since DG-MOSFETs reached channel length down to 20nm, the parasitic source/drain resistances get more important and can't be neglected. To calculate these resistances in such devices a two-dimensional model in analytical closed-form has been derived by using the conformal mapping technique. Additionally, the model is able to predict the parasitic resistances for DG-MOSFETs with raised source drain (RSD) structures and/or wrapped contacts. The influence of source/drain geometries on access resistances is accurately described and a bias dependency is obtained by introducing two fitting parameters. The model is compared with the parasitic source/drain resistances determined from TCAD device simulations.
{"title":"2D Analytical calculation of the source/drain access resistance in DG-MOSFET structures","authors":"T. Holtij, M. Schwarz, A. Kloes, B. Iñíguez","doi":"10.1109/ULIS.2011.5758006","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758006","url":null,"abstract":"Since DG-MOSFETs reached channel length down to 20nm, the parasitic source/drain resistances get more important and can't be neglected. To calculate these resistances in such devices a two-dimensional model in analytical closed-form has been derived by using the conformal mapping technique. Additionally, the model is able to predict the parasitic resistances for DG-MOSFETs with raised source drain (RSD) structures and/or wrapped contacts. The influence of source/drain geometries on access resistances is accurately described and a bias dependency is obtained by introducing two fitting parameters. The model is compared with the parasitic source/drain resistances determined from TCAD device simulations.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115266322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757983
Martin Paul Vaughan, F. Murphy-Armando, S. Fahy
A method is developed to obtain the alloy scattering coefficients from first-principles band structure calculations. It is found that the scattering matrix can be decomposed into two additive components: a chemical part due to atomic substitution and a part due to ionic relaxation. The method is then applied to find the intra-and inter-valley electron scattering rates for substitutional carbon in silicon. Intravalley scattering is found to be the dominant process.
{"title":"Alloy scattering of substitutional carbon in silicon: A first principles approach","authors":"Martin Paul Vaughan, F. Murphy-Armando, S. Fahy","doi":"10.1109/ULIS.2011.5757983","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757983","url":null,"abstract":"A method is developed to obtain the alloy scattering coefficients from first-principles band structure calculations. It is found that the scattering matrix can be decomposed into two additive components: a chemical part due to atomic substitution and a part due to ionic relaxation. The method is then applied to find the intra-and inter-valley electron scattering rates for substitutional carbon in silicon. Intravalley scattering is found to be the dominant process.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128351346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757996
Michael Schmidt, H. Gottlob, J. Bolten, T. Wahlbrink, Heinrich Kurz
Gadolinium-silicate (GdSiO) as high-k dielectric in sub 10nm gate first nanowire (NW) nMOSFETs is investigated. NW- and UTB- nMOSFETs with conventional SiO2/Poly-Si gate stacks have been fabricated and compared with GdSiO/TiN NW nMOSFETs. Specific nMOSFETs with multiple NWs in parallel have been used to extract the effective mobility by split-CV method and to eliminate the series resistance to correct the measured data.
{"title":"Mobility extraction in sub 10nm nanowire nMOSFETs with gadolinium-silicate as gate dielectric","authors":"Michael Schmidt, H. Gottlob, J. Bolten, T. Wahlbrink, Heinrich Kurz","doi":"10.1109/ULIS.2011.5757996","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757996","url":null,"abstract":"Gadolinium-silicate (GdSiO) as high-k dielectric in sub 10nm gate first nanowire (NW) nMOSFETs is investigated. NW- and UTB- nMOSFETs with conventional SiO2/Poly-Si gate stacks have been fabricated and compared with GdSiO/TiN NW nMOSFETs. Specific nMOSFETs with multiple NWs in parallel have been used to extract the effective mobility by split-CV method and to eliminate the series resistance to correct the measured data.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116705680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757953
C. Berti, S. Furini, E. Sangiorgi, C. Fiegna
In this work we present a three-dimensional numerical simulation technique for the study of ion permeation through ion channels embedded in silicon membranes, that can be exploited for sensor applications. The results of this work clarify how the charges embedded in the protein forming the ion channel can influence ionic conductance through silicon membrane slabs, controlling the channel conductance and selectivity with respect to ionic species.
{"title":"Brownian dynamics simulation of ion channels embedded in silicon membranes for sensor applications","authors":"C. Berti, S. Furini, E. Sangiorgi, C. Fiegna","doi":"10.1109/ULIS.2011.5757953","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757953","url":null,"abstract":"In this work we present a three-dimensional numerical simulation technique for the study of ion permeation through ion channels embedded in silicon membranes, that can be exploited for sensor applications. The results of this work clarify how the charges embedded in the protein forming the ion channel can influence ionic conductance through silicon membrane slabs, controlling the channel conductance and selectivity with respect to ionic species.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"157 16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126928834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757958
T. Hiramoto
The silicon MOS transistors for VLSI have been scaled down for more than forty years in order to attain higher speed, lower power, higher integration, and lower cost. The gate length is now less than 30 nm. The silicon devices are certainly in the nanometer regime. Fig. 1 shows technology nodes and gate length according to ITRS [1]. It is predicted in the 2009 version of ITRS that the gate length will become less than 10 nm in 2021 in production. In the research level, a CMOS device with 3.8nm gate length has already been reported [2]. However, there are a lot of technical barriers to realize the 10nm-scale CMOS devices. It is now well recognized that simple scaling of bulk MOSFETs will fail in the nanometer regime. Every effort to extend the CMOS platform to future information technologies is being made. In this talk, transistor evolution for further CMOS extension is presented. Conventional planar bulk MOSFETs are compared with emerging fully-depleted SOI MOSFETs and nanowire MOSFETs in terms of short channel effects, carrier transport, and variability, and the advantages of new channel structures are discussed.
{"title":"From bulk toward FDSOI and silicon nanowire transistors: Challenges and opportunities","authors":"T. Hiramoto","doi":"10.1109/ULIS.2011.5757958","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757958","url":null,"abstract":"The silicon MOS transistors for VLSI have been scaled down for more than forty years in order to attain higher speed, lower power, higher integration, and lower cost. The gate length is now less than 30 nm. The silicon devices are certainly in the nanometer regime. Fig. 1 shows technology nodes and gate length according to ITRS [1]. It is predicted in the 2009 version of ITRS that the gate length will become less than 10 nm in 2021 in production. In the research level, a CMOS device with 3.8nm gate length has already been reported [2]. However, there are a lot of technical barriers to realize the 10nm-scale CMOS devices. It is now well recognized that simple scaling of bulk MOSFETs will fail in the nanometer regime. Every effort to extend the CMOS platform to future information technologies is being made. In this talk, transistor evolution for further CMOS extension is presented. Conventional planar bulk MOSFETs are compared with emerging fully-depleted SOI MOSFETs and nanowire MOSFETs in terms of short channel effects, carrier transport, and variability, and the advantages of new channel structures are discussed.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116654589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758009
S. Makovejev, V. Kilchytska, M. Arshad, D. Flandre, F. Andrieu, O. Faynot, S. Olsen, J. Raskin
Self-heating and substrate effects are discussed and qualitatively compared in the ultra-thin body ultra-thin BOX (UTB2) devices without a ground plane. Ultra-thin body is aggravating thermal properties of the devices due to the interface effects. Ultra-thin BOX (10 nm) improves heat dissipation from the channel to the bulk silicon substrate but also results in strongly pronounced substrate effects. It is observed that output conductance degradation in the UTB2 devices due to the substrate effects can be as strong as degradation due to the self-heating.
{"title":"Self-heating and substrate effects in ultra-thin body ultra-thin BOX devices","authors":"S. Makovejev, V. Kilchytska, M. Arshad, D. Flandre, F. Andrieu, O. Faynot, S. Olsen, J. Raskin","doi":"10.1109/ULIS.2011.5758009","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758009","url":null,"abstract":"Self-heating and substrate effects are discussed and qualitatively compared in the ultra-thin body ultra-thin BOX (UTB2) devices without a ground plane. Ultra-thin body is aggravating thermal properties of the devices due to the interface effects. Ultra-thin BOX (10 nm) improves heat dissipation from the channel to the bulk silicon substrate but also results in strongly pronounced substrate effects. It is observed that output conductance degradation in the UTB2 devices due to the substrate effects can be as strong as degradation due to the self-heating.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133365428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757987
F. Murphy-Armando, S. Fahy
First-principles electronic structure methods are used to predict the rate of n-type carrier scattering due to phonons in highly-strained Ge. We show that strains achievable in nanoscale structures, where Ge becomes a direct band-gap semiconductor, cause the phonon-limited mobility to be enhanced by hundreds of times that of unstrained Ge, and over a thousand times that of Si.
{"title":"Giant mobility enhancement in highly strained, direct gap Ge","authors":"F. Murphy-Armando, S. Fahy","doi":"10.1109/ULIS.2011.5757987","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757987","url":null,"abstract":"First-principles electronic structure methods are used to predict the rate of n-type carrier scattering due to phonons in highly-strained Ge. We show that strains achievable in nanoscale structures, where Ge becomes a direct band-gap semiconductor, cause the phonon-limited mobility to be enhanced by hundreds of times that of unstrained Ge, and over a thousand times that of Si.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129859420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758000
G. Lucovsky, L. Miotti, D. Zeller, C. Adamo, D. Scholm
Alloy induced multivalency in transition metal oxides increases device functionality. Effects include insulator to metal transitions in the d0 perovskites (i) GdScO3, by substitution of tetravalent Ti trivalent for Sc, and (ii) LaMnO3 by alloy substitution of trivalent La and divalent Sr for trivalent La. Substituion of Ti3+ for Sc3+ on the ScO2 planes leads to hopping induced multivalencey for both Ti and Sc, but only for Ti compositions above a percolation threshold. The formation of La1−xSrxMnO3 alloys leads to mixed valence of the Mn-atoms: Mn3+ in the LaMnO3 fraction, and Mn4+ in the SrMnO3 fraction. Spectroscopic detection is based on charge transfer multiplet theory applied to Ti, Sc and Mn L2,3 spectra were multivalent charge states increase the number of spectral features. Multivalency also occurs suboxide alloys such as TiO2−x in a composition range: TiO2 > TiO2−x > TiO1.5. These alloys have a mix of Ti4+ and Ti3+ local bonding states, but due to hopping transport, the mix includes Ti2+. One important aspect of controlled multivalency is that it provides a way of changing and/or controlling the density of O-vacancy defects. Electrons can be injected into the oxide negative ion states ion states from Si, Ge, and other semiconductors, as well as metals with different offset energies [1]. The two terminal devices with asymmetric current-voltage charateristics providing options for memory devices.
{"title":"X-ray absorption studies of elemental and complex transition metal (TM) oxides: Differences between: (i) Chemical, and (ii) Local site symmetry multivalency","authors":"G. Lucovsky, L. Miotti, D. Zeller, C. Adamo, D. Scholm","doi":"10.1109/ULIS.2011.5758000","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758000","url":null,"abstract":"Alloy induced multivalency in transition metal oxides increases device functionality. Effects include insulator to metal transitions in the d<sup>0</sup> perovskites (i) GdScO<inf>3</inf>, by substitution of tetravalent Ti trivalent for Sc, and (ii) LaMnO<inf>3</inf> by alloy substitution of trivalent La and divalent Sr for trivalent La. Substituion of Ti<sup>3+</sup> for Sc<sup>3+</sup> on the ScO<inf>2</inf> planes leads to hopping induced multivalencey for both Ti and Sc, but only for Ti compositions above a percolation threshold. The formation of La<inf>1−x</inf>Sr<inf>x</inf>MnO<inf>3</inf> alloys leads to mixed valence of the Mn-atoms: Mn<sup>3+</sup> in the LaMnO<inf>3</inf> fraction, and Mn<sup>4+</sup> in the SrMnO<inf>3</inf> fraction. Spectroscopic detection is based on charge transfer multiplet theory applied to Ti, Sc and Mn L<inf>2,3</inf> spectra were multivalent charge states increase the number of spectral features. Multivalency also occurs suboxide alloys such as TiO<inf>2−x</inf> in a composition range: TiO<inf>2</inf> > TiO<inf>2−x</inf> > TiO<inf>1.5</inf>. These alloys have a mix of Ti<sup>4+</sup> and Ti<sup>3+</sup> local bonding states, but due to hopping transport, the mix includes Ti<sup>2+</sup>. One important aspect of controlled multivalency is that it provides a way of changing and/or controlling the density of O-vacancy defects. Electrons can be injected into the oxide negative ion states ion states from Si, Ge, and other semiconductors, as well as metals with different offset energies [1]. The two terminal devices with asymmetric current-voltage charateristics providing options for memory devices.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128890577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758016
E. Miranda, D. Jiménez, J. Suñé
A simple analytic model for the progressive breakdown (BD) dynamics of ultrathin) gate oxides is presented. It is shown how the interplay between series and parallel resistances that represent the breakdown path and its surroundings leads to a sigmoidal I-t characteristic compatible with experimental data. The analysis is carried out using the Lyapunov exponent and the potential function associated with the logistic equation for the leakage current. The roles played by the initial current value and the system's attractor in the breakdown trajectories are discussed.
{"title":"Toy model for the progressive breakdown dynamics of ultrathin gate dielectrics","authors":"E. Miranda, D. Jiménez, J. Suñé","doi":"10.1109/ULIS.2011.5758016","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758016","url":null,"abstract":"A simple analytic model for the progressive breakdown (BD) dynamics of ultrathin) gate oxides is presented. It is shown how the interplay between series and parallel resistances that represent the breakdown path and its surroundings leads to a sigmoidal I-t characteristic compatible with experimental data. The analysis is carried out using the Lyapunov exponent and the potential function associated with the logistic equation for the leakage current. The roles played by the initial current value and the system's attractor in the breakdown trajectories are discussed.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116967787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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